CN1197443C - 带有弹性封装的一电子器件的组件 - Google Patents

带有弹性封装的一电子器件的组件 Download PDF

Info

Publication number
CN1197443C
CN1197443C CNB998079707A CN99807970A CN1197443C CN 1197443 C CN1197443 C CN 1197443C CN B998079707 A CNB998079707 A CN B998079707A CN 99807970 A CN99807970 A CN 99807970A CN 1197443 C CN1197443 C CN 1197443C
Authority
CN
China
Prior art keywords
substrate
socket
semiconductor device
equipment
socket substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB998079707A
Other languages
English (en)
Other versions
CN1307793A (zh
Inventor
D·V·佩德森
B·N·埃尔德里奇
I·Y·坎达斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FormFactor Inc
Original Assignee
FormFactor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/108,163 external-priority patent/US6033935A/en
Application filed by FormFactor Inc filed Critical FormFactor Inc
Publication of CN1307793A publication Critical patent/CN1307793A/zh
Application granted granted Critical
Publication of CN1197443C publication Critical patent/CN1197443C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
    • B23K20/004—Wire welding
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • H05K3/326—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • C25D21/02—Heating or cooling
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/22—Electroplating combined with mechanical treatment during the deposition
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/01—Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889—Interfaces, e.g. between probe and tester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/1075—Shape details
    • H05K2201/10757—Bent leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/1075—Shape details
    • H05K2201/10878—Means for retention of a lead in a hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/10886—Other details
    • H05K2201/10909—Materials of terminal, e.g. of leads or electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/10886—Other details
    • H05K2201/10946—Leads attached onto leadless component after manufacturing the component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

本发明揭示了一种用于测试半导体装置的设备，该设备包括：多个半导体装置，该半导体装置各具有多个细长弹性连接件；一支承基底，该支承基底具有供测试信号来去半导体或者用的多个第一电连接件；多个接线匣基底，各接线匣基底的第一侧固定至支承基底，接线匣基底各具有置于接线匣基底的第二侧上的、用于接纳多个细长弹性连接件的其中之一的多个接线匣；多个导电通道，该导电通道分别置于接线匣基底的其中之一的第二侧上，且与接线匣的其中之一电连接；多个第二电连接件，第二电连接件用于使导电通道分别与第一电连接件相连接；以及一推压机构，该推压机构用于将半导体装置推压在接线匣基底上，以便细长弹性连接件与接线匣形成电连接。

Description

带有弹性封装的一电子器件的组件
技术领域
本发明涉及用于电子器件的接线匣，特别地用于与带有弹性封装(MicroSpringTM接点)的半导体相匹配。该接线匣可用于接触从单个装置到整个晶片的各种结构的一装置，并可用于该装置的固定、接触、测试、熔焊、以及常规运作。
背景技术
许多年来芯片封装(chip scale packaging)的目标一直是本行业中的热点研究问题。一个非常有前景的技术包括将一小型弹性件固定在适当的基底上，并使用这些元件在运行的装置和其他电路之间形成接触。
发明人KHANDROS于93年11月16日递交的第08/152,812号已知的美国专利申请(95年12月19日授权USP4,576,211)及其对应的正在审批中的于95年6月1日递交的第08/457,479号(状态：审批中)和95年12月11日递交的第08/570,230号(状态：审批中)已知的“分案”美国专利申请揭示了形成用于微电子应用的弹性互连件的方法，该方法包括将一柔韧的细长芯件(例如导线“杆”或“骨干”)的一个端部安装在一电子器件上的接线端上，用具有预定组合厚度的一种或多种材料的“护套”涂覆该柔韧的芯件和接线端的相邻表面，获得强度和弹性模量以确保所得到的弹性接点具有预定的受力偏移的特性。芯件的典型材料包括金。涂层的典型材料包括镍及其合金。所得到的弹性接触件适于在两个或多个包括半导体装置的电子器件之间形成压力连接或可拆卸的连接。
发明人KHANDROS和MATHIEU于94年11月15日递交的已知的正在审批中的第08/340,144号美国专利申请及其相应的于94年11月16递交的PCT专利申请PCT/US94/13373(WO95/14314，95年5月26日公开)揭示了上述弹性接触件的多种应用，例如形成一插入物。该申请还揭示了用以在弹性接触件的端部制作接触衬垫(接触末端结构)的技术。
发明人ELDRIDGE、GRUBE、KHANDROS和MATHIEU于95年5月26日递交的已知的正在审批中的第08/452,225号美国专利申请及其相应的于95年11月13递交的PCT专利申请PCT/US95/14909(WO96/17278，96年6月6日公开)揭示了用以制造弹性接触件例如组合互连件、以及用以制造接触末端结构和将接触末端结构安装在该组合互连件的自由端(末端)的附加技术和冶金术。
发明人ELDRIDGE、GRUBE、KHANDROS和MATHIEU于95年11月15日递交的已知的正在审批中的第08/558,332号美国专利申请及其相应的于95年11月15递交的PCT专利申请US95/14885揭示了用以制造弹性接触结构的方法，其特别适于制造直接位于半导体装置之上的弹性接触件。
本发明致力于且特别适于以良好的间距形成当今微电子装置的相互连接。在此所使用的“良好的间距”一词意味着微电子装置具有以小于约5密尔、例如2.5密尔或65微米的间距设置的接线端(在本发明中是指它们的互连件)。但是本发明可用于带有任何间距(例如毫米级或更大)的装置，但是特别适用于小于大约15密尔(375微米)的间距。在一个有用的例子中，一装置可安装有以大约10密尔(250微米)的间距位于一个区域阵列中的若干弹性件阵列。一相应的连接件具有与弹性件的接触区域相同的间距。例如，一相应的接线匣应具有一相应样式的带有相同间距的截获衬垫，以接纳弹性件的阵列。
在所描述的主要内容中，此后，可插入地接纳的电子器件是半导体装置，它具有为细长互连件的互连件，更具体说是从其表面上延伸出的弹性接触件。在此，具有安装在那里的弹性接触件的半导体装置被称之为弹性的半导体装置。
一弹性半导体装置能够以两种主要方式中的一种与一个互连基底相互连接。可以永久地连接，例如通过将弹性接触件的自由端焊接在互连基底例如一印刷电路板的相应的接线端上。另外，也可以可逆地连接于接线端，例如简单地通过对着互连基底推压弹性半导体装置，以在接线端和弹性接触件的接触部分之间形成压力连接。这样的可逆的压力连接可描述为用于弹性半导体装置的自身插入。
能够从与互连基底的压力连接状态移开一弹性半导体装置的能力在替换或升级弹性半导体装置的情况下非常有用，可简单地通过与弹性半导体装置形成可逆的连接获得一非常有益的目的。这对于测试弹性半导体装置特别有用。这对于暂时或永久安装在一系统的互连基底上也是有用的，以便(1)熔焊弹性的半导体装置，或者(2)确定该弹性的半导体装置是否达到其规格。总的来说，这可通过与弹性接触件形成压力连接来完成。这样的接触可以具有依靠接触力等的可松弛的限制。本发明揭示了用以插入到弹性半导体装置的多种技术。
发明人DOZIER、ELDRIDGE、GRUBE、KHANDROS和MATHIEU于95年10月18日递交的已知的正在审批中的第08/533,385号美国专利申请及其相应的于95年11月13递交的PCT专利申请US95/14842揭示了具有弹性接触件的接线匣基底，用于与一运行的半导体装置形成可逆的连接。该接线匣本身又被固定和连接于电子电路。从最为广义的角度讲，本发明致力于可视为类似，但却是可逆的情形，即，使具有弹性接触件的电子器件与接线匣基底形成可逆的连接。
发明人KHANDROS和PEDERSEN于97年6月15日递交的已知的正在审批中的第08/784,862号美国专利申请及其对应的于97年5月15递交的PCT专利申请US97/08604揭示了用于晶片级熔焊和测试的一系统，其中多个相对较小的运行的电子器件例如特别应用的集成电路(ASICs)安装在一相对较大的互连基底上。多个半导体装置放置在被测试的晶片(WUT)上。
弹性接触件从半导体装置的表面延伸且是适于，但并不局限于此，自由地竖立的细长的互连件，例如揭示在上述已知的审批中的于95年5月26日递交的第08/452,225号美国专利及其对应的于95年11月13日递交的PCT专利申请US95/14909中的互连件。如在此的图3B所示，多个倒置棱锥形的凹口从其表面延伸进入到ASIC中。金属层施加至这些凹口的侧壁，与ASIC的电路元件建立电性连通。
在使用中，一ASIC和WUT被放置在一起，WUT上的弹性接触件的末端进入到ASIC中的凹口中，且以足够大的力来啮合凹口的侧壁，以确保可靠的电性压力连接。如在此的图3C所示，另外，每个ASIC都具有多个以传统形式形成在其前表面上的衬垫(接线端)，以及一层绝缘材料。这样的硅模子可被微加工成具有从其内延伸且与接触衬垫对齐的多个小孔，且可以设置在ASIC的前表面上。该绝缘材料层提供了与形成在ASICs中的凹口可相比较的“截获”能力。这些专利申请的图5A-5C示出形成通过ASIC的导电通路的技术，其中凹口(第一和第二孔部分)形成在ASIC的两侧，直到它们变得彼此相邻。而后，设置一导电层(例如钨、钛-钨等等)，例如通过喷涂在第一和第二孔部分中，从而得到延伸进入到第一孔部分中的第一导电层部分和延伸进入到第二孔部分中的第二导电层部分。当第一和第二孔部分位于硅基底例如一晶片的相反侧上时，这将特别有意义。而后施加大量的导电材料(例如金、镍等等)以连接(桥接)两个孔部分中的导电层。该大量的导电材料适于通过电镀来施加。
发明人ELDRIDGE、GRUBE、KHANDROS、MATHIEU、PEDERSEN和STADT于1998年6月30日递交的已知的审批中的第09/108,163号美国专利申请揭示了用以与一弹性半导体装置形成可逆连接的多种技术，用于熔焊该弹性的半导体装置并确定该弹性的半导体装置是否能够达到其规格要求。例如，该专利申请的图2示出一技术，其中对着一互连基底例如一印刷电路板(PCB)推压该弹性的半导体装置，致使弹性接触件的末端与PCB上的相应的多个接线端形成压力接触，以在此建立压力连接。例如，该专利申请的图4示出一技术，其中弹性接触件的端部被插入到互连基底例如印刷电路板的电镀的通孔接线端中。例如，该专利申请的图5A示出一技术，其中弹性接触件的端部与一互连基底的多个凹入的接线端中的相应一个相接触。该凹入的接线端形成类似电镀的通孔，它具有圆锥形或棱锥形的上部，该棱锥形的基部位于互连基底的上表面处，且其顶点位于该互连基底中。该专利申请的图5B示出凹入的诸接线端，每个接线端都是半球形，该半球形的基部位于互连基底的上表面处，且其顶端位于该互连基底中。该专利申请的图5C示出诸凹入的接线端，该接线端具有梯形实心的上部，该梯形相对较宽的基部位于互连基底的上表面处，且其相对较窄的基部位于互连基底中。在该专利申请的图5A、5B和5C的每个例子中，弹性接触结构的末端从最宽部进入到凹入的接线端中，由此能够更容易地进入且引导或“截获”带有接线端的弹性接触件的端部。
发明内容
因此，本发明的目的在于提供一种能克服上述缺陷的用于测试半导体装置的设备。
为实现上述目的，本发明提供了一种用于测试半导体装置的设备，该设备包括：多个半导体装置，该半导体装置各具有多个细长弹性连接件；一支承基底，该支承基底具有供测试信号来去半导体或者用的多个第一电连接件；多个接线匣基底，各接线匣基底的第一侧固定至支承基底，接线匣基底各具有置于接线匣基底的第二侧上的、用于接纳多个细长弹性连接件的其中之一的多个接线匣；多个导电通道，该导电通道分别置于接线匣基底的其中之一的第二侧上，且与接线匣的其中之一电连接；多个第二电连接件，第二电连接件用于使导电通道分别与第一电连接件相连接；以及一推压机构，该推压机构用于将半导体装置推压在接线匣基底上，以便细长弹性连接件与接线匣形成电连接。
较佳地，多个半导体装置是非单个(unsingulated)半导体晶片的模子。
较佳地，接线匣基底分别与其中一个模子相对应。
较佳地，支承基底是探测卡组件的一部分。
较佳地，支承基底通过一插入物与探测卡电连接，并且支承基底、插入物以及探测卡构成了探测卡组件。
较佳地，半导体装置是未包装的单个半导体模子。
较佳地，还包括设置用来控制半导体装置的温度的温控装置。
较佳地，温控装置包括：与半导体装置热接触的第一热吸盘；以及与接线匣基底热接触的第二热吸盘。
较佳地，接线匣基底成行地设置在支承基底上，并且该设备还包括置于支承基底上的多个能源线，能源线分别与其中一行接线匣基底相对应，并向该行中的每个接线匣基底提供能量。
较佳地，还包括多个绝缘电阻器，每个绝缘电阻器置于其中一个能源线与其中一个接线匣基底之间。
较佳地，推压机构包括测试头或者真空吸盘的其中之一。
较佳地，多个第二电连接件包括多根连接线，每根连接线与其中一个导电通道以及其中一个第一电连接件相连。
较佳地，接线匣包括蚀刻到一相应的接线匣基底的第二侧中的凹坑。
较佳地，接线匣基底包括硅。
从以下的说明和附图中可更完全地理解本发明的这些和其他目的和优点，以及一说明性实施例的细节。
附图说明
现详尽地参考本发明的较佳实施例，其例子示出在附图中。尽管本发明被描述在这些较佳实施例中，但应理解到，无意将本发明的精神和范围限制于这些具体的实施例。在此的侧视图中，为了清楚起见，侧视图中常常只有一部分为剖视，许多部分可为立体图。在此的附图中，为了清楚起见，某些元件的尺寸常常被放大(相对图中的其他元件不成比例)。
图1A是按照本发明制作一弹性接触件的一个步骤的侧剖视图，该弹性接触件是一组合的互连件。
图1B是按照本发明制作图1A所示弹性接触件的另一步骤的侧剖视图。
图1C是按照本发明在图1B步骤后的一弹性接触件的侧剖视图。
图2是按照本发明推动一弹性半导体装置与一互连基底的平坦的截获衬垫(接线端)相接触的一侧剖视图。
图2A是示出按照本发明推动一弹性半导体装置与一互连基底的平坦的截获衬垫相接触的一侧剖视图。
图2B是示出按照本发明推动一弹性半导体装置与一互连基底的平坦的接线端相接触的一侧剖视图。
图2C是示出按照本发明推动一弹性半导体装置与一互连基底的凹入的半球形接线端相接触的一侧剖视图。
图2D是示出按照本发明推动一弹性半导体装置与一互连基底的凹入到棱锥形接线端相接触的一侧剖视图。
图2E是示出按照本发明推动一弹性半导体装置与一互连基底的凹入的截头棱锥形接线端相接触的一侧剖视图。
图2F是示出按照本发明推动一弹性半导体装置与一互连基底的复合的沙漏形通孔接线端相接触的一侧剖视图。
图3A是示出按照本发明将本发明的接线匣基底连接于一外部装置(图未示)的侧剖视图。
图3B是示出按照本发明将本发明的接线匣基底连接于一外部装置(图未示)的侧剖视图。
图3C是示出按照本发明将本发明的接线匣基底连接于一外部装置(图未示)的侧剖视图。
图4A-4F是示出按照本发明制作截获衬垫的侧剖视图，该截获衬垫是位于接线匣基底中的沙漏形通孔。
图4G是按照本发明参照图4A-4F描述的工艺中的一个步骤的示意图。
图4H是按照本发明参照图4A-4F描述的工艺中的另一步骤的示意图。
图4I是按照本发明使用图4H所示的方法制作出的一接线匣基底的侧剖视图。
图4J是按照本发明另一接线匣基底的侧剖视图。
图4K是示出按照本发明支承和连接于接线匣基底的侧剖视图。
图5是按照本发明用于可插入地接纳带有一接线匣基底的一弹性半导体装置的一固定组件的侧剖视图。
图5A是按照本发明图5所示接线匣基底的俯视图。
图5B是按照本发明用于参照图5描述的组件的一壳体构件的立体图。
图5C是按照本发明用于可插入地接纳带有一接线匣基底的一弹性半导体装置的另一固定组件的侧剖视图。
图5D是按照本发明用于参照图5C描述的组件的一壳体构件的立体图。
图6是按照本发明用于可插入地接纳带有一接线匣基底的一弹性半导体装置的一固定结构的局部示意的侧剖视图。
图6A是示出按照本发明可插入地接纳一弹性半导体装置且与一外部装置形成连接的示意图。
图7是示出按照本发明可插入地接纳带有多个接线匣基底的多个弹性半导体装置的侧剖视图。
图7A是按照本发明位于一互连基底上的图7所示的接线匣基底的俯视图。
图7B是按照本发明用于可插入地接纳位于一互连基底上的多个弹性半导体模子的一单个较大接线匣基底的俯视图。
图8是按照本发明具有用于可插入地接纳位于一半导体晶片上的多个弹性半导体装置的一单个非常大的接线匣基底的一互连基底组件的平面图。
图8A是按照本发明图8所示组件的侧剖视图。
图8B是按照本发明图8所示组件的另一形式的侧剖视图。
图8C是示出按照本发明连接于多个接线匣部位的示意图，该多个接线匣部位位于用于可插入地接纳一半导体晶片上的多个弹性半导体装置的一非常大的基底上。
图9是按照本发明用于探测弹性半导体装置的一组件的侧剖视图。
图10是示出按照本发明的测试步骤的整个工艺的流程图。
具体实施方式
半导体装置的安装弹性接触件
上述已知的PCT专利申请US95/14909文本中的附图1C、1D和1E作为图1A、1B和1C复制在此，它揭示了在半导体装置的电子器件上制造上述组合互连类型的弹性接触件的一典型技术。一有用的技术详细地揭示在1998年6月30日授权的第5,772,451号美国专利“用于电子器件的接线匣和连接电子器件的方法”和1998年9月15日授权的第5,806,181号美国专利“用于组装带有弹性接触件的较大基底的接触承载体(瓷片)”。
现参见图1A、1B和1C，用于制造有弹力、细长、自由竖立的弹性接触件的一典型技术给出了位于电子器件108上的组合互连件。在一具体的较佳实施例中，电子器件108可以是一半导体装置。一导电材料的导电层126设置在钝化层124之上。施加光阻材料128，光阻材料128带有在钝化层中的开口122上方对齐的开口132。导线102的自由端102a连接于电子器件108的表面，而后镀上一层或多层导电材料，以得到自由竖立的细长的组合互连结构的一弹性接触件。除去光阻材料128和导电层126的阻挡覆盖的部分。
示出在图1C中的弹性接触件130是一组合互连件，它是细长的且具有安装在电子器件108上的一基(近)端和位于其相反端的一自由(远)端(尖端)。这对于与另一电子器件的接线端或其他接触端形成压力接触是有用的。(见图2、2A-2F)。
另外的弹性接触在特定的较佳实施例中是有用的。例如，1997年11月20日公开的WO97/43654或1997年11月27日公开的WO97/44676所揭示的弹性接触结构是特别较佳的。这些弹性接触件以想要的形式直接电镀在半导体装置上，或者电镀在中间的牺牲的基底上，接触件通过牺牲的基底固定在所需的半导体装置上，并去除牺牲的基底。
另一弹性接触件在本发明中也是有用的。举例讲，可按照1998年2月26日Pederson和Khandros递交的第09,032,473号美国专利申请“通过平板印刷界定的微电子接触结构”所揭示的内容来制造一特别有用的接触件。
一简单的接线匣技术
图2示出一较佳的基础的接线匣技术。在该例子中，组件200具有一电子器件202，电子器件202带有安装在一相应的接线端206上且从这里以弹性接触件204的形式伸展的一个或多个互连件。一接线匣基底208具有一个或多个截获衬垫210，如图所示，每一衬垫都是呈位于一表面上的扁平接线端的形式。在一具体的较佳实施例中，电子器件202是一半导体装置。
接线匣基底208可采用包括任何合适绝缘材料例如陶瓷或PCB的许多形式。一特别较佳的接线匣基底是硅。硅可直接用作半导体，也可以处理成绝缘体，并隔离所示的导体。基底本身可以是一有源的半导体装置。接线匣基底可以是一硅片，或一硅片的某部分。
向着接线匣基底208推动该电子器件202，如箭头212所示，以致弹性接触件204的尖端(远端)与对应的截获衬垫210接合且形成电性接触。
导电通道(trace)214可设置在接线匣基底208上。一导电通道从截获衬垫210伸展，所以可与电子器件202上的相应的接线端206形成电性连接。这对于借助截获衬垫210和对电子器件202的弹性接触件204来连接一外部装置例如一测试器(图未示)是特别有用的。
电子器件和接线匣基底之间的连接取决于这些器件之间的充分接触。可从接线匣基底上移开该电子器件。不同电子器件和/或不同接线匣基底的多种或重复的组合允许各种各样的或甚至是相同电子器件与给定接线匣基底的重复插入。这对于将半导体装置安装在完成的产品中特别有用，与当今广泛使用的用于安装容纳有一半导体装置的一单元的其他接线匣几乎一样。
这对于半导体装置的熔焊或测试也特别有用。在熔焊或测试情况中，一接线匣和支承电子器件可设计为用于固定和接触该半导体装置，以进行所需的测试。但是在此的区别是该半导体装置直接被插入，而没有独立的包装。
以此方式，接线匣基底208可作为能够与电子器件202形成可逆连接的一接线匣，电子器件202具有从其一表面上伸展提升的接触件。以下揭示其他接线匣结构。
在弹性接触件204和对应的截获衬垫210之间形成电性连接时，如果存在某些扫动动作，这通常是有益的，该扫动动作一般是接触件尖端横过截获衬垫的表面侧向移动的形式。有帮助地是它趋于移开或挖通截获衬垫的表面上或弹性接触件的尖端上的任何残留物和污染物。通过选择弹性接触件204的合适形状，电子器件202沿方向212(沿接线匣基底208的Z轴线)的移动将使接触件沿相反的Z方向变形。一弹性接触件的形状可使对该Z向移动的一响应包括有在垂直于Z轴线的XY平面中的分量的矢量运动。在较佳的实施例中，弹性接触件的形状被设计为使该XY分量沿着接触衬垫移动电子器件接触件的尖端，以给出有用的扫动动作。当接触件的尖端与截获衬垫相接触时或之后，通过相对XY平面中的半导体装置机械地移动接线匣基底来产生另一扫动动作。本领域的技术人员可设计出能够在选定的接触件和对应的接触衬垫之间产生某种扫动动作的有用的弹性形状。
导电通道214可连接于其他电路，例如连接于一外部电子装置，或者连接于一接触点或接线端以与一外部电子装置相连接。其他电路可组合在接线匣基底中并连接于一导电通道，以通过一个或多个互连件204最终连接于该电子器件。
第二接线匣结构
图2A示出用以与一电子器件(图未示)的互连件222(比较204)形成连接的另一接线匣220。接线匣基底224可与接线匣基底208相似。金属化的诸层以已知的方式形成在接线匣基底224的表面上，且包括一层或多层绝缘材料层和一层或多层金属化的层。可按照标准技术来组合这些层。在该图示中，所示的一金属化的层226嵌入在绝缘材料228中。另一金属化的层是暴露和可接触的，并形成用以连接互连件222的端部和第二接线端232的截获衬垫230，以与外部装置(图未示)形成连接。使用本领域中已知的技术，选定的一个截获衬垫230借助于金属化层226的选定部分和适当的内部连接件而电性连接于选定的一个第二接线端232。可以制造多层的连通性。以此方式，可得到复杂的线路配置。
第三接线匣结构
图2B示出与一电子器件(图未示)的互连件242(比较222)形成可逆连接的另一接线匣240。在该例子中，一绝缘层244施加在接线匣基底246(比较224)上且带有诸开口，截获衬垫248通过这些开口被暴露。绝缘层中的这些开口有助于向着截获衬垫248定位互连件242的端部，特别是当互连件首先与截获衬垫248对齐且大致对着衬垫248定位时。当接线匣基底是半导体晶片或其部分时，绝缘层244可应用为传统的钝化层。该绝缘层244给导电通道(例如图2中的214)提供实际保护。例如，如果互连件242被不适当地定位且错过对应的截获衬垫248时，绝缘层244可防止信号或电能的错向。
第四接线匣结构
图2C示出用以与一电子器件(图未示)的互连件262(比较242)形成连接的另一接线匣260。在该例子中，接线匣基底264(比较246)具有凹入的、而不是平坦的截获衬垫266(比较截获衬垫210、230、248)。在一个较佳的实施例中，截获衬垫266被压入到接线匣基底264的表面之中，或者压入到覆盖在接线匣基底上的诸层的表面中(比较图2A中的228)。所示的凹入的截获衬垫266是半球形，它的直径比与截获衬垫266相接触的互连件262的端部的直径大，这有助于对着截获衬垫引导或定位互连件的端部。
以上述的方式，导电通道268(比较图2中的214)从截获衬垫266适当地延伸至接线匣基底264上的其他位置。
具有其他形状的接线端也处在本发明的范围之内，例如延伸进入到接线匣基底或覆盖接线匣基底的一层的表面中的圆柱形凹陷。在此所使用的“凹入”一词包括圆柱形。
第五接线匣结构
图2D示出用以与一电子器件(图未示)的互连件282(比较262)形成可逆连接的另一接线匣280。在该例子中，接线匣基底284设置有适当的倒置棱锥形状的凹入的截获衬垫286(比较266)。在一较佳的实施例中，金属化的诸层以已知的方式形成在接线匣基底284的表面上(比较224)，且包括一层或多层绝缘材料层和一层或多层金属化层。在该图例中，所示的一金属化层288(比较226)嵌入在绝缘材料290中(比较228)。另一金属化层用以形成第一导电通道292(比较230)，第一导电通道292与各个截获衬垫286和导电通道294(比较232)电性接触，以与其他电路形成连接。选定的各第一导电通道292借助于嵌入的金属化层288的选择部分电性连接于选定的各第二导电通道294。
第六接线匣结构
图2E示出用以与一电子器件(图未示)的互连件203(比较282)形成连接的另一接线匣201。在该图例中，接线匣基底205(比较284)设置有一凹部207，凹部207是带有平坦底表面的倒置棱锥形。这样的凹部207是通过遮蔽(mask)一硅片、蚀刻、且在倾斜的侧壁聚合在顶点之前终止蚀刻来制作的(比较上述棱锥形的接线端286)。该凹部被金属化，如金属层209所示。这形成了一有用的截获衬垫。一导电通道211(比较图2中的214)示出在接线匣基底205上，并连接于金属化层209(比较210)。
第七接线匣结构
在以上结合图2A-2E所述的接线匣结构中，接线匣的接线端和一外部装置(图未示)之间的连接一般是通过该接线匣基底的第一表面上(或第一表面中)的导电通道(或金属化层)来完成的。该第一表面可视为接线匣基底的“顶”表面。
图2F示出用以与一电子器件(图未示)的诸互连件223(仅示出一个，比较203)形成可逆连接的另一接线匣221。在一具体的较佳实施例中，该接线匣基底是硅，可以全部是一硅片或一硅片的一部分。接线匣基底225(比较205)设置有诸凹部227(仅示出一个，比较207)，每个凹部227是两个在顶端相交的倒置金字塔的形式。凹部被金属化，如金属层229所示(比较209)。以下结合图4-4I详尽描述制造这样结构的一方法。
在该例子中，金属化的凹部的顶部接纳互连件223的自由(末)端。与外部装置的连接可从接线匣基底的底表面通过直接连接凹部接线端的底部来完成。一导电通道231可用来再次定位一接触点，或者形成所需的互连。当然，导电通道可设置在接线匣基底的任一侧上，并可以使用一层或多层金属化层。以此方式，能够形成复杂的连接配置。
连接于基底
图3A示出通过接线匣基底302将一外部装置连接于一电子装置的一接线匣300，接线匣基底302具有用以接纳一细长互连件(图未示)的端部的截获衬垫304。比较图2E的接线匣基底205和其相应部分。在此，导电通道306将截获衬垫金属化层304连接在位于基底302的边缘处的接线端308上。导电通道306仅是举例说明，接线端304和308之间的连接也可以是埋置的，如图2A和2D所示，这在本领域中是已知的。箭头310示意地表示可进行一外部装置与接线端308之间的连接。有用的连接是众所周知的，包括带有相应的接线匣、管脚(pogo pins)、导线连接线、引线框架等等的边缘连接件。
图3B示出将一外部装置连接于接线匣基底322的接线匣组件320的一较佳实施例，接线匣基底322具有接纳一细长互连件(图未示，比较203)的端部的一截获衬垫324。在该例子中，一导电通道326设置在基底322上且延伸至位于基底322的边缘处的接线端328。在该例子中，接线匣基底322被一支承基底330支承住。该支承基底可以是多种材料，较佳地为陶瓷、硅或PCB。支承基底330具有一接线端332。插座基底322的接线端328可通过任何适当的方式例如一连接线334电性连接于支承基底330的接线端332，连接线334可使用传统的导线焊接技术进行连接。箭头336示意地表示可进行一外部装置与接线端338之间的连接，由此连接于截获凹槽324。
图3C示出接线匣的另一较佳实施例，在此为接线匣340。接线匣基底342具有一截获凹坑344，截获凹坑344带有用以接纳一细长互连件(图未示)的端部的一个部分344a(比较227a)。在该例子中，截获凹坑344完全延伸通过接线匣基底342且具有用以形成其他连接的一下部344b(比较227b)。在该实施例中，支承基底346具有第一接线端348、第二接线端350、以及连接两接线端348和350的导电通道352。导电材料块354(比较334)诸如焊料、焊料球、一块导电环氧材料等等设置在接线端344的下部344b中，并从支承基底延伸以在接线匣基底342的接线端344和支承基底346的接线端348之间形成电性连接。在该例子中，箭头356指示在一外部装置与接线端350之间进行的连接。
在硅片中形成通孔接线端
如上述结合图2F和3C的讨论，可以提供带有通孔类型接线端的接线匣基底(225、346)，其顶部接纳一细长互连件的自由端，其底部可按所需连接。
在特定的应用中，用硅形成接线匣基底是符合需要的。在与运作的半导体装置将紧密接触的一组件中这特别有益。这样的装置在使用中或者或许在测试中会变热，连接于具有相近热膨胀系数的材料是有益的，从而运行的装置和连接件保持相近的几何关系。使一硅装置与另一硅装置相匹配是特别符合需要的。
图4A-4F示出加工一结构400以在硅基底402中形成通孔类型接线端的过程。参见PCT WO97/43656(“晶片级的熔焊和测试”)中结合该公开物的图5A、5B和5C的讨论。
图4A示出该工艺的第一步骤。一渗氮层404施加至基底402的前表面上，基底402是一片1，0，0硅。该渗氮层带有诸开口406。这些开口406较佳地为正方形，并具有150-250μm、例如200μm的截面尺寸(S1)。以相似的方式，一渗氮层408施加在基底402的后表面上，并带有诸开口410。渗氮层408中的诸开口410较佳地为正方形，且具有150-250μm、例如200μm的截面尺寸(S2)。选定的若干个、且总的来说每个开口406与相应的一个开口410直接相对。一对对齐的开口406和410将决定形成在硅基底402中的一通孔接线端的位置。
所示的开口406和410具有相同的截面尺寸(即S1＝S2)，但是如以下将讨论到，这不是必需的，并且在某些应用中不是较佳的。
在一较佳实施例中，与406和410等同的开口是矩形，而不是正方形。相对的开口可以是平行定向的矩形，或者相对的开口是正交的。简言之，当蚀刻时，一矩形开口将产生一个槽结构，而不是一个点。每一开口的相对尺寸不需要相同。
图4B示出下一步骤，其中基底402在开口406和410中被蚀刻，渗氮层404和408起到遮蔽材料的作用，以防止在开口406和410之外的其他地方被蚀刻。一合适的蚀刻剂是氢氧化钾(KOH)。1，0，0硅的一个特征是在KOH中会蚀刻成一个角度，该角度是53.7°。按照硅的晶格进行蚀刻。因此诸如406和410的开口较佳地定向成与晶格对齐是较佳的。晶格的定向是已知的，一般是由圆形硅晶片中的一个凹口来指示。
仅从一侧蚀刻得到了延伸进入基底的该侧的一棱锥形的凹坑(比较图2D中的286)。该凹坑的尺寸被其内发生蚀刻的开口的尺寸和定向以及1，0，0硅的蚀刻角度所控制。当基底的表面上没有保持暴露的硅时蚀刻将停止。简言之，以正方形开口起始，可产生棱锥形的凹坑。如果蚀刻没有完成，则形成截头的棱锥形。在用于蚀刻的开口是矩形时，将形成一个槽结构。
在一较佳实施例中，蚀刻是从两侧进行的，两个棱锥形的凹坑412和414向着彼此“生长”。通过保证开口具有足够的宽度，并且基底足够薄，这两个棱锥形的凹坑412和414将生长进入到彼此中(重叠)，从而得到图4B所示的“沙漏形”通孔。如果需要，凹坑可以“过度蚀刻”，致使渗氮层404和408稍微悬在凹坑开口上。一旦完成蚀刻，可通过择优侵蚀除去渗氮层404和408。
蚀刻该沙漏则在硅基底中形成一个通路。通路广泛使用在诸如半导体装置等许多电子产品和多层基底中。该新通路将被制成可导电，就能够以使用通路的许多已知方式来使用。
图4C示出下一步骤，其中基底402被再渗氮，例如在基底402、包括凹坑412和414的侧壁内的全部表面上热生成一非常薄的渗氮层416。该氮化物可部分起到使半导体基底与任何随后施加的导电材料相绝缘的作用。
图4D示出下一步骤，其中整个基底402被涂覆上(例如喷涂)钛-钨(TiW)材料的薄层418，而后涂覆较薄的金材料的晶粒层(seed layer)420。典型的尺寸和有用的方法及材料详细地列在1998年2月26日提交的第09/032,473号美国专利“通过平板印刷界定的微电子接触结构”中，其全部内容引述在此，以供参考。
图4E示出下一步骤，其中遮蔽材料层430例如光致抗蚀剂施加至基底402的两侧上且带有与凹坑412和414对齐的开口。凹坑中的晶粒层420没有被遮蔽材料覆盖。而后，例如通过电镀将一层或多层导电材料432例如镍设置在凹坑412和414中暴露的晶粒层420上。
图4F示出下一(最后)步骤，其中遮蔽层430被除去(例如通过漂洗)，晶粒层418和420的未电镀部分也被除去(例如通过选择性的化学蚀刻)，将导电材料432留在其内，并桥接两个凹坑412和414，由此形成通过基底402的导电通路。这在凹坑412和414之间提供了电性连通。
图4G示出刚刚描述过的工艺中的一中间暂时步骤。当凹坑412和414(见图4B)被首先蚀刻时，它们向着彼此“生长”。在开口406和410(见图4A)具有相同截面尺寸(都为“S1”)的情况下，该生长的凹坑应当彼此对称，一个是另一个的镜像，如图所示。
图4H示出该工艺中的一中间暂时步骤(比较图4G)，在开口406和410(见图4A)不具有相同截面尺寸的情况下，例如开口406具有比开口410较大的截面尺寸(即，S1＞S2)。在此可观察到两个凹坑444和446(比较412和414)以相同的速率生长进入到基底442(比较402)中，但是凹坑446已到达其顶点且终止其生长。凹坑444将持续生长，直到蚀刻自身终止。设计者应当选择基底402的厚度和开口406和410的尺寸，以获得该蚀刻图形，或者其他选定的蚀刻图形。
图4I示出一接线匣基底452(比较442)，其中该工艺以不具有相同截面尺寸的开口(比较406和410)开始，如同结合图4H所讨论的情况。在此可观察到，凹坑454(比较444)比凹坑456(比较446)较宽且较深。示出了设置在凹坑454和456中的晶粒层(图未示)上的导电材料458。
在使用中，细长互连件(比较223，图2F)的自由端能与凹坑412中的导电材料432相接触，导电块(比较354，图3C)能于凹坑414中的导电材料432相接触。
其他后连接技术
例如以上在图2F、3C和4E中已描述了通过接线匣基底与其后侧形成连接的技术。
图4J示出另一结构460。在该较佳的实施例中，形成通过接线匣基底462、从其前侧上的截获接线端464至其后侧的连接。所示的接线端464是凹坑类型的接线端，如同参考图2D或3A分别描述的那些(比较286和304)。
导电线路片466在接线端464和传统电镀的通孔468之间延伸，通孔468延伸通过接线匣基底462。以此方式，可实现与接线匣基底462的后侧的连接(例如连接于互连基底等等)。这样的导电通道可与上述电镀的通孔结合使用。例如，参见图4I，并使用所示的结构替换图4J中的468。
图4K示出使用具有喷镀金属的双棱锥形通孔484(比较344)通过接线匣基底482(比较图3C中的342)形成连接的另一可替代的技术480。接线匣基底482合适地包括一硅晶片。通孔484的下部484b与细长互连件486的一个端部形成连接，细长互连件486以图2F所示的相同方式从互连基底488(比较346)处延伸。在一个较佳的实施例中，该互连件486可连接于一插入件。接线匣基底482被一个或多个支承基底加固和支承，但并不必电性连接于该支承基底。这些支承基底较佳地被电性隔离，并可用绝缘材料制造。硅或陶瓷是特别适用的。在该例子中，示出两个支承基底490和492。
第一支承基底490被设置成紧靠接线匣基底482，且带有从中延伸通过的一个孔494，孔494与通孔484对齐(例如同轴线)。孔494具有比进入到接线匣基底482的后侧处的通孔484较大的截面尺寸。使用适当的粘合剂例如腈基丙烯酸酯将接线匣基底482较佳地粘附在支承基底490上。
第二支承基底492被设置成邻近第一支承基底490，且带有从中延伸通过的一个孔496，孔496与孔494对齐(例如同轴线)。孔496具有比孔494大的截面尺寸。使用适当的粘合剂例如腈基丙烯酸酯将第一支承基底490较佳地粘附在第二支承基底492上。孔494和496的尺寸较佳地逐渐变大，形成锥形开口。但是，只要所需的互连件可与通孔484形成电性接触，这些尺寸不是特别严格。例如，具有较窄的孔496也是合乎需要的，可给该组件提供额外的强度或有助于定位细长的互连件486。
以此方式，从互连基底488至包括接线匣基底482的截获衬垫的通孔484的部分484a可形成电性连接。
用于单个小片(die)的熔焊固定结构(组件)
以上已描述了适合与电子器件例如半导体装置上的细长的接触件形成电性连接的多种接线匣基底。现描述这样的接线匣基底的一个典型的应用。
图5示出一组件500，组件500包括一互连和支承基底502(比较图3B中的330)和以上参考图3B所描述的类型的接线匣基底504(比较322)。接线匣基底504具有截获衬垫即接线端506(比较324)，接线端506通过导电通道510(比较326)连接于接出接线端508(比较328)。该接出接线端508通过连接线512(比较334)连接于互连基底502上的接线端514(比较332)。可使用本领域中众所周知的技术将接线端514连接于其他装置。一个代表性的方法就是在支承基底的表面上设置导电通道。参见图5A的俯视图，接线匣基底504适当地设置有多个接线端506。以举例的方式示出八个。
在使用中，接线端506接纳相应的多个互连件516(比较204)的端部，互连件516例如可以是从电子器件518(比较202)例如半导体装置的表面上延伸出的弹性接触件。
组件500还包括总体呈开放盒形的一壳体(罐)520。参见图5B，壳体520具有一顶表面522和四个侧壁524、526、528和530(在图5的剖视图中可看到其中两个侧壁524和528)。壳体520的底部是开放的。相对的侧壁524和528分别设置有片状的腿部532和534，腿部532和534在此延伸超出壳体520的底部。壳体520的顶表面522设置有弓形部(段)536，在使用中，如图5中的箭头538所示，弓形部536向着电子器件518的后表面向下压，致使互连件516的端部与接线端506相接触。为了将壳体520夹持在互连基底502上的适当位置中，腿部532和534的端部分别通过相应的孔540和542插入到互连基底502中。参见图5，腿部532和534的端部延伸超过互连基底502的底表面，且成型(卷曲、弯曲)以便被截获在互连基底502的底表面上，以将壳体520保持在互连基底502上的适当位置中。
组件500按照如下的方式在电子器件上例如半导体装置上进行熔焊时非常有用。将装置518放置在接线匣基底502上，致使互连件516的端部接合接线匣基底504的接线端506。壳体520设置在半导体装置518上，致使弓形部536推压半导体装置518的后表面，并且小片532和534延伸通过互连基底502中的相应的孔540和542。电能可供给互连基底502的接线端508以接通半导体装置518的电源且熔焊半导体装置518。如箭头544所示，可通过向内挤压(向着彼此)腿部532和534来取出壳体520，并且也可取出半导体装置518。将另一装置安装在其位置上，并重复该过程(该壳体重新安装在互连基底上以熔焊随后的器件)。
用于单个器件的另一固定结构
图5C和5D示出另一较佳的实施例。壳体550与上述的壳体520相似。壳体550总体呈开放的盒形。从图5D中(比较图5B)可最清楚地看出，壳体550具有一顶表面552(比较522)和四个侧壁554、556、558和560(比较524、526、528和530)，在图5C的剖视图中可看到其中两个侧壁554和558。壳体550的底部是开放的。两个相对的侧壁554和558都分别设置有片状的腿部562和564(比较532和534)，腿部562和564在此延伸且超过壳体550的底表面。
壳体550的顶表面552可通过冲压或类似方式而形成三个细长部分566、568和570。其中两个细长部分566和570从顶表面522的邻近的一个边缘向着顶表面的相对的边缘平行地延伸且彼此分隔开。第三细长部分568从顶表面的邻近的相对的边缘向着顶表面的另一边缘延伸，平行于且位于两细长部分566和570之间。每个细长部分566、568和570成型为悬出的“弓”(比较536)，如箭头574(比较538)所示，能够下压电子器件572(比较518)的后表面。
壳体550的腿部562和564适当地以以下方式形成。参见图5D，腿部564通过两个分开的平行的切口576和578形成在壳体的侧壁558中，切口576和578从侧壁558的底边缘基本延伸至侧壁558的顶边缘。而后将腿部564从侧壁向外弯曲，而后可弯曲腿部的端部564A以使其与侧壁相平行地延伸。这垂直于(90°)带有孔的互连基底(比较502)，该孔接纳细长腿部564的端部。而且，如同前面的例子，腿部562和564的端部可成型(卷曲、弯曲)以便被截获在互连基底(502)的底表面上，并使壳体550在互连基底(502)上保持就位。
在接触结构的有用变型中，接触接线端直接设置在支承基底上。作为一个例子参见图5，接线端506可直接形成在支承基底502上。在一较佳的实施例中，该接线端506是邻近支承基底的平坦的接触件。支承基底502可以是有机材料，例如印刷电路板。在该实施例中，不需要连接线512，接线端506可依照需要直接连接于其他电路。
在封装壳体的有用变型中，一简单的扁平单元在四个角安装有腿部，近似一个普通的桌子，诸腿部可以向着支承基底延伸。该支承基底本身具有可使腿部插入的相应的孔。诸腿部具有可弯曲的、偏移的或扩张的锁定特征，以将该扁平单元夹持就位，来固定半导体装置518，使之与接线端506相接触。在一特别较佳的实施例中，壳体安装有热塑材料的腿部。半导体装置518与接线端506对齐，并且该壳体被定位成在半导体装置上施加一些压力，而诸腿部穿过支承基底中的孔。而后加热壳体的每个腿部(“热打桩的”)，以防止腿部通过基底中的孔向后移动的方式来熔化材料。
用于单个小片模的另一结构
以上已描述了两个固定结构，都包含有用于可逆地将一电子器件(518、572)连接于一接线匣基底以对该电子器件进行(熔焊或测试)操作的壳体(520、550)。也已描述了用于在接线匣基底和一外部装置或系统之间形成连接的方法。
图6示出用以夹持一电子器件602的另一技术600，电子器件602具有从其上对着接线匣基底608的接线端延伸的细长互连件604。在该例子中，接线匣基底608是以上参考图3B所述的类型。接线匣基底608(比较322)具有凹坑型的接线端606(比较324)，接线端606通过导电通道612(比较326)连接于接出接线端610(比较328)。该接出接线端610通过连接线614(比较334)连接在互连基底609上的接线端616(比较332)。
在该例子中，在互连基底608的表面上并非具有导电通道(比较339)和接线端(比较336)，并且与互连基底609的顶侧没有连接(比较336)，互连基底609设置有一组“管脚”620，管脚620从其底表面延伸且通过内部导电通道622连接于接线端616。
在该例子中，不是靠一壳体(520、550)将电子器件(518、572)夹持在接线匣基底上，电子器件602通过一测试头(或者真空吸盘)630被夹持在接线匣基底608上。
图6A示出一技术650，代表上述可插入地接纳一电子器件以进行熔焊或测试的所有的技术。一接线匣基底652具有位于其表面上的多个“截获”接线端604(凹坑、衬垫等等)，该接线匣基底652并以任何适当的方式(连接线、导电块等等)安装和连接于一互连基底656，互连基底656又以任何适当的方式(例如边缘连接件、管脚等等)连接于一外部测试装置或系统(“测试器”)658。
用于多个小片的固定结构
可插入地接纳单个弹性半导体装置的原理可容易地延伸至多个弹性半导体装置，如下所述。
图7和7A示出同时对多个(图7中示出四个)电子器件702进行操作的装置700，电子器件702是弹性的半导体装置。每个弹性半导体装置702(比较518)都具有细长的互连件，该互连件是从其一个表面上延伸出的弹性接触件。相应的多个(图7A中示出八个)接线匣基底704(比较504)具有诸截获衬垫706(在每个接线匣基底中示出六个)，截获衬垫706是合适的凹坑型接线端(比较506)，能够以上述任何方式可插入地接纳细长互连件的自由端。接线匣基底704以上述任何方式合适地安装且电性连接在普通的支承/互连基底708(比较502)上。为清楚起见，没有示出具体的连接。从互连基底708至“外部世界”的典型的连接在该例子中为多个管脚710。如箭头712所示，弹性的半导体装置702以上述任何适当的方式(例如壳体520和550、测试头630等等)夹持在相应的接线匣基底704上。以此方式，多个(例如八个)单独的弹性半导体装置能够可逆地连接于外部装置或系统(比较658)。
如图7B所示，对一组单小片(电子器件)进行操作的原理可由被互连基底708’支承且连接于互连基底708’的单个接线匣基底704’来实现。在该图中，所示的位于接线匣基底704’上的八个接线匣区域被虚线分隔，且与图7A所示的八个分离的接线匣基底704相对应。
晶片级的系统
以上已描述了用以可插入地接纳单个弹性半导体装置和可插入地接纳多个弹性半导体装置的原理。该原理可延伸至对弹性半导体装置的整个晶片进行操作，如下所述。
图8示出用于测试具有弹性半导体装置的整个晶片(WUT)802(比较702)的一个装置800。具有适当的截获衬垫的单个接线匣基底或接线匣基底与互连基底的组合被整体量定尺寸，且带有用以接纳互连件的自由端的截获衬垫(接线端，图未示)，在该例子中，互连件是从WUT802上的所有的半导体装置上延伸出的。这能够以各种方式来实现。
第一种方式是给单个的较大互连基底(比较708)设置适当数目的单独的接线匣基底(比较704)，以致WUT802上的每个半导体装置都具有一个与其相关且接纳其互连件的接线匣基底。这类似图7所示的装置，但它是较大的比例，而且半导体装置(702)停靠在WUT802上(即没有独立于WUT)。
另一方式是给单个较大的互连基底(比较708)设置适当较少数目的接线匣基底(比较704’)，每一个接线匣基底都能够接纳从位于WUT802之上的多个(例如八个)半导体小片(比较702)伸出的互连件。这类似图7A所示的装置，但它是较大的比例。
另一方式示出在图8A中。在该例子中，可用另一硅晶片形成的单个接线匣基底804比WUT802大(例如直径)。在WUT802的周边之外延伸的接线匣基底804的周边区域设置有衬垫806或类似物，用于以上述的任何方式与外部系统或装置形成连接。在使用中(即当运行WUT之上的半导体装置时)，分别通过热吸盘812和814可从WUT802和接线匣基底804上除去不想要的热量。
另一方式示出在图8B中，在该例子中，可用另一硅晶片形成的单个接线匣基底804’具有与WUT802大约相同的尺寸，并安装和连接在互连基底808上，互连基底808比接线匣基底804’和WUT802都大。在接线匣基底804’的周边之外延伸的互连基底808的周边区域设置有衬垫806’或类似物，用于以上述的任何方式形成与外部系统和装置的连接。在使用中(即，当运行WUT之上的半导体时)，可分别通过热吸盘812’和814’从WUT802和接线匣基底804’上除去不想要的热量。
图8C示意地示出用以布置和连接位于接线匣基底、不论是图8A所示的接线匣基底804，还是图8B所示的接线匣基底804’之上的各种接线匣(比较704’)的一典型的线路图。多个接线匣822被设置成诸列(从“a”到“n”，)和诸行(从“1”到“N”)。每个接线匣822对应被测试的晶片(WUT)802之上的其中一个半导体装置。对于简单地熔焊WUT802之上的多个半导体装置的目的，每个接线匣都具有对应于弹性半导体装置之上的互连件的接线端(例如凹坑型接线端)一般是足够的，需要能量来熔焊该半导体装置。换言之，通常不必要与半导体装置的所有互连件形成连接来熔焊它们。如图所示，电能借助于减少数量的普通导线824可传送给各个接线匣822，每根导线通过电阻826连接于对于的接线匣。以此方式，如果位于WUT802之上的其中一个半导体装置短路，将通过该电阻隔离其余在熔焊的那些半导体装置。
转换探测卡
探测卡包括一互连基底和诸细长的弹性接触件，弹性接触件直接或间接地从那里延伸且被设置为与一半导体晶片上的半导体装置的接线端相接触。一测试器连接于探测卡以运行位于晶片上的半导体装置。
已知的审批中的于95年11月9日递交的第08/554,902号美国专利申请及其对应的于95年11月13日递交的PCT专利申请(状态：审批中，96年5月23日公开，公开号：WO96/15458)揭示了一典型的探测卡。图9可与这些审批中的专利申请的图5相比，在这些申请标号为5××的元件在此总的被标为9××。
图9示出一探测卡组件900，组件900包括作为其主要功能构件的探测卡902、一插入件904、以及一互连基底906，互连基底906是一空间变换器，它适于用来与从位于半导体晶片908之上的半导体装置处延伸出的细长互连件926形成可逆的相互连接。
该审批中的专利申请的空间变换器(518)设置有多个弹性互连件(524“探针”、“探测件”)，该互连件设置成与半导体晶片(508)上的半导体装置上的对应的连接衬垫(526)形成压力连接。在本发明的探测卡组件900中，上述任何类型的一接线匣基底924以上述的任何方式适当地安装且连接在互连基底918上。
在使用中，对着探测卡组件900(如箭头925所示)推动晶片908(反之亦然)，致使从位于半导体晶片908之上的一个或多个(包括全部)半导体装置处延伸的细长互连件926的端部与接线匣基底924上的接线端(例如凹坑型接线端)相接触。在互连件比正被接触的所有半导体装置少的情况下，测试被接触的半导体装置之后，重新定位晶片908，致使其他半导体装置被接触(重复“触地”)和被测试。
通过使用本发明的探测卡组件900可容易地意识到一个优点，那就是可容易地控制接线匣基底924的截获接线端的冶金过程，以使与互连件926的端部的接触最优化，例如金与金的接触和有限的擦洗。
考虑到完整性，以下简要描述探测卡组件900的其他元件。
探测卡902一般是传统的电路板基底，该基底具有设置在其顶表面上(如图所示)的多个(示出其中两个)接触区域(接线端)910。夹置体904具有一基底912。多个(示出其中两个)弹性互连件914(通过它们的近端)安装在基底912的底表面上并从这底表面向下延伸(如图所示)，对应的多个(示出其中两个)弹性互连件916(通过它们的近端)安装在基底912的顶表面上并从这顶表面向上延伸(如图所示)。互连基底906包括一合适的电路化的基底918，例如一多层陶瓷基底，该基底具有设置在其下表面(如图所示)上的多个(示出其中两个)接线端(接触区域、衬垫)920和设置在其上表面(如图所示)上的多个(示出其中两个)接线端(接触区域、衬垫)922。
探测卡组件900具有用于将夹置体904和互连基底906堆叠在探测卡902上的以下的主要元件：
用刚性材料例如不锈钢制造的一后安装板930，
用刚性材料例如不锈钢制造的一致动安装板932，
用刚性材料例如不锈钢制造的一前安装板934，
包括一外差动螺旋件和一内差动螺旋件938的多个(示出其中两个，三个是较佳的)差动螺旋件，
一安装环940，该安装环较佳地用弹性材料例如磷青铜制造且具有从其延伸的弹性片(图未示)的样式，
将安装环940固定在前安装板934上的多个(示出其中两个)螺钉942，互连基底906被截获在其问，
设置在安装环940和互连基底906之间的一可选择的间隔环944，以适应制造公差；以及
设置在差动螺旋件的顶部(如图所示，例如内差动螺旋件938的顶部)的多个(示出其中两个)支点球体946。
后安装板930是设置在探测卡902的底表面(如图所示)上的金属板或环(图中示为一个环)。多个(示出其中一个)孔948延伸通过后安装板。
致动安装板932是设置在后安装板930的底表面(如图所示)上的金属板或环(图中示为一个环)。多个(示出其中一个)孔950延伸通过致动安装板。在使用中，致动安装板932以适当的方式例如用螺钉(清楚起见，图中省略)固定在后安装板930上。
前安装板934是刚性的、较佳地为金属环。在使用中，前安装板934以适当的方式例如用螺钉(清楚起见，图中省略)固定在后安装板930上。螺钉穿过通过探测卡902的相应的孔(清楚起见，图中省略)，由此将探测卡902牢固地截获在前安装板934和后安装板930之间。
前安装板934具有对着探测卡902的顶表面(如图所示)设置的一平坦的底表面(如图所示)。前安装板934具有由其内边缘952界定的一较大的中心开口，该开口的尺寸设定成允许探测卡902的多个接触接线端910处在前安装板934的中心开口中，如图所示。
前面已提到，前安装板934是具有平坦底表面(如图所示)的环型结构。前安装板934的顶表面(如图所示)是台阶形，前安装板的外部区域比其内部区域厚(沿竖立方向，如图所示)。该台阶或台肩位于虚线所示的位置(标为954)，且其尺寸允许互连基底906离开前安装板的外部区域而停靠在前安装板934的内部区域上(尽管看起来互连基底906实际停靠在支点球体946上)。
多个孔955(示出其中一个)从前安装板顶表面(如图所示)延伸进入到前安装板934的外部区域中，并至少局部通过前安装板934(图中所示的这些孔仅局部延伸通过前安装板)，从图中可看出，这些孔用来接纳对应的多个螺钉942。对于此目的，孔955是带螺纹的孔。这允许通过安装环940将互连基底906固定在前安装板上，因此对着探测卡902被推压。
多个(示出其中一个)孔958完全延伸通过前安装板934的较薄的内部区域，孔958与延伸通过探测卡902的多个(示出其中一个)对应的孔960对齐，孔960又与后安装板中的孔948和致动安装板938中的孔950对齐。
支点球体946宽松地设置在对齐的孔958和960中、内差动螺旋件938的顶端处(如图所示)。外差动螺旋件936拧入到致动安装板932的(螺纹)孔950中，内差动螺旋件938拧入到外差动螺旋件936的螺纹孔中。以此方式，在各个支点球体946的位置可进行非常精确的调节。例如，外差动螺旋件具有每英寸72个螺纹的外部螺纹，内差动螺旋件938具有每英寸80个螺纹的外部螺纹。这可容易且精确地调节与探测卡902相对的互连基底906的平面度。因此，无需改变探测卡902的方位就可改变接线匣基底924的位置。依靠设置在夹置体的两表面上的弹性或顺应的接触结构，夹置体904确保电连接在互连基底的整个调节范围内都保持在互连基底906和探测卡902之间。
探测卡组件900是简单地通过以下方式装配的，将夹置体放置在前安装板934的开口952中，致使互连件914的末端接触探测卡902的接触接线端910，将互连基底906放置在夹置体904的顶部，致使互连件916的末端接触互连基底906的接触衬垫920，可选择地将分隔件944放置在互连基底906上，将安装环940放置在分隔件944上，并将螺钉942通过安装环940和分隔件944插入到前安装板934的孔955中，通过将螺钉(其中一个在局部示出为955)通过后安装板930和探测卡902插入到前安装板934的底表面(如图所示)中的螺纹孔(图未示)中，将该“子组件”安装在探测卡902上。而后将致动安装板938装配(例如用螺钉，其中一个在局部示出为956)在后安装板930上，使支点球体960坠落在致动安装板932的孔950中，并将差动螺旋件936和938插入到致动安装板932的孔950中。
总的方法
以上已描述了用于接触从电子器件(例如弹性的半导体装置)上延伸出的细长的互连件的技术，该电子器件包括单个的半导体装置、成组的半导体装置、以及半导体装置的整个晶片，该技术包括通过进行熔焊和/或测试过程来操作该半导体装置。现描述从开始制造到最终产品的整个工艺流程。
图10示出用以制造具有从其表面上延伸的弹性接触件的半导体装置的整个工艺1000的序列步骤。
在工艺流程1000的第一步骤(“晶片制造”)1002中，制造半导体装置。这些半导体装置制造成带有从其一个表面上延伸出的细长的弹性互连件，而不是简单地带有传统的连接衬垫，这些半导体装置被称之为“弹性的半导体装置”。多个弹性的半导体装置位于一半导体晶片之上。
在工艺流程1000的下一步骤(“晶片分类1”)1004中，制造成具有弹性半导体装置的晶片被分类。这可使用传统的探测方法，例如使用图9所示的探测卡。
在工艺流程1000的下一步骤(“修正”)1006中，可选择地修正出现的问题，可使用本领域中已知的技术，例如激光修正、防熔合技术等等。
在工艺流程100的下一步骤(“晶片级熔焊”)1008中，晶片上已知的良好小片(die)被熔焊，例如可使用上述图8所示的技术。
在工艺流程1000的下一步骤(“晶片分类2”)1010中，已在步骤1008中被熔焊的已知小片进行功能测试和分类，例如，可通过使用上述图9所示的技术。
在最后的步骤(图未示)，从晶片上单独取下熔焊的、测试/分类的小片，包装(如果需要)贴上标签，存放或装配至系统(图未示)中。
以上已对本发明的装置和使用本发明的方法以及本发明的较佳实施例作了总的描述。在上述装置和方法的许多方面，本领域的技术人员可意识到并可进行多种变化和改型，这都处在本发明的范围之内。本发明的精神和范围仅应当由以下列出的权利要求书来限定。

Claims (14)

1.一种用于测试半导体装置的设备，所述设备包括：
多个半导体装置，所述半导体装置各具有多个细长弹性接触件；
一互连基底，所述互连基底具有供测试信号来去所述半导体用的多个第一电连接件；
多个接线匣基底，所述各接线匣基底的第一侧固定至所述互连基底，所述接线匣基底各具有置于所述接线匣基底的第二侧上的、用于分别接纳所述多个细长弹性接触件的其中之一的多个截获衬垫；
多个导电通道，所述导电通道分别置于所述多个接线匣基底的其中之一的所述第二侧上，且与所述截获衬垫的其中之一电连接；
多个第二电连接件，所述第二电连接件用于使所述导电通道分别与所述第一电连接件相连接；以及
一推压机构，所述推压机构用于将所述半导体装置推压在所述接线匣基底上，以便所述细长弹性接触件与所述截获衬垫形成电连接。
2.如权利要求1所述的设备，其特征在于，所述多个半导体装置是非单个半导体晶片的模子。
3.如权利要求2所述的设备，其特征在于，所述接线匣基底分别与其中一个模子相对应。
4.如权利要求1所述的设备，其特征在于，所述互连基底是探测卡组件的一部分。
5.如权利要求4所述的设备，其特征在于，所述互连基底通过一插入物与探测卡电连接，并且所述互连基底、所述插入物以及所述探测卡构成了所述探测卡组件。
6.如权利要求1所述的设备，其特征在于，所述半导体装置是未包装的单个半导体模子。
7.如权利要求1所述的设备，其特征在于，还包括设置用来控制所述半导体装置的温度的温控装置。
8.如权利要求7所述的设备，其特征在于，所述温控装置包括：
与所述半导体装置热接触的第一热吸盘；以及
与所述接线匣基底热接触的第二热吸盘。
9.如权利要求1所述的设备，其特征在于，所述接线匣基底成行地设置在所述互连基底上，并且所述设备还包括置于所述互连基底上的多个能源线，所述能源线分别与其中一行接线匣基底相对应，并向该行中的每个接线匣基底提供能量。
10.如权利要求9所述的设备，其特征在于，还包括多个绝缘电阻器，每个绝缘电阻器置于其中一个能源线与其中一个所述接线匣基底之间。
11.如权利要求1所述的设备，其特征在于，所述推压机构包括测试头或者真空吸盘的其中之一。
12.如权利要求1所述的设备，其特征在于，所述多个第二电连接件包括多根连接线，每根连接线分别与所述多个导电通道中的一个以及所述多个第一电连接件中的一个相连。
13.如权利要求1所述的设备，其特征在于，所述截获衬垫包括蚀刻到一相应的接线匣基底的第二侧中的凹坑。
14.如权利要求1所述的设备，其特征在于，所述接线匣基底为硅材料。
CNB998079707A 1998-06-30 1999-06-30 带有弹性封装的一电子器件的组件 Expired - Fee Related CN1197443C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/108,163 US6033935A (en) 1997-06-30 1998-06-30 Sockets for "springed" semiconductor devices
US09/205,502 1998-12-04
US09/205,502 US20020004320A1 (en) 1995-05-26 1998-12-04 Attaratus for socketably receiving interconnection elements of an electronic component
US09/108,163 1998-12-04

Publications (2)

Publication Number Publication Date
CN1307793A CN1307793A (zh) 2001-08-08
CN1197443C true CN1197443C (zh) 2005-04-13

Family

ID=26805592

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB998079707A Expired - Fee Related CN1197443C (zh) 1998-06-30 1999-06-30 带有弹性封装的一电子器件的组件

Country Status (7)

Country Link
US (3) US20020004320A1 (zh)
EP (1) EP1092338B1 (zh)
JP (2) JP3723079B2 (zh)
CN (1) CN1197443C (zh)
DE (2) DE69922656T2 (zh)
TW (1) TW548756B (zh)
WO (1) WO2000001208A1 (zh)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5772451A (en) * 1993-11-16 1998-06-30 Form Factor, Inc. Sockets for electronic components and methods of connecting to electronic components
US20020004320A1 (en) * 1995-05-26 2002-01-10 David V. Pedersen Attaratus for socketably receiving interconnection elements of an electronic component
WO1999000844A2 (en) * 1997-06-30 1999-01-07 Formfactor, Inc. Sockets for semiconductor devices with spring contact elements
US6627483B2 (en) * 1998-12-04 2003-09-30 Formfactor, Inc. Method for mounting an electronic component
US6468098B1 (en) * 1999-08-17 2002-10-22 Formfactor, Inc. Electrical contactor especially wafer level contactor using fluid pressure
US7396236B2 (en) 2001-03-16 2008-07-08 Formfactor, Inc. Wafer level interposer
DE10121969C1 (de) * 2001-05-05 2002-08-29 Semikron Elektronik Gmbh Schaltungsanordnung in Druckkontaktierung und Verfahren zu seiner Herstellung
JP4752157B2 (ja) * 2001-08-27 2011-08-17 株式会社村田製作所 コイル装置
US6764869B2 (en) 2001-09-12 2004-07-20 Formfactor, Inc. Method of assembling and testing an electronics module
US7064953B2 (en) * 2001-12-27 2006-06-20 Formfactor, Inc. Electronic package with direct cooling of active electronic components
US6891385B2 (en) 2001-12-27 2005-05-10 Formfactor, Inc. Probe card cooling assembly with direct cooling of active electronic components
US6650456B2 (en) * 2002-04-11 2003-11-18 Triquint Technology Holding Co. Ultra-high frequency interconnection using micromachined substrates
US7694246B2 (en) * 2002-06-19 2010-04-06 Formfactor, Inc. Test method for yielding a known good die
JP3918708B2 (ja) * 2002-10-08 2007-05-23 セイコーエプソン株式会社 回路基板及びその製造方法、転写チップ、転写元基板、電気光学装置、電子機器
US7135704B2 (en) * 2003-08-14 2006-11-14 Lockhead Martin Corporation VCSEL settling fixture
US7024763B2 (en) 2003-11-26 2006-04-11 Formfactor, Inc. Methods for making plated through holes usable as interconnection wire or probe attachments
US20050108875A1 (en) * 2003-11-26 2005-05-26 Mathieu Gaetan L. Methods for making vertical electric feed through structures usable to form removable substrate tiles in a wafer test system
JP2005311205A (ja) * 2004-04-23 2005-11-04 Nec Corp 半導体装置
CN1304189C (zh) * 2004-08-24 2007-03-14 宇东电浆科技股份有限公司 热塑性固定装置和热塑性固定装置处理方法
JP2006339553A (ja) * 2005-06-06 2006-12-14 Fuji Electric Device Technology Co Ltd 薄膜磁気誘導素子およびその製造方法
JP4581864B2 (ja) * 2005-06-21 2010-11-17 パナソニック電工株式会社 半導体基板への貫通配線の形成方法
KR100731351B1 (ko) * 2006-02-01 2007-06-21 삼성전자주식회사 탄성 표면파 디바이스 웨이퍼 레벨 패키지 및 그 패키징방법
US20080073778A1 (en) * 2006-09-27 2008-03-27 Texas Instruments Incorporated Two-way heat extraction from packaged semiconductor chips
US7479794B2 (en) * 2007-02-28 2009-01-20 Sv Probe Pte Ltd Spring loaded probe pin assembly
US7928582B2 (en) * 2007-03-09 2011-04-19 Micron Technology, Inc. Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces
US7688077B2 (en) * 2007-08-23 2010-03-30 Advantest Corporation Test system and daughter unit
CN101316014B (zh) * 2007-10-17 2012-02-01 番禺得意精密电子工业有限公司 电连接装置及其组装方法
JP5351071B2 (ja) * 2009-02-24 2013-11-27 株式会社アドバンテスト テスト部ユニット、テストヘッドおよび電子部品試験装置
DE102009022659B4 (de) 2009-05-26 2012-01-19 Semikron Elektronik Gmbh & Co. Kg Kontakteinrichtung für ein Leistungshalbleitermodul
TWI405375B (zh) * 2009-11-13 2013-08-11 Unimicron Technology Corp 電連接器
JP5777997B2 (ja) * 2011-03-07 2015-09-16 日本特殊陶業株式会社 電子部品検査装置用配線基板およびその製造方法
JP5798435B2 (ja) 2011-03-07 2015-10-21 日本特殊陶業株式会社 電子部品検査装置用配線基板およびその製造方法
KR101149759B1 (ko) * 2011-03-14 2012-06-01 리노공업주식회사 반도체 디바이스의 검사장치
JP5690678B2 (ja) * 2011-07-19 2015-03-25 日本特殊陶業株式会社 電子部品検査装置用配線基板およびその製造方法
CN102891116B (zh) * 2011-07-20 2015-06-10 讯芯电子科技（中山）有限公司 内埋元件封装结构及制造方法
CN103325773A (zh) * 2012-03-22 2013-09-25 民瑞科技股份有限公司 集成电路的封装结构
JP6341634B2 (ja) * 2013-05-28 2018-06-13 新光電気工業株式会社 プローブガイド板及びその製造方法、半導体検査装置
US9252138B2 (en) * 2014-05-27 2016-02-02 General Electric Company Interconnect devices for electronic packaging assemblies
EP2962799B8 (de) * 2014-07-04 2016-10-12 ABB Schweiz AG Halbleitermodul mit Ultraschall geschweißten Anschlüssen
CN104251923B (zh) * 2014-09-17 2017-06-30 大族激光科技产业集团股份有限公司 二线测试探针装置及其应用方法
US9530749B2 (en) * 2015-04-28 2016-12-27 Invensas Corporation Coupling of side surface contacts to a circuit platform
US10468363B2 (en) 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts
WO2017091591A1 (en) 2015-11-25 2017-06-01 Formfactor, Inc. Floating nest for a test socket
JP6706076B2 (ja) * 2016-01-14 2020-06-03 新光電気工業株式会社 プローブガイド板及びその製造方法とプローブ装置
CN106983966B (zh) * 2017-03-31 2022-05-20 四川华川工业有限公司 一种钢化玻璃自动破碎装置
RU2657460C1 (ru) * 2017-05-10 2018-06-14 Открытое акционерное общество "ОКБ-Планета" ОАО "ОКБ-Планета" Контактное устройство
US10446729B1 (en) * 2018-03-22 2019-10-15 Innolux Corporation Display device having an electronic device disposed on a first pad and a second pad
CN109300859B (zh) * 2018-09-18 2020-08-28 苏州施密科微电子设备有限公司 一种半导体芯片封装框架
JPWO2021100449A1 (zh) * 2019-11-21 2021-05-27
TWI799887B (zh) * 2021-06-08 2023-04-21 進聯工業股份有限公司 接合器及可組合該接合器之導線端子座結構
JP7182817B1 (ja) 2022-03-14 2022-12-05 ユニコン株式会社 プローブシート及びその製造方法
EP4261872A1 (en) * 2022-04-11 2023-10-18 Nexperia B.V. Molded electronic package with an electronic component encapsulated between two substrates with a spring member between the electronic component and one of the substrates and method for manufacturing the same
TWI811005B (zh) * 2022-07-05 2023-08-01 中華精測科技股份有限公司 可拆式測試裝置

Family Cites Families (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US720677A (en) * 1902-12-18 1903-02-17 Seth A Crone Brake-beam.
NL292051A (zh) * 1962-04-27
US3939831A (en) * 1974-03-04 1976-02-24 Intreprinderea Flacara Rosie Process for preparing medicinal dressings
US3939381A (en) * 1974-03-22 1976-02-17 Mcm Industries, Inc. Universal burn-in fixture
GB1530786A (en) * 1974-12-30 1978-11-01 Trw Inc Electrical connector
FR2322465A1 (fr) * 1975-08-29 1977-03-25 Doloise Metallurgique Dispositif de raccordement pour composants munis de fiches
DE2936615C2 (de) * 1979-09-11 1985-03-28 Brown, Boveri & Cie Ag, 6800 Mannheim Schutzvorrichtung
CA1186418A (en) * 1981-08-14 1985-04-30 Allen J. Wright Electrostatic discharge protected integrated circuit module
US4477134A (en) * 1981-08-14 1984-10-16 Hewlett-Packard Company Electrostatic discharge protected integrated circuit module
US4711024A (en) * 1981-10-30 1987-12-08 Honeywell Information Systems Inc. Method for making testable electronic assemblies
US4511201A (en) * 1982-11-05 1985-04-16 At&T Bell Laboratories Module mounting assembly
US4553192A (en) * 1983-08-25 1985-11-12 International Business Machines Corporation High density planar interconnected integrated circuit package
US5917707A (en) * 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
JPS62229896A (ja) * 1986-03-29 1987-10-08 株式会社東芝 印刷配線基板
US5195237A (en) * 1987-05-21 1993-03-23 Cray Computer Corporation Flying leads for integrated circuits
JPH063820B2 (ja) 1988-07-25 1994-01-12 松下電器産業株式会社 半導体装置の実装方法
US5036431A (en) * 1988-03-03 1991-07-30 Ibiden Co., Ltd. Package for surface mounted components
DE3903060A1 (de) * 1989-02-02 1990-08-09 Minnesota Mining & Mfg Vorrichtung zum pruefen von integrierten schaltungsanordnungen
US4940181A (en) * 1989-04-06 1990-07-10 Motorola, Inc. Pad grid array for receiving a solder bumped chip carrier
US4922376A (en) * 1989-04-10 1990-05-01 Unistructure, Inc. Spring grid array interconnection for active microelectronic elements
US4933808A (en) * 1989-05-11 1990-06-12 Westinghouse Electric Corp. Solderless printed wiring board module and multi-module assembly
US4966556A (en) * 1989-06-13 1990-10-30 General Datacomm, Inc. Electrical connector for direct connection to plated through holes in circuit board
US5366380A (en) * 1989-06-13 1994-11-22 General Datacomm, Inc. Spring biased tapered contact elements for electrical connectors and integrated circuit packages
JPH03142847A (ja) 1989-10-30 1991-06-18 Hitachi Ltd 半導体集積回路装置
JPH0711422Y2 (ja) * 1989-12-25 1995-03-15 山一電機工業株式会社 Ｉｃソケット
AU645283B2 (en) * 1990-01-23 1994-01-13 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5663654A (en) * 1990-08-29 1997-09-02 Micron Technology, Inc. Universal wafer carrier for wafer level die burn-in
US5207585A (en) * 1990-10-31 1993-05-04 International Business Machines Corporation Thin interface pellicle for dense arrays of electrical interconnects
US5578934A (en) * 1991-06-04 1996-11-26 Micron Technology, Inc. Method and apparatus for testing unpackaged semiconductor dice
US5239260A (en) * 1991-06-28 1993-08-24 Digital Equipment Corporation Semiconductor probe and alignment system
US5175491A (en) * 1991-09-18 1992-12-29 Sgs-Thomson Microelectronics, Inc. Integrated circuit testing fixture
JPH0649656A (ja) 1992-08-04 1994-02-22 Vacuum Metallurgical Co Ltd ガス・デポジション法による超微粒子膜の形成法およびその形成装置
US5489854A (en) * 1993-04-01 1996-02-06 Analog Devices, Inc. IC chip test socket with double-ended spring biased contacts
US5329423A (en) * 1993-04-13 1994-07-12 Scholz Kenneth D Compressive bump-and-socket interconnection scheme for integrated circuits
US5811982A (en) * 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
JP3053507B2 (ja) 1993-06-11 2000-06-19 裕子 鈴木 ドーム型羽毛ふとん
US5500605A (en) * 1993-09-17 1996-03-19 At&T Corp. Electrical test apparatus and method
US5772451A (en) 1993-11-16 1998-06-30 Form Factor, Inc. Sockets for electronic components and methods of connecting to electronic components
US6835898B2 (en) * 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US6064213A (en) * 1993-11-16 2000-05-16 Formfactor, Inc. Wafer-level burn-in and test
US6336269B1 (en) 1993-11-16 2002-01-08 Benjamin N. Eldridge Method of fabricating an interconnection element
US6525555B1 (en) * 1993-11-16 2003-02-25 Formfactor, Inc. Wafer-level burn-in and test
US5475317A (en) * 1993-12-23 1995-12-12 Epi Technologies, Inc. Singulated bare die tester and method of performing forced temperature electrical tests and burn-in
GB9400384D0 (en) 1994-01-11 1994-03-09 Inmos Ltd Circuit connection in an electrical assembly
US5455390A (en) * 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
WO1995034825A1 (fr) * 1994-06-15 1995-12-21 Advantest Corporation Sabot pour manipulateur de circuits integres
US5476818A (en) * 1994-08-19 1995-12-19 Motorola, Inc. Semiconductor structure and method of manufacture
US5495667A (en) * 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
EP1408337A3 (en) * 1994-11-15 2007-09-19 FormFactor, Inc. Probe card assembly
KR100366746B1 (ko) 1994-11-15 2003-01-09 폼팩터, 인크. 2개의 전자 장치의 조립체
US6229320B1 (en) * 1994-11-18 2001-05-08 Fujitsu Limited IC socket, a test method using the same and an IC socket mounting mechanism
JPH1069955A (ja) 1996-08-28 1998-03-10 Fujitsu Ltd Ｉｃソケット及びこれを用いた試験方法及びｉｃソケットの実装機構
JPH08263092A (ja) 1995-03-23 1996-10-11 N T T Data Tsushin Kk 応答音声生成方法および音声対話システム
ATE213873T1 (de) * 1995-04-24 2002-03-15 Infineon Technologies Ag Halbleiter-speichervorrichtung unter verwendung eines ferroelektrischen dielektrikums und verfahren zur herstellung
EP0742682B1 (en) * 1995-05-12 2005-02-23 STMicroelectronics, Inc. Low-profile socketed integrated circuit packaging system
US6002266A (en) * 1995-05-23 1999-12-14 Digital Equipment Corporation Socket including centrally distributed test tips for testing unpackaged singulated die
US20020004320A1 (en) * 1995-05-26 2002-01-10 David V. Pedersen Attaratus for socketably receiving interconnection elements of an electronic component
US5578870A (en) * 1995-08-03 1996-11-26 Precision Connector Designs, Inc. Top loading test socket for ball grid arrays
US5874780A (en) * 1995-07-27 1999-02-23 Nec Corporation Method of mounting a semiconductor device to a substrate and a mounted structure
US5714803A (en) * 1995-07-28 1998-02-03 Sgs-Thomson Microelectronics, Inc. Low-profile removable ball-grid-array integrated circuit package
US5686842A (en) * 1995-08-31 1997-11-11 Nat Semiconductor Corp Known good die test apparatus and method
JP2891665B2 (ja) 1996-03-22 1999-05-17 株式会社日立製作所 半導体集積回路装置およびその製造方法
EP0898712B1 (en) 1996-05-17 2003-08-06 Formfactor, Inc. Wafer-level burn-in and test
US5865639A (en) * 1996-06-25 1999-02-02 Texas Instruments Incorporated Burn-in test socket apparatus
DE69734158T2 (de) * 1996-09-13 2006-06-22 International Business Machines Corp. Prüfkopfstruktur mit mehreren getrennten isolierten prüfspitzen
US5764486A (en) * 1996-10-10 1998-06-09 Hewlett Packard Company Cost effective structure and method for interconnecting a flip chip with a substrate
US6060891A (en) * 1997-02-11 2000-05-09 Micron Technology, Inc. Probe card for semiconductor wafers and method and system for testing wafers
US6025730A (en) * 1997-03-17 2000-02-15 Micron Technology, Inc. Direct connect interconnect for testing semiconductor dice and wafers
WO1999000844A2 (en) * 1997-06-30 1999-01-07 Formfactor, Inc. Sockets for semiconductor devices with spring contact elements
JPH1172534A (ja) * 1997-08-28 1999-03-16 Mitsubishi Electric Corp テスト端子付き半導体装置およびｉｃソケット
US6018249A (en) * 1997-12-11 2000-01-25 Micron Technolgoy, Inc. Test system with mechanical alignment for semiconductor chip scale packages and dice
US6292003B1 (en) * 1998-07-01 2001-09-18 Xilinx, Inc. Apparatus and method for testing chip scale package integrated circuits
US6031282A (en) * 1998-08-27 2000-02-29 Advantest Corp. High performance integrated circuit chip package
US6627483B2 (en) 1998-12-04 2003-09-30 Formfactor, Inc. Method for mounting an electronic component
US7694246B2 (en) 2002-06-19 2010-04-06 Formfactor, Inc. Test method for yielding a known good die
US6920689B2 (en) 2002-12-06 2005-07-26 Formfactor, Inc. Method for making a socket to perform testing on integrated circuits

Also Published As

Publication number Publication date
DE69922656D1 (de) 2005-01-20
US7534654B2 (en) 2009-05-19
DE69937416D1 (de) 2007-12-06
TW548756B (en) 2003-08-21
US20020004320A1 (en) 2002-01-10
WO2000001208A1 (en) 2000-01-06
EP1092338A1 (en) 2001-04-18
US7202677B2 (en) 2007-04-10
DE69922656T2 (de) 2005-11-03
CN1307793A (zh) 2001-08-08
US20070285114A1 (en) 2007-12-13
US20040152348A1 (en) 2004-08-05
EP1092338B1 (en) 2004-12-15
JP3723079B2 (ja) 2005-12-07
JP2002519872A (ja) 2002-07-02
DE69937416T2 (de) 2008-07-24
JP2006013526A (ja) 2006-01-12

Similar Documents

Publication Publication Date Title
CN1197443C (zh) 带有弹性封装的一电子器件的组件
CN1145802C (zh) 微电子弹簧接触元件及电子部件
CN1281966C (zh) 探针片、探针卡及半导体检查装置
CN1206719C (zh) 接触器、其制造方法、探针板. 及半导体器件测试插座
CN1290170C (zh) 探针板和半导体芯片的测试方法、电容器及其制造方法
CN1118099C (zh) 将中间连接元件装设至电子组件的端子上的方法
CN1276259C (zh) 光刻接触元件
CN1256761C (zh) 接触构件及其生产方法以及采用该接触构件的探针接触组件
CN101520470B (zh) 探测卡及其制造方法和半导体检测装置及其制造方法
CN1151009C (zh) 利用牺牲基片制作互连件和接点
CN101069277A (zh) 包括检测探针的探针卡制造方法和探针卡、探针卡检查系统
CN1222776C (zh) 探测卡及其制造方法
CN1612321A (zh) 半导体集成电路器件的制造方法
CN1431518A (zh) 用于测试小型装置和部件的接触器
CN1797732A (zh) 半导体检查装置以及半导体装置的制造方法
CN1745502A (zh) 用于印刷电路板的互连装置、制造该装置的方法及具有该装置的互连组件
CN1816748A (zh) 探针板及使用探针片或探针板的半导体检测装置及半导体装置的制造方法
CN1670540A (zh) 电气信号连接装置、及使用此装置之探针组装体及探测器装置
CN1345086A (zh) 半导体集成电路器件的制造方法及其测试设备
CN1802775A (zh) 采用匹配装置的器件探测
CN1529352A (zh) 测试具有许多半导体器件的晶片的探针卡及其制作方法
CN1398448A (zh) 触点结构及其制造方法以及使用该触点结构的探针接触装置
CN1350325A (zh) 接触构件及其生产方法以及采用该接触构件的探针接触组件
CN1774839A (zh) 电连接器及制造方法
US20140179031A1 (en) Designed asperity contactors, including nanospikes, for semiconductor test using a package, and associated systems and methods

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20050413

Termination date: 20100630