CN1213851A - 带难熔金属衬里的铜栓结构 - Google Patents

带难熔金属衬里的铜栓结构 Download PDF

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CN1213851A
CN1213851A CN98119730A CN98119730A CN1213851A CN 1213851 A CN1213851 A CN 1213851A CN 98119730 A CN98119730 A CN 98119730A CN 98119730 A CN98119730 A CN 98119730A CN 1213851 A CN1213851 A CN 1213851A
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J·M·E·哈柏
R·M·格夫肯
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Abstract

提供一种具有增加电迁移寿命的多层互连电子元件。互连为栓的形式,包括具有一沿侧壁的难熔金属扩散阻挡衬里的垂直侧壁。在栓的底部没有阻挡层,栓的底部接触元件介质层上的金属化敷层。附着层形成于栓的底部和金属化敷层的表面之间,附着层可以连续或不连续。附着层优选在元件的制备或使用期间通过加热溶解在栓或金属化敷层的金属如铝。优选的元件利用了双金属镶嵌结构。

Description

带难熔金属衬里的铜栓结构
本发明涉及在元件内具有电互连结构的电子元件，如半导体器件、多层薄膜结构和多层陶瓷结构等，特别涉及将结构的一层上的金属化敷层电连接到另一层上的金属化敷层的垂直互连结构，并且该互连结构和电子元件具有增加的电迁移寿命。
多层电子元件向如计算机、通讯、军事和消费应用等中的高性能系统提供了一种有吸引力的封装解决办法。这些电子元件可在给定电子元件尺寸下提供高密度的互连和增加电路的能力。
一般来说，多层电子元件包括多个电介质材料层，在每层上具有通孔、焊盘、将焊盘连接到通孔的带以及布线形式的金属化敷层。介质层中的通孔或其它开口从一层延伸到另一层，并且这些开口填充有导电材料并将一层上的金属化敷层电连接到另一层上的金属化敷层，用于现今工业中使用的高密度电子元件装置。
多层电子元件的一个重要方案是层之间的通孔或开口，在其中施加导电材料以提供不同层上金属化敷层之间的电接触。概括地说，典型的多层电子元件由许多介质材料层构成，例如硅氧化物、氟化硅氧化物、包括聚酰亚胺和氟化聚酰亚胺的高聚物、陶瓷、碳以及其它介质材料。在现有技术中称做“金属镶嵌工艺(Damascene Process)”的加工顺序中，使用已知的技术如使用曝光后限定出布线图案的光刻胶材料构图介质层。显影后，光刻胶起掩模的作用，通过它用如等离子体腐蚀或反应离子腐蚀等的去杂质腐蚀工艺穿过掩模除去介质材料的图案。使用金属镶嵌工艺，在介质层中形成限定布线图案的开口，由介质层的一个表面延伸到介质层的另一表面。然后使用如电镀、化学镀、化学汽相淀积、物理汽相淀积或这些方法的组合等填充技术用金属填充这些布线图案。该工艺包括通过用如化学机械抛光的方法去除过量材料使金属平面化。在单金属镶嵌工艺中，在介质层中附加地形成有通孔或开口并在其中填充金属化敷层以提供布线级的层之间的电接触。在双金属镶嵌工艺中，在填充金属化敷层之前，通孔和布线图案开口都形成在介质层中。该工艺简化了工序并消除了一些内部界面。对电子元件中的每一层继续进行这些工序直到完成电子元件。
在图4中，显示出了现有技术的双金属镶嵌线。示出介质层11a和11b，其上有水平阻挡层16，层11b上有金属化敷层12，层11a内有金属化敷层12a和栓14。示出的栓14和金属化敷层12a由扩散阻挡衬里15的垂直壁以及包括为栓14的底部和金属化敷层12的上表面之间提供扩散阻挡的栓的底部衬里的水平衬里15a包围。已显示出这种类型的结构提供具有低电迁移寿命的互连电子元件。
介质材料提供了铜布线元件之间的电绝缘和电隔离。介质层中的开口统称为通孔，当填充有导电材料时，通常称做栓。栓提供了电子元件的不同层上水平铜金属化敷层之间的垂直互连。
为避免金属和介质之间的金属扩散，也称做衬里的阻挡层包括在结构中以容纳铜或其它金属，并提供铜衬里和栓与介质或其它金属化敷层的改善的附着力。
对于通孔，阻挡层通常为如Ta或TaN的难熔金属，不但对通孔和介质之间铜金属的扩散形成阻挡，而且在铜金属和导体布线级下面或上面的金属化敷层之间形成阻挡。通常阻挡层形成在通孔内的两个侧壁上及其底部，形成阻挡层。当镀铜并填充通孔时，阻挡层将栓与介质、栓与和它进行电连接的下和上层金属化敷层分离。现已发现当电子元件中的铜布线暴露在高电路密度中很长一段时间时，阻挡层会在铜栓或金属化敷层中产生孔隙(取决于电流的方向)，并导致电路开路的故障。发生该故障需要的时间称做电迁移寿命，它随栓和金属化敷层材料以及阻挡层材料而变。
相关的申请由本发明的受让人于1997年5月19日申请，题目为“在通孔中形成自对准铜扩散阻挡层的方法”，目的在于在通孔的侧壁上形成铜扩散阻挡层。
考虑到现有技术的问题和不足，因此本发明的一个目的是提供一种包含使用单金属镶嵌工艺或双金属镶嵌工艺制成的元件的多层电子元件，所述多层电子元件包括至少一层具有通孔或开口的层，通孔或开口内填充有导电材料形成栓，该栓电连接层上的金属化敷层，并且栓和电子元件的电迁移寿命增加。
本发明的另一目的是提供一种制造多层电子元件的方法，所述多层电子元件具有栓互连并包括使用单金属镶嵌工艺或双金属镶嵌工艺制成的元件，其中栓和电子元件的电迁移寿命增加。
通过说明书，本发明的其它目的和优点将变得显而易见。
本发明中实现了将对于本领域的技术人员可理解的以上和其它目的，本发明的一个方案的多层电子元件包括：至少一个介质层，在该层的两个表面上有金属化敷层；和延伸穿过该层并将一个表面上的金属化敷层连接到另一表面上的金属化敷层的开口(通孔)，这些开口包括：一开口侧壁上的扩散阻挡材料，优选地为难熔金属如钽、钨、氮化钽、氮化钨、氮化硅、氮化钨硅、氮化钛、氮化钛硅；和一侧壁内的导体，该导体填充开口并接触金属化敷层。
在本发明的另一方案中，电子元件的介质材料为多层氧化物、陶瓷或聚酰亚胺(高聚物)，并且氧化层、陶瓷层或其它介质层表面上的金属化敷层为相同的金属，优选为铜。电子元件的介质包括多种材料，通常为硅氧化物、氟氧化物、高聚物、类金刚石碳或旋涂玻璃。
在本发明的又一方案中，在通孔金属化敷层和表面金属化敷层之间提供有一附着层。附着层的作用不是通孔金属化敷层的扩散阻挡层，附着层很薄并且不连续。优选的附着层是铝或铬，最好在电子元件的制造或使用期间附着层融化在通孔和/或表面金属化敷层内。
在本发明的再一方案中，在介质的表面和介质表面的金属化敷层之间形成有一水平的扩散阻挡层，例如当在双金属镶嵌工艺中腐蚀通孔时可作为腐蚀终止扩散阻挡层。
在附带的权利要求书中对相信是新颖的本发明的特征和本发明的元件特性进行了详细的说明。附图仅为图示的目的，并没有按比例画出。然而，参考结合附图进行的详细说明可对关于结构和操作方法的本发明自身有更好地理解。
图1为本发明的电互连多层电子元件的局部剖面透视图。
图2A-2E示出了根据本发明的方法形成双金属镶嵌线的步骤顺序。
图3示出了在互连栓的底部和层金属化敷层之间具有不连续的附着层的本发明电互连多层电子元件的局部剖面透视图。
图4示出了具有双金属镶嵌互连栓且扩散阻挡层位于栓的底部和元件的相邻下层上金属化敷层的上表面之间的现有技术多层电子元件的剖面图。
下面参考图1-3介绍本发明的优选实施例，其中本发明的类似特征用类似的数字表示。在图中不必按比例显示出本发明的特征。
参考图1，以局部剖面透视示意性地示出多层电子元件10的部分，该部分包括集中显示为11和分别显示为11a、11b和11c的层。根据电子元件的应用，层11可以由任何合适的介质材料制成，包括如硅氧化物、氟氧化物、如聚酰亚胺的高聚物、类金刚石碳或旋涂玻璃等材料。示出的层其上具有布线或线12和12a以及互连通孔或栓14形式的金属化敷层。可以看出栓14电连接布线12a与布线12。金属化敷层12、12a和14由如铜等的导体形成。
示出的层11a-11c分别由水平阻挡层16和28分隔，阻挡层16和28可以相同或不同且可以防止铜金属化敷层从一层扩散到下一层。层28可以是当化学腐蚀元件时也起腐蚀终止作用的材料。示出的垂直阻挡扩散层(衬里)15形成金属化敷层12和12a以及栓14的外壁。可以在栓14和金属化敷层12或金属化敷层12a中任意一个之间避免衬里15，以增加所有金属层的电迁移寿命并由此增加元件的使用寿命。下面参考图2A-2E介绍垂直衬里15的形成。
衬里15可以是提供布线和/或栓金属化敷层以及介质之间扩散阻挡的任何适宜材料。优选的衬里材料为难熔材料如钽、钨、氮化钽、氮化钨、氮化硅、氮化钽硅、氮化钨硅、氮化钛、氮化钛硅，优选含钽的材料。衬里的厚度通常为2nm到100nm。
关于图2A-2E，显示了在含有双金属线的多层电子元件10中本发明的互连栓的制造步骤顺序。在图2A中，显示出的现有技术公知的典型的双金属线包括绝缘(介质)层11a、11b和11c，其中的水平表面上具有扩散阻挡层16和28。当在用于金属线的层11a中腐蚀开口时，扩散阻挡层28也起腐蚀终止的作用。衬里层15形成在双金属镶嵌结构的所有暴露表面上。水平表面上的衬里用15A表示。最好衬里材料15与水平扩散阻挡层16和28不同。可以看出衬里15也覆盖在通孔14底部的金属化敷层12的上表面。在图2B中，箭头所示的选择性腐蚀用来从通孔14的下水平表面和终止于腐蚀终止层28的介质11a和11b的水平表面腐蚀水平衬里15a。选择性腐蚀优选使用如能产生挥发性腐蚀产物的氯气等气体的活性离子腐蚀。选择性腐蚀形成侧壁间隔层15，这在本领域是公知的。有必要使腐蚀剂终止于腐蚀终止层28，以便保留该层提供扩散阻挡层。
然后使用公知的技术如薄镀、物理汽相淀积、化学汽相淀积或化学镀施加铜籽晶层(seed layer)19，如图2C所示，籽晶层19覆盖介质11a、阻挡层28、通孔14的侧壁和通孔的底部。然后如图2D所示电镀铜层24，填充槽22和通孔14。也可以通过化学汽相淀积或物理汽相淀积来淀积铜24。此外，可以使用化学镀形成金属化敷层。在这些情况中，通常不需要单独的铜籽晶层。
然后将铜层24平面化到层11a的表面，形成完成的栓14和金属化敷层12a。为清楚起见，金属化敷层12a和铜籽晶层19与淀积的铜24一起显示为金属化敷层12a和栓14。在金属化敷层12和栓14之间或金属化敷层12a和栓14之间没有无铜层。因此，栓14和两个金属化敷层的连接可以避免其扩散阻挡，增加了电迁移寿命。
可以就在淀积铜籽晶层19之前或如果不使用铜籽晶层，就在CU层14之前使用附着层。在被镀的元件中，如果使用了铜籽晶层(未显示在图3中)，铜将填充和铜籽晶层19一起的开口14，并仅通过不连续的附着层18与金属化敷层12分离(如图3所示)。附着层不是阻挡层，通常为如铝或铬等的金属。附着层18的厚度约0.5到20nm，优选约5nm。如果使用附着层，附着层最好在制造元件或使用元件期间通过加热溶解在加热时的栓金属和/或金属化敷层中。因此，在最终的电子元件结构中，即使使用了附着层18，栓材料将基本上直接连接(粘接)到金属线12。
虽然结合具体的优选实施例详细地介绍了本发明，但显而易见，根据以上的介绍作出许多替换、修改和变形对本领域的技术人员来说是显然的。因此附带的权利要求书将包含落入本发明实际范围和精神的任何这些替换、修改和变形。

Claims (30)

1．一种用于将一层上的金属化敷层连接到延伸至所述金属化敷层的槽或通孔的电子元件中的互连结构，电子元件的电迁移寿命增加，特征在于包括：
包括第一材料的第一导体层；
所述第一导体层上的一介质；
一槽或通孔，穿过所述介质延伸到所述第一导体层；
第一衬里，沿所述槽或通孔的侧壁，用于向所述介质提供一扩散阻挡层；
包括所述第一材料的第二导体层，所述第一材料填充电接触所述第一导体层的所述槽或通孔，所述第一衬里不位于所述第一和第二导体层之间。
2．根据权利要求1的互连，特征在于所述第一导体层和第二导体层包括铜。
3．根据权利要求1的互连，特征在于所述介质包括硅氧化物、氟氧化物、高聚物、类金刚石碳和旋涂玻璃中的一种。
4．根据权利要求1的互连，特征在于一附着层位于所述第一和所述第二导体层之间。
5．根据权利要求4的互连，特征在于所述附着层不是对铜的扩散阻挡层。
6．根据权利要求5的互连，特征在于所述附着层不连续。
7．根据权利要求5的互连，特征在于所述附着层为一种不是阻挡铜扩散的材料。
8．根据权利要求7的互连，特征在于所述附着层为铝和铬中的一种。
9．根据权利要求1的互连，特征在于一水平层为沿槽中一暴露的水平表面，水平层由第二介质形成，水平层提供所述第二导体和所述第一介质之间一扩散阻挡层，所述水平层由不同于第一衬里的材料形成。
10．根据权利要求9的互连，特征在于所述水平层是对第一介质的腐蚀终止层。
11．一种具有一增加的电迁移寿命的多层电子元件，特征在于包括：
具有金属化敷层于其上的多个介质层；
槽或通孔形式的开口，延伸穿过至少一层，并连接槽或通孔的下表面上的金属化敷层；
沿所述槽或通孔侧壁的第一衬里，用于向介质提供一扩散阻挡层；以及
一导体，填充电接触所述金属化敷层的所述槽或通孔，所述第一衬里不位于所述第一和第二导体层之间。
12．根据权利要求11的多层电子元件，特征在于金属化敷层和导体为铜。
13．根据权利要求12的多层电子元件，特征在于具有双金属镶嵌结构。
14．根据权利要求11的多层电子元件，特征在于介质是硅氧化物、氟氧化物、高聚物、类金刚石碳或旋涂玻璃。
15．根据权利要求11的多层电子元件，特征在于在金属化敷层和导体层之间存在附着层。
16．根据权利要求15的多层电子元件，特征在于所述附着层不是对铜的扩散阻挡层。
17．根据权利要求16的多层电子元件，特征在于所述附着层不连续。
18．根据权利要求15的多层电子元件，特征在于附着层是制造电子元件或使用电子元件期间溶解在导体或金属化敷层内的材料。
19．根据权利要求18的多层电子元件，特征在于附着层为铝、铬。
20．根据权利要求11的多层电子元件，特征在于一水平扩散阻挡层设置在层之间，用于提供它的表面上金属化敷层和介质之间的扩散阻挡，所述水平层由不同于第一衬里的材料形成。
21．根据权利要求20的多层电子元件，特征在于水平层是对介质的腐蚀终止层。
22．一种制造具有增加的电迁移寿命的多层电子元件的方法，特征在于包括：
在做电子元件时，用金属化敷层形成其上的介质层层叠层地形成多层电子元件，并形成延伸穿过至少一层的开口以连接层表面上的金属化敷层；
在开口内形成一扩散阻挡层衬里；
使用选择性腐蚀从开口的底部腐蚀衬里，保留开口侧壁上的衬里；以及
用一导体填充开口以提供接触金属化敷层的导体。
23．根据权利要求22的方法，特征在于金属化敷层和导体为铜。
24．根据权利要求23的方法，特征在于元件内部为双金属镶嵌结构。
25．根据权利要求22的方法，特征在于介质包括硅氧化物、氟氧化物、高聚物、类金刚石碳或旋涂玻璃。
26．根据权利要求22的方法，特征在于在金属化敷层和导体层之间存在一附着层。
27．根据权利要求26的方法，特征在于附着层不是对铜的扩散阻挡层。
28．根据权利要求26的方法，特征在于附着层不连续。
29．根据权利要求28的方法，特征在于附着层为铝、铬。
30．根据权利要求22的方法，特征在于沿每个介质层的表面存在一水平介质层，将它的表面上的金属化敷层与介质分离。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100375266C (zh) * 2004-01-14 2008-03-12 国际商业机器公司 牺牲无机聚合物金属间介质镶嵌布线和过孔衬里
CN101728358B (zh) * 2008-10-17 2013-01-23 日立电线株式会社 配线结构及配线结构的制造方法
CN104025263A (zh) * 2011-12-30 2014-09-03 英特尔公司 自封闭的非对称互连结构
US9455224B2 (en) 2012-12-04 2016-09-27 Intel Corporation Semiconductor interconnect structures

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3515363B2 (ja) * 1998-03-24 2004-04-05 株式会社東芝 半導体装置の製造方法
US6169024B1 (en) * 1998-09-30 2001-01-02 Intel Corporation Process to manufacture continuous metal interconnects
US6518591B1 (en) * 1998-12-02 2003-02-11 Cypress Semiconductor Corporation Contact monitor, method of forming same and method of analizing contact-, via- and/or trench-forming processes in an integrated circuit
US6333560B1 (en) * 1999-01-14 2001-12-25 International Business Machines Corporation Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies
JP4108228B2 (ja) * 1999-07-15 2008-06-25 富士通株式会社 半導体装置の製造方法
KR100574922B1 (ko) * 1999-07-16 2006-05-02 삼성전자주식회사 반도체장치의 다층배선구조 및 그 제조방법
JP2001044202A (ja) 1999-07-30 2001-02-16 Nec Corp 半導体装置及びその製造方法
US6399983B1 (en) * 1999-09-02 2002-06-04 Micron Technology, Inc. Reduction of shorts among electrical cells formed on a semiconductor substrate
US6221780B1 (en) * 1999-09-29 2001-04-24 International Business Machines Corporation Dual damascene flowable oxide insulation structure and metallic barrier
JP2001250863A (ja) * 1999-12-27 2001-09-14 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6284657B1 (en) * 2000-02-25 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Non-metallic barrier formation for copper damascene type interconnects
US6858937B2 (en) * 2000-03-02 2005-02-22 Micron Technology, Inc. Backend metallization method and device obtained therefrom
TW503518B (en) * 2000-04-19 2002-09-21 Ibm Interconnect via structure and method
US6528180B1 (en) * 2000-05-23 2003-03-04 Applied Materials, Inc. Liner materials
US6541861B2 (en) * 2000-06-30 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method including forming step of SOI structure and semiconductor device having SOI structure
US6501180B1 (en) * 2000-07-19 2002-12-31 National Semiconductor Corporation Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures
US6358842B1 (en) * 2000-08-07 2002-03-19 Chartered Semiconductor Manufacturing Ltd. Method to form damascene interconnects with sidewall passivation to protect organic dielectrics
KR100504548B1 (ko) * 2000-12-14 2005-08-03 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성 방법
US6479898B1 (en) * 2001-01-11 2002-11-12 Advanced Micro Devices, Inc. Dielectric treatment in integrated circuit interconnects
US6472757B2 (en) * 2001-01-11 2002-10-29 Advanced Micro Devices, Inc. Conductor reservoir volume for integrated circuit interconnects
US6555909B1 (en) * 2001-01-11 2003-04-29 Advanced Micro Devices, Inc. Seedless barrier layers in integrated circuits and a method of manufacture therefor
AU2002241936A1 (en) * 2001-01-22 2002-07-30 N.V.Bekaert S.A. Copper diffusion barriers
KR100385227B1 (ko) 2001-02-12 2003-05-27 삼성전자주식회사 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법
US6689684B1 (en) * 2001-02-15 2004-02-10 Advanced Micro Devices, Inc. Cu damascene interconnections using barrier/capping layer
EP1233449A3 (en) * 2001-02-15 2006-03-01 Interuniversitair Micro-Elektronica Centrum A method of fabricating a semiconductor device
US6586842B1 (en) 2001-02-28 2003-07-01 Advanced Micro Devices, Inc. Dual damascene integration scheme for preventing copper contamination of dielectric layer
US6440847B1 (en) 2001-04-30 2002-08-27 Taiwan Semiconductor Manufacturing Company Method for forming a via and interconnect in dual damascene
US6534865B1 (en) * 2001-06-12 2003-03-18 Advanced Micro Devices, Inc. Method of enhanced fill of vias and trenches
US6555461B1 (en) 2001-06-20 2003-04-29 Advanced Micro Devices, Inc. Method of forming low resistance barrier on low k interconnect
US6509267B1 (en) 2001-06-20 2003-01-21 Advanced Micro Devices, Inc. Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer
US6455413B1 (en) * 2001-06-27 2002-09-24 Advanced Micro Devices, Inc. Pre-fill CMP and electroplating method for integrated circuits
US6531780B1 (en) * 2001-06-27 2003-03-11 Advanced Micro Devices, Inc. Via formation in integrated circuit interconnects
US20030008243A1 (en) * 2001-07-09 2003-01-09 Micron Technology, Inc. Copper electroless deposition technology for ULSI metalization
US6611039B2 (en) * 2001-09-28 2003-08-26 Hewlett-Packard Development Company, L.P. Vertically oriented nano-fuse and nano-resistor circuit elements
US6657304B1 (en) * 2002-06-06 2003-12-02 Advanced Micro Devices, Inc. Conformal barrier liner in an integrated circuit interconnect
US20040036171A1 (en) * 2002-08-22 2004-02-26 Farnworth Warren M. Method and apparatus for enabling a stitch wire bond in the absence of discrete bump formation, semiconductor device assemblies and electronic systems including same
US7056826B2 (en) * 2003-01-07 2006-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming copper interconnects
JP2005005370A (ja) 2003-06-10 2005-01-06 Renesas Technology Corp 半導体装置の配線構造
JP4537753B2 (ja) * 2003-06-10 2010-09-08 大日本印刷株式会社 多層配線基板およびその製造方法
US20050026416A1 (en) * 2003-07-31 2005-02-03 International Business Machines Corporation Encapsulated pin structure for improved reliability of wafer
DE102004021239B4 (de) * 2004-04-30 2017-04-06 Infineon Technologies Ag Lange getemperte integrierte Schaltungsanordnungen und deren Herstellungsverfahren
JP2008502150A (ja) * 2004-06-03 2008-01-24 エピオン コーポレーション 改善された二重ダマシン集積構造およびその製造方法
KR100621548B1 (ko) * 2004-07-30 2006-09-14 삼성전자주식회사 반도체 소자의 금속 배선 형성 방법
US20070184656A1 (en) * 2004-11-08 2007-08-09 Tel Epion Inc. GCIB Cluster Tool Apparatus and Method of Operation
CN100472739C (zh) * 2004-11-08 2009-03-25 Tel艾派恩有限公司 铜互连布线和形成铜互连布线的方法
US7799683B2 (en) * 2004-11-08 2010-09-21 Tel Epion, Inc. Copper interconnect wiring and method and apparatus for forming thereof
US7514725B2 (en) * 2004-11-30 2009-04-07 Spire Corporation Nanophotovoltaic devices
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
JP2008078183A (ja) * 2006-09-19 2008-04-03 Elpida Memory Inc 相変化メモリ装置および相変化メモリ装置の製造方法
TWI365517B (en) * 2008-05-23 2012-06-01 Unimicron Technology Corp Circuit structure and manufactring method thereof
US7919409B2 (en) * 2008-08-15 2011-04-05 Air Products And Chemicals, Inc. Materials for adhesion enhancement of copper film on diffusion barriers
JP5565095B2 (ja) * 2010-05-25 2014-08-06 富士通株式会社 配線回路基板の製造方法
US8580687B2 (en) * 2010-09-30 2013-11-12 Infineon Technologies Ag Semiconductor structure and method for making same
US20140147984A1 (en) * 2012-11-27 2014-05-29 United Microelectronics Corp. Semiconductor device and method of fabricating through silicon via structure
US9349691B2 (en) * 2014-07-24 2016-05-24 International Business Machines Corporation Semiconductor device with reduced via resistance
KR102521222B1 (ko) * 2017-11-15 2023-04-12 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US11164778B2 (en) 2019-11-25 2021-11-02 International Business Machines Corporation Barrier-free vertical interconnect structure

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4691435A (en) * 1981-05-13 1987-09-08 International Business Machines Corporation Method for making Schottky diode having limited area self-aligned guard ring
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5221449A (en) * 1990-10-26 1993-06-22 International Business Machines Corporation Method of making Alpha-Ta thin films
JPH05206641A (ja) * 1992-01-29 1993-08-13 Sharp Corp 簡易スルホールプリント配線板の製造方法
JPH05218645A (ja) * 1992-02-05 1993-08-27 Ngk Insulators Ltd 薄膜多層配線基板の製造方法
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
JPH05283362A (ja) * 1992-04-03 1993-10-29 Sony Corp 多層配線の形成方法
US5284801A (en) * 1992-07-22 1994-02-08 Vlsi Technology, Inc. Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric
US5488013A (en) * 1993-12-20 1996-01-30 International Business Machines Corporation Method of forming transverse diffusion barrier interconnect structure
KR0147682B1 (ko) * 1994-05-24 1998-11-02 구본준 반도체 소자의 금속배선 제조방법
US5654232A (en) 1994-08-24 1997-08-05 Intel Corporation Wetting layer sidewalls to promote copper reflow into grooves
US5529953A (en) * 1994-10-14 1996-06-25 Toshiba America Electronic Components, Inc. Method of forming studs and interconnects in a multi-layered semiconductor device
JP3442200B2 (ja) * 1995-08-08 2003-09-02 インターナショナル・ビジネス・マシーンズ・コーポレーション プリント回路基板、プリント回路基板の製造方法
JPH09153545A (ja) * 1995-09-29 1997-06-10 Toshiba Corp 半導体装置及びその製造方法
US5824599A (en) * 1996-01-16 1998-10-20 Cornell Research Foundation, Inc. Protected encapsulation of catalytic layer for electroless copper interconnect
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US6008117A (en) * 1996-03-29 1999-12-28 Texas Instruments Incorporated Method of forming diffusion barriers encapsulating copper
US5904565A (en) * 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6100184A (en) * 1997-08-20 2000-08-08 Sematech, Inc. Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
US6077771A (en) * 1998-04-20 2000-06-20 United Silicon Incorporated Method for forming a barrier layer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100375266C (zh) * 2004-01-14 2008-03-12 国际商业机器公司 牺牲无机聚合物金属间介质镶嵌布线和过孔衬里
CN101728358B (zh) * 2008-10-17 2013-01-23 日立电线株式会社 配线结构及配线结构的制造方法
CN104025263A (zh) * 2011-12-30 2014-09-03 英特尔公司 自封闭的非对称互连结构
US9960110B2 (en) 2011-12-30 2018-05-01 Intel Corporation Self-enclosed asymmetric interconnect structures
TWI637477B (zh) * 2011-12-30 2018-10-01 英特爾股份有限公司 自包圍非對稱內連線結構
US9455224B2 (en) 2012-12-04 2016-09-27 Intel Corporation Semiconductor interconnect structures
US9754886B2 (en) 2012-12-04 2017-09-05 Intel Corporation Semiconductor interconnect structures

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KR19990029770A (ko) 1999-04-26
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JPH11191676A (ja) 1999-07-13
CN1149653C (zh) 2004-05-12
US6300236B1 (en) 2001-10-09
KR100279322B1 (ko) 2001-02-01
TW404034B (en) 2000-09-01
JP3330546B2 (ja) 2002-09-30

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