CN1241032A - 高集成度芯片上芯片封装 - Google Patents
高集成度芯片上芯片封装 Download PDFInfo
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- CN1241032A CN1241032A CN99107091A CN99107091A CN1241032A CN 1241032 A CN1241032 A CN 1241032A CN 99107091 A CN99107091 A CN 99107091A CN 99107091 A CN99107091 A CN 99107091A CN 1241032 A CN1241032 A CN 1241032A
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Abstract
借助于具有至少二个功能完全的芯片且电连接在一起的芯片上芯片组件以及用来将功能完全的芯片电连接到外部电路的芯片上芯片元件连接/互连,实现了本发明的优点。
Description
本申请涉及到二个共同未决的申请:Bertin等人的题为“半导体封装件中的微弯曲工艺”的美国申请No.09/105382和Ference等人的题为“改变特性的芯片上芯片互连”的美国申请No.09/105477。相关的申请被转让于记载的受让人,因而同时提出申请,此处并列为参考。
本发明一般涉及到半导体器件,更具体地说是涉及到半导体器件中的芯片上芯片封装。
在电子开发和封装中,最近50年已发生了巨大的进步。集成电路密度已经并继续高速提高。但80年代之前,制作在芯片中的电路外部的互连电路密度的相应提高跟不上集成电路密度的提高。出现了许多新的封装工艺。一个特定的工艺称为“芯片上芯片组件”工艺。本发明涉及到芯片上芯片组件的具体技术领域。
许多情况下,比之设计新的衬底集成电路,可以更快速而便宜地制造芯片上芯片组件。芯片上芯片组件工艺由于密度的提高而显现出优点。由于密度的提高,在信号传播速度和与其它装置不协调的器件总重量方面得到了同样的改进。目前的芯片上芯片组件结构通常由直接粘合到一系列集成电路元件的印刷电路板衬底组成。
还有许多不同的技术领域,与如何将粘合有芯片上芯片组件的衬底从外部电连接到衬底上的电路有关。这些技术领域包括引线键合、载带自动键合(TAB)、倒装TAB和倒装芯片。在下列美国专利中可找到一些例子:1994年6月授予Fogal等人的美国专利No.5323060“具有叠层芯片分布的多芯片组件”、1997年2月授予Bone等人的美国专利No.5600541“具有由介质载带制作的分立芯片载体的垂直IC芯片叠层”、1996年2月授予Korneld等人的美国专利No.5495394“多芯片组件中的三维管芯封装”、以及1995年3月授予Rostoker等人的美国专利No.5399898“采用倒装芯片管芯的多芯片半导体分布”。
不幸的是,这些技术很昂贵,而且在大多数情况下无法返工(亦即清除和代换)封装件的组元,从而降低了成品率并增加了成本。芯片尺寸的个性化设计也受到严重限制。目前,芯片能够在晶片级或封装级进行个性化设计。由于在封装之前,在晶片后制造工艺中不能够个性化设计芯片,而无法得到产品应用的明显灵活性和制造成本的优点。
因此,本发明的优点是提供消除上述和其它限制的芯片上芯片元件、互连、及其制造方法。
借助于具有至少二个功能完全独立的芯片且电连接在一起的芯片上芯片组件以及用来将芯片电连接到外部电路的芯片上芯片元件连接/互连,实现了本发明的优点。
从如附图所示的本发明最佳实施例的更确切的描述中,本发明的上述和其它的优点和特定将更为明显。
以下结合附图来描述本发明的最佳示范实施例,在这些附图中,相似的参考号表示相似的元件。
图1是根据本发明最佳实施例的具有第一示范芯片上芯片元件连接的芯片上芯片元件的剖面图;
图2、3和4是根据本发明最佳实施例的具有第二、第三和第四示范芯片上芯片元件连接的芯片上芯片元件的剖面图;
图5是采用图4的示范芯片上芯片元件连接的芯片上芯片封装件的剖面图;
图6是具有第五示范芯片上芯片元件连接的图1的芯片上芯片元件的剖面图;
图7是采用图6的示范芯片上芯片元件连接的芯片上芯片封装件的剖面图;
图8、9、10、11、12和13剖面图示出了根据本发明第二实施例的芯片上芯片元件的制造顺序;
图14是根据本发明第三实施例的芯片上芯片元件的剖面图;
图15是采用图14的芯片上芯片元件的芯片上芯片封装件的剖面图;
图16是根据本发明第四实施例的芯片上芯片元件的剖面图;
图17是根据本发明第五实施例的芯片上芯片元件的剖面图;
图18是采用图17的芯片上芯片元件的芯片上芯片封装件的剖面图。
参照图1,示出了根据本发明最佳实施例的第一示范芯片上芯片元件10。芯片上芯片元件10包含第一芯片30、第二芯片40和芯片上芯片元件连接20。第一芯片30的有源区35通过诸如C4(控制熔塌芯片连接)焊料球连接50之类的芯片间连接或光子互连,被电连接到第二芯片40的有源区45。焊料球连接50提供了芯片间联系的高性能电通路。这一互连与芯片电学布线的固有高性能一起,大大地降低了第一芯片30和第二芯片40二者的芯片外驱动器(未示出)的尺寸和功率。虽然此例和以后的例子具体示出了焊料球和焊料柱,但应该理解,也可以采用诸如聚合物金属复合物互连、电镀铜柱、微锁连接等等之类的不同组分构成的其它互连。
在此特定例子中,芯片上芯片元件连接20是连接于第一芯片30的焊料柱22。焊料柱22使得能够将芯片上芯片元件10一般通过衬底连接到外部电路。
图2示出了第二示范芯片上芯片元件,其中芯片上芯片元件连接20包含焊料球。在图1和2中,在IBM Dkt,No.BU9-98-011的相关应用中,可找到制造焊料柱和焊料球的示范性方法。也可以通过下列步骤来制造焊料柱和焊料球:
1)制造具有可焊金属焊点的第一芯片。可以用作焊料柱焊点的外围区焊点的直径可以是例如125微米,间距为250微米。中心区焊点的直径可以是50微米,间距为100微米。
2)制造具有C4焊料球阵列的第二芯片。C4的组分可以是Pb∶Sn=97∶3,且C4应该与第一芯片中心区焊点的间距一致。
3)将第一芯片固定到第二芯片。通过标准的芯片拾放技术(CPP),或通过诸如不用清除的助熔剂、PADS、松香助熔剂与炉回流结合的工艺,可以做到这一点。
4)将焊料柱或焊料球固定到第二芯片。通过焊料注入铸模,可以做到这一点。
5)将芯片上芯片元件连接到衬底。借助于通过标准的放置与连结工艺将易熔焊料连结在衬底TSM焊点上,可以做到这一点。
图3和4示出了芯片上芯片元件的第三和第四例子,其中的芯片上芯片元件连结20包含焊料球26和布线25(图3)或丝焊28(图4)。在图3中,在衬底57中制作空腔55,使第二芯片40的顶部与衬底57的顶部的高度相同。焊料球26则可以与连接的焊料球50尺寸相同,从而将芯片上芯片元件连接到衬底57。
图5示出了采用图4的芯片上芯片元件10A的芯片上芯片封装件。丝焊28连接于衬底72的顶侧。衬底72的底侧包含用来将芯片上芯片封装件连接于不同封装级的焊料球76。粘合剂71将芯片上芯片元件10A机械连接于衬底72。树脂挡条66和包封剂64保护着芯片30和40,并为丝焊和芯片结构60提供强度。金属盖62提供了紧凑、耐用而热增强的芯片上芯片封装件。
如图6和7可见,芯片上芯片元件10B的芯片上芯片元件连结20包含焊料球插件32。焊料球插件32提供了到衬底的电互连以及第二芯片40的尺寸所需的高度。焊料球插件32由连接于一个芯片40的有源区的第一组焊料球、连接于外部电路的第二组焊料球、以及第一组和第二组焊料球之间的导电通道组成。此通道被不导电的材料包围。图7示出了采用图6的芯片上芯片元件10B的芯片上芯片封装件。焊料球插件被连接于衬底72的顶侧。衬底72的底侧包含用来将芯片上芯片封装件连接于不同级封装件的焊料球76。散热器74通过粘合剂78被连接到第一芯片30。散热器使芯片上芯片元件10B得以散热。
图1-7和后面例子的芯片上芯片元件的一些优点包括:可以用不同的半导体工艺来制造芯片30和40,并将它们连接起来而不受这些工艺用于单一芯片时所固有的限制。例如,芯片30可以是逻辑芯片,而芯片40可以是DRAM芯片,在芯片上芯片元件级上产生逻辑/DRAM组合。第二,比之在每个芯片上提供所有功能和电路的单个芯片来说,芯片30和40单独地说是较小而较不复杂的。第三,大量存储器可以位于处理器的紧邻。第四,由于芯片上芯片元件的极为平坦的金属特性,而具有较大的互连密度。最后,本发明的芯片上芯片元件提供了比提供同样功能的简单高集成芯片更低的成本、更低的功率和更高的性能。
图8-13剖面图示出了根据本发明第二实施例的芯片上芯片元件的制造顺序。在图8中,示出了具有有源电路和互连层145的芯片晶片140。晶片140可以是例如硅晶片、GaAs晶片、SiGe晶片等。有源电路和互连层145包含外部互连所需的结构和图形。在图9中,二类元件被固定到晶片140:集成电路(IC)芯片130和焊料球插件(也称为隔件)32。IC芯片130被电连接于晶片140中的有源电路,并提供较高水平的集成电路功能。可以使用诸如带包封的焊料球和丝焊之类的电连接。焊料球插件32提供了晶片140上有源电路层145和IC芯片130有源电路层侧形成的平面之间的电通路。虽然在本例子中具体示出了焊料球插件32,但也可以使用诸如具有通道孔的硅晶片、多层陶瓷和有机PCB间隔之类的其它间隔。同时,虽然在本例子中用焊料球来将IC芯片130和焊料球插件32连接到晶片140,但也可以采用诸如导电环氧树脂、PMC胶、各向异性导电粘合剂和瞬变液相键合之类的其它互连方法。可以用焊料球包封体(未示出)来包围焊料球。
如图10所见,在整个表面上淀积共形涂层34(例如对二甲苯)。然后如图11所示,用机械和/或化学方法整平此涂层。整平的一个例子可以是用标准的晶片抛光方法对表面进行机械抛光。这一整平使结构中焊料球插件32中的互连通道孔出现在表面上。这些通道孔构成到外部电路的连接。图12示出了在焊料球插件32上制造用于对外部电路互连的焊料球36。在预定点38处切割芯片上芯片元件,形成能够用焊料球36连接到外部电路的“超芯片”。图13示出了连接于载体/衬底72的超芯片。制造图13所示的超芯片有一些优点。这些优点包括:用多层不同半导体工艺的非常高的集成度;元件速度、带宽要求和芯片外速度方面的优越性能;组元芯片物理上很小且不需要复杂的电路或制造工艺,导致成品率高和成本低;以及借助于以各种形式连接几个组元元件,能够达到专用化。
图14和15是根据本发明第三实施例的芯片上芯片元件80的剖面图。芯片上芯片元件80包含由二个芯片构成一组的二个组,每个组有电连接于第二芯片的第一芯片30和40以及30A和40A(例如图1中的芯片上芯片元件10)。在此例子中,芯片30和30A的背侧彼此相对。二组芯片通过芯片上芯片元件连接20A(此例子中是互连衬底88)电连接到一起。互连衬底88还通过诸如丝焊84、C4连接86和金属焊点连接82之类的电连接,将芯片上芯片元件80连接到外部器件。虽然为了说明的目的,在图14和15的芯片上芯片元件80上示出了不同类型的连接,但通常对于一种应用只使用一种类型的连接(亦即,连接82、84和86可以都是例如C4连接)。图15示出了采用图14的芯片上芯片元件80的芯片上芯片封装件。二个散热器92通过粘合剂94被连接于芯片30和30A。散热器使芯片上芯片元件80得以散热。在衬底57中制作空腔55,使第二芯片40的顶部与衬底57的顶部的高度相同。焊料球26则可以与连接的焊料球50尺寸相同,从而将芯片上芯片元件连接到衬底57。这样,如根据本发明这一实施例所述,可以将几个各具有分立和特定功能且可能用不同的半导体工艺制造的芯片结合在一起。
图16是根据本发明第四实施例的包含芯片上芯片元件80A的可插接的芯片上芯片封装件的剖面图。芯片上芯片元件80A包含芯片30、30A、40、40A、互连衬底88A、和耦合衬底88B。在此例子中,芯片上芯片元件80A被包封剂96包封,从而提供一个坚实的元件。互连衬底88A使得能够通过可插接界面电连接到外部电路。
图17是根据本发明第五实施例的芯片上芯片元件80B的剖面图。除了芯片上芯片元件连接20A包含延伸于芯片上芯片元件80B上下表面的可堆叠的互连衬底88C之外,芯片上芯片元件80B与芯片上芯片元件80(图14)是相似的。芯片上芯片元件连接20A的上表面包含可熔性金属焊点82,而芯片上芯片元件连接20A的下表面包含焊料球86。芯片上芯片元件结构80B是三维可堆叠组件的示范单元结构。另一种示范单元结构可以包含取消芯片40和40A,并使芯片上芯片元件连接20A延伸跨过芯片30和30A。图18示出了含有二个图17的芯片上芯片元件单元结构80B的堆叠的组件。
堆叠的组件和单元结构的一些优点是:首先,可以容易地适应不同尺寸和厚度的芯片。第二,结构是可返工的。第三,各种尺寸的结构都是可能的而没有明显的先决条件。第四,有可能安排单元结构之间的热问题。
于是,根据本发明的芯片上芯片元件和连接,使得能够得到高集成度工艺和可靠而紧凑的半导体封装件。芯片上芯片封装件还提供了增强的电学性能、机械性能与热性能。
虽然参照最佳实施例已经具体地描述了本发明,但本技术领域熟练人员能够理解,可以作出上述的和其它的形式和细节的改变而不超越本发明的构思与范围。
Claims (20)
1.一种装置,它包含:
至少具有有源区电连接在一起的二个独立芯片的芯片上芯片组件,其中所述二个芯片的所述有源区彼此面对;以及
用来将所述芯片电连接到外部电路的芯片上芯片元件连接。
2.权利要求1的装置,其中所述芯片上芯片元件连接是焊料球插件,它包含:
连接于一个所述芯片的所述有源区的第一组焊料球;
用来连接到所述外部电路的第二组焊料球;以及
连接在所述第一组和所述第二组焊料球之间的导电通道,其中所述通道被不导电的材料包围。
3.权利要求1的装置,其中该至少二个芯片的工艺不同。
4.权利要求1的装置,其中所述芯片上芯片元件连接是互连衬底,它包含:
连接于所述芯片的所述有源区的第一组连接元件;
用来连接到所述外部电路的第二组连接元件;以及
具有导电线条的衬底,所述导电线条将所述第一组连接元件连接到所述第二组连接元件。
5.权利要求4的装置,其中所述外部电路是可插接的连接。
6.权利要求4的装置,其中所述第二组连接元件包含:
与所述至少二个芯片中的一个的第一背面齐平的第二组焊料球;以及
与所述至少二个芯片中的另一个的第二背面齐平的第二组金属焊点,
其中所述芯片上芯片组件的所述第二组焊料球,通过所述第二芯片上芯片组件的金属焊点,将所述芯片上芯片组件连接到第二芯片上芯片组件。
7.权利要求2的装置,其中所述焊料球插件与所述芯片上芯片组件的所述至少二个芯片中的一个的高度相同。
8.一种制造芯片上芯片元件的方法,它包含下列步骤:
a)制造具有至少二个有源区电连接在一起的独立芯片的芯片上芯片组件,其中所述二个芯片的所述有源区彼此面对;以及
b)制造用来将所述芯片上芯片组件连接到外部电路的芯片上芯片元件连接。
9.权利要求8的方法,其中所述步骤a)和b)还包含下列步骤:
1)提供具有晶片有源区的晶片;
2)将具有IC有源区的集成电路(IC)芯片固定到所述晶片,其中所述IC有源区被连接到所述晶片有源区;
3)将芯片上芯片元件连接固定到所述晶片有源区,其中所述芯片上芯片元件连接具有与所述IC芯片相同的高度;
4)在所述晶片、所述固定的IC芯片和所述固定的芯片上芯片元件连接上,淀积共形涂层;
5)将所述涂层整平到所述IC芯片的所述高度,以形成芯片上芯片晶片;以及
6)在预定点处切割所述芯片上芯片晶片,以形成具有所述芯片上芯片组件和所述芯片上芯片元件连接的芯片上芯片元件。
10.权利要求8的方法,其中步骤b)还包含下列步骤:
1)提供第一组焊料球;
2)将所述第一组焊料球连接到一个所述芯片的所述有源区;
3)提供用来连接到所述外部电路的第二组焊料球;以及
4)将所述第一组和所述第二组焊料球与被不导电的材料包围的导电通道连接,以形成焊料球插件。
11.权利要求8的方法,其中该至少二个芯片的工艺不同。
12.权利要求8的方法,其中步骤b)还包含下列步骤:
1)提供第一组连接元件;
2)将所述第一组连接元件连接到一个所述芯片的所述有源区;
3)提供用来连接到所述外部电路的第二组连接元件;以及
4)将所述第一组和所述第二组焊料球与具有导电线条的衬底连接,以形成互连衬底。
13.权利要求12的方法,其中所述外部电路是可插接的连接。
14.权利要求12的方法,其中步骤3)还包含下列步骤:
3a)对具有所述至少二个芯片中的一个的第一背面和具有所述至少二个芯片中的另一个的第二背面的所述互连衬底进行整平;
3b)提供与所述第一背面齐平的第二组焊料球;
3c)提供与所述第二背面齐平的第二组金属焊点;以及
3d)通过所述第二组连接元件,将所述芯片上芯片组件连接到第二芯片上芯片组件。
15.一种芯片上芯片封装件,它包含:
外部元件;
至少具有有源区电连接在一起的二个独立芯片的芯片上芯片组件,其中所述二个芯片的所述有源区彼此面对;以及
用来将所述芯片电连接到所述外部元件的芯片上芯片元件连接。
16.权利要求15的芯片上芯片封装件,其中所述芯片上芯片元件连接是焊料球插件,它包含:
连接于一个所述芯片的所述有源区的第一组焊料球;
用来连接到所述外部元件的第二组焊料球;以及
连接在所述第一组和所述第二组焊料球之间的导电通道,其中所述通道被不导电的材料包围。
17.权利要求15的芯片上芯片封装件,其中该至少二个芯片的工艺不同。
18.权利要求15的芯片上芯片封装件,其中所述芯片上芯片元件连接是互连衬底,它包含:
连接于所述芯片的所述有源区的第一组连接元件;
用来连接到所述外部元件的第二组连接元件;以及
具有导电线条的衬底,所述导电线条将所述第一组连接元件连接到所述第二组连接元件。
19.权利要求18的芯片上芯片封装件,其中所述外部元件具有可插接的连接。
20.权利要求18的芯片上芯片封装件,其中所述第二组连接元件包含:
与所述至少二个芯片中的一个的第一背面齐平的第二组焊料球;以及
与所述至少二个芯片中的另一个的第二背面齐平的第二组金属焊点,
其中所述芯片上芯片组件的所述第二组焊料球,通过所述第二芯片上芯片组件的金属焊点,将所述芯片上芯片组件连接到第二芯片上芯片组件。
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US105419 | 1998-06-26 | ||
US09/105,419 US5977640A (en) | 1998-06-26 | 1998-06-26 | Highly integrated chip-on-chip packaging |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100336221C (zh) * | 2002-11-04 | 2007-09-05 | 矽品精密工业股份有限公司 | 可堆栈半导体封装件的模块化装置及其制法 |
CN102148220A (zh) * | 2010-02-05 | 2011-08-10 | 台湾积体电路制造股份有限公司 | 半导体装置 |
CN101519183B (zh) * | 2008-01-31 | 2011-09-21 | 台湾积体电路制造股份有限公司 | 具有集成电路管芯的微机电系统封装 |
CN101803020B (zh) * | 2007-09-18 | 2012-05-23 | 奥林巴斯株式会社 | 叠层安装结构体和叠层安装结构体的制造方法 |
CN103000588A (zh) * | 2011-09-09 | 2013-03-27 | 东琳精密股份有限公司 | 芯片封装结构及其制造方法 |
CN104584212A (zh) * | 2012-09-27 | 2015-04-29 | 英特尔公司 | 包括封装衬底中的管芯的堆叠管芯封装 |
CN105489589A (zh) * | 2016-01-26 | 2016-04-13 | 兰微悦美(天津)科技有限公司 | 可堆叠的集成电路及其封装方法 |
CN106057788A (zh) * | 2015-04-13 | 2016-10-26 | 爱思开海力士有限公司 | 具有中介层的半导体封装及其制造方法 |
CN108630670A (zh) * | 2018-03-30 | 2018-10-09 | 维沃移动通信有限公司 | 一种封装模块及堆叠封装结构 |
Families Citing this family (345)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6687842B1 (en) | 1997-04-02 | 2004-02-03 | Tessera, Inc. | Off-chip signal routing between multiply-connected on-chip electronic elements via external multiconductor transmission line on a dielectric element |
AU6878398A (en) * | 1997-04-02 | 1998-10-22 | Tessera, Inc. | Chip with internal signal routing in external element |
JPH1177512A (ja) | 1997-09-09 | 1999-03-23 | Oki Electric Ind Co Ltd | 表面実装パッケージのリード端子自動研磨方法及びその自動研磨装置 |
US6091138A (en) * | 1998-02-27 | 2000-07-18 | Advanced Micro Devices, Inc. | Multi-chip packaging using bump technology |
US6150724A (en) * | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
US6059173A (en) * | 1998-03-05 | 2000-05-09 | International Business Machines Corporation | Micro grid array solder interconnection structure for second level packaging joining a module and printed circuit board |
US6137164A (en) * | 1998-03-16 | 2000-10-24 | Texas Instruments Incorporated | Thin stacked integrated circuit device |
US6642136B1 (en) | 2001-09-17 | 2003-11-04 | Megic Corporation | Method of making a low fabrication cost, high performance, high reliability chip scale package |
KR100266693B1 (ko) | 1998-05-30 | 2000-09-15 | 김영환 | 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법 |
US6107119A (en) * | 1998-07-06 | 2000-08-22 | Micron Technology, Inc. | Method for fabricating semiconductor components |
US6337509B2 (en) * | 1998-07-16 | 2002-01-08 | International Business Machines Corporation | Fixture for attaching a conformal chip carrier to a flip chip |
US6586835B1 (en) * | 1998-08-31 | 2003-07-01 | Micron Technology, Inc. | Compact system module with built-in thermoelectric cooling |
US6424034B1 (en) | 1998-08-31 | 2002-07-23 | Micron Technology, Inc. | High performance packaging for microprocessors and DRAM chips which minimizes timing skews |
SG75873A1 (en) * | 1998-09-01 | 2000-10-24 | Texas Instr Singapore Pte Ltd | Stacked flip-chip integrated circuit assemblage |
US6618267B1 (en) * | 1998-09-22 | 2003-09-09 | International Business Machines Corporation | Multi-level electronic package and method for making same |
US6295220B1 (en) * | 1998-11-03 | 2001-09-25 | Zomaya Group, Inc. | Memory bar and related circuits and methods |
US6160718A (en) * | 1998-12-08 | 2000-12-12 | Viking Components | Multi-chip package with stacked chips and interconnect bumps |
KR100470386B1 (ko) * | 1998-12-26 | 2005-05-19 | 주식회사 하이닉스반도체 | 멀티-칩패키지 |
US6222246B1 (en) * | 1999-01-08 | 2001-04-24 | Intel Corporation | Flip-chip having an on-chip decoupling capacitor |
US6130823A (en) * | 1999-02-01 | 2000-10-10 | Raytheon E-Systems, Inc. | Stackable ball grid array module and method |
JP2000223657A (ja) * | 1999-02-03 | 2000-08-11 | Rohm Co Ltd | 半導体装置およびそれに用いる半導体チップ |
JP2000227457A (ja) * | 1999-02-05 | 2000-08-15 | Rohm Co Ltd | 半導体装置 |
US6204562B1 (en) * | 1999-02-11 | 2001-03-20 | United Microelectronics Corp. | Wafer-level chip scale package |
JP3828673B2 (ja) * | 1999-02-23 | 2006-10-04 | ローム株式会社 | 半導体装置 |
JP2000252414A (ja) * | 1999-03-04 | 2000-09-14 | Mitsubishi Electric Corp | 半導体装置 |
JP3754221B2 (ja) * | 1999-03-05 | 2006-03-08 | ローム株式会社 | マルチチップ型半導体装置 |
US6215193B1 (en) * | 1999-04-21 | 2001-04-10 | Advanced Semiconductor Engineering, Inc. | Multichip modules and manufacturing method therefor |
JP3575001B2 (ja) * | 1999-05-07 | 2004-10-06 | アムコー テクノロジー コリア インコーポレーティド | 半導体パッケージ及びその製造方法 |
JP3339838B2 (ja) * | 1999-06-07 | 2002-10-28 | ローム株式会社 | 半導体装置およびその製造方法 |
US6077766A (en) * | 1999-06-25 | 2000-06-20 | International Business Machines Corporation | Variable thickness pads on a substrate surface |
JP2001024150A (ja) * | 1999-07-06 | 2001-01-26 | Sony Corp | 半導体装置 |
JP2001044362A (ja) * | 1999-07-27 | 2001-02-16 | Mitsubishi Electric Corp | 半導体装置の実装構造および実装方法 |
JP2001044358A (ja) * | 1999-07-28 | 2001-02-16 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
TW417839U (en) * | 1999-07-30 | 2001-01-01 | Shen Ming Tung | Stacked memory module structure and multi-layered stacked memory module structure using the same |
WO2001015228A1 (fr) * | 1999-08-19 | 2001-03-01 | Seiko Epson Corporation | Panneau de cablage, procede de fabrication d'un panneau de cablage, dispositif semiconducteur, procede de fabrication d'un dispositif semiconducteur, carte a circuit imprime et appareil electronique |
EP1154474A4 (en) * | 1999-08-23 | 2008-07-16 | Rohm Co Ltd | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING THEREOF |
JP2001077301A (ja) * | 1999-08-24 | 2001-03-23 | Amkor Technology Korea Inc | 半導体パッケージ及びその製造方法 |
US6392428B1 (en) * | 1999-11-16 | 2002-05-21 | Eaglestone Partners I, Llc | Wafer level interposer |
JP2001156251A (ja) * | 1999-11-25 | 2001-06-08 | Mitsubishi Electric Corp | 半導体装置 |
US6320249B1 (en) * | 1999-11-30 | 2001-11-20 | Glotech, Inc. | Multiple line grids incorporating therein circuit elements |
SE517921C2 (sv) * | 1999-12-16 | 2002-08-06 | Strand Interconnect Ab | Modul innefattande ett eller flera chip |
JP2001196529A (ja) * | 2000-01-17 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置及びその配線方法 |
US6369448B1 (en) * | 2000-01-21 | 2002-04-09 | Lsi Logic Corporation | Vertically integrated flip chip semiconductor package |
JP2001223323A (ja) * | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置 |
US6586836B1 (en) * | 2000-03-01 | 2003-07-01 | Intel Corporation | Process for forming microelectronic packages and intermediate structures formed therewith |
JP3772066B2 (ja) * | 2000-03-09 | 2006-05-10 | 沖電気工業株式会社 | 半導体装置 |
US6344401B1 (en) * | 2000-03-09 | 2002-02-05 | Atmel Corporation | Method of forming a stacked-die integrated circuit chip package on a water level |
US6531335B1 (en) | 2000-04-28 | 2003-03-11 | Micron Technology, Inc. | Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods |
US7247932B1 (en) | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
US6452278B1 (en) | 2000-06-30 | 2002-09-17 | Amkor Technology, Inc. | Low profile package for plural semiconductor dies |
US6525413B1 (en) * | 2000-07-12 | 2003-02-25 | Micron Technology, Inc. | Die to die connection method and assemblies and packages including dice so connected |
KR100549299B1 (ko) * | 2000-07-18 | 2006-02-02 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조 방법 |
US6812048B1 (en) | 2000-07-31 | 2004-11-02 | Eaglestone Partners I, Llc | Method for manufacturing a wafer-interposer assembly |
US6537831B1 (en) * | 2000-07-31 | 2003-03-25 | Eaglestone Partners I, Llc | Method for selecting components for a matched set using a multi wafer interposer |
KR100385087B1 (ko) * | 2000-08-01 | 2003-05-22 | 밍-퉁 센 | 멀티칩 반도체 모듈 및 그 제조 방법 |
US6495910B1 (en) * | 2000-08-25 | 2002-12-17 | Siliconware Precision Industries Co., Ltd. | Package structure for accommodating thicker semiconductor unit |
TW569403B (en) * | 2001-04-12 | 2004-01-01 | Siliconware Precision Industries Co Ltd | Multi-chip module and its manufacturing method |
JP2002093831A (ja) | 2000-09-14 | 2002-03-29 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
SG97938A1 (en) * | 2000-09-21 | 2003-08-20 | Micron Technology Inc | Method to prevent die attach adhesive contamination in stacked chips |
US6530515B1 (en) | 2000-09-26 | 2003-03-11 | Amkor Technology, Inc. | Micromachine stacked flip chip package fabrication method |
US6522015B1 (en) * | 2000-09-26 | 2003-02-18 | Amkor Technology, Inc. | Micromachine stacked wirebonded package |
US6638789B1 (en) | 2000-09-26 | 2003-10-28 | Amkor Technology, Inc. | Micromachine stacked wirebonded package fabrication method |
US6815712B1 (en) | 2000-10-02 | 2004-11-09 | Eaglestone Partners I, Llc | Method for selecting components for a matched set from a wafer-interposer assembly |
KR100508261B1 (ko) * | 2000-10-04 | 2005-08-18 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조방법 |
KR20020029990A (ko) * | 2000-10-16 | 2002-04-22 | 윤종용 | 실장리드가 구비된 기판을 포함하는 반도체 패키지 및 그제조방법 |
US6686657B1 (en) | 2000-11-07 | 2004-02-03 | Eaglestone Partners I, Llc | Interposer for improved handling of semiconductor wafers and method of use of same |
JP4505983B2 (ja) * | 2000-12-01 | 2010-07-21 | 日本電気株式会社 | 半導体装置 |
US6858941B2 (en) * | 2000-12-07 | 2005-02-22 | International Business Machines Corporation | Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array |
US6507115B2 (en) * | 2000-12-14 | 2003-01-14 | International Business Machines Corporation | Multi-chip integrated circuit module |
US6529022B2 (en) | 2000-12-15 | 2003-03-04 | Eaglestone Pareners I, Llc | Wafer testing interposer for a conventional package |
US6524885B2 (en) | 2000-12-15 | 2003-02-25 | Eaglestone Partners I, Llc | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
US20020078401A1 (en) * | 2000-12-15 | 2002-06-20 | Fry Michael Andrew | Test coverage analysis system |
US6564454B1 (en) | 2000-12-28 | 2003-05-20 | Amkor Technology, Inc. | Method of making and stacking a semiconductor package |
JP2002204053A (ja) * | 2001-01-04 | 2002-07-19 | Mitsubishi Electric Corp | 回路実装方法、回路実装基板及び半導体装置 |
JP2002222914A (ja) * | 2001-01-26 | 2002-08-09 | Sony Corp | 半導体装置及びその製造方法 |
US6815324B2 (en) | 2001-02-15 | 2004-11-09 | Megic Corporation | Reliable metal bumps on top of I/O pads after removal of test probe marks |
US6673653B2 (en) * | 2001-02-23 | 2004-01-06 | Eaglestone Partners I, Llc | Wafer-interposer using a ceramic substrate |
TWI313507B (en) | 2002-10-25 | 2009-08-11 | Megica Corporatio | Method for assembling chips |
US7034386B2 (en) * | 2001-03-26 | 2006-04-25 | Nec Corporation | Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same |
SG108245A1 (en) * | 2001-03-30 | 2005-01-28 | Micron Technology Inc | Ball grid array interposer, packages and methods |
KR100406448B1 (ko) * | 2001-04-02 | 2003-11-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조 방법 |
US6762487B2 (en) * | 2001-04-19 | 2004-07-13 | Simpletech, Inc. | Stack arrangements of chips and interconnecting members |
DE10120408B4 (de) * | 2001-04-25 | 2006-02-02 | Infineon Technologies Ag | Elektronisches Bauteil mit einem Halbleiterchip, elektronische Baugruppe aus gestapelten Halbleiterchips und Verfahren zu deren Herstellung |
US7115986B2 (en) * | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
JP2002329836A (ja) * | 2001-05-02 | 2002-11-15 | Mitsubishi Electric Corp | 半導体装置および配線フィルム |
DE10124774B4 (de) * | 2001-05-21 | 2016-05-25 | Infineon Technologies Ag | Halbleiterbauelement mit zumindest einem Halbleiterchip auf einem als Substrat dienenden Basischip und Verfahren zu dessen Herstellung |
JP4413452B2 (ja) * | 2001-05-30 | 2010-02-10 | パナソニック株式会社 | 半導体装置およびその製造方法 |
US6547124B2 (en) | 2001-06-14 | 2003-04-15 | Bae Systems Information And Electronic Systems Integration Inc. | Method for forming a micro column grid array (CGA) |
US6683375B2 (en) * | 2001-06-15 | 2004-01-27 | Fairchild Semiconductor Corporation | Semiconductor die including conductive columns |
DE10131011B4 (de) * | 2001-06-27 | 2016-02-18 | Infineon Technologies Ag | Halbleiterchip und Anordnung eines Halbleiterbauelementes auf einem Substrat |
KR100425766B1 (ko) * | 2001-06-28 | 2004-04-03 | 동부전자 주식회사 | 반도체 패키지 및 그 제조 방법 |
JP2003060153A (ja) * | 2001-07-27 | 2003-02-28 | Nokia Corp | 半導体パッケージ |
US6790710B2 (en) | 2002-01-31 | 2004-09-14 | Asat Limited | Method of manufacturing an integrated circuit package |
SG122743A1 (en) | 2001-08-21 | 2006-06-29 | Micron Technology Inc | Microelectronic devices and methods of manufacture |
US6613606B1 (en) * | 2001-09-17 | 2003-09-02 | Magic Corporation | Structure of high performance combo chip and processing method |
US7099293B2 (en) | 2002-05-01 | 2006-08-29 | Stmicroelectronics, Inc. | Buffer-less de-skewing for symbol combination in a CDMA demodulator |
US20030054583A1 (en) * | 2001-09-20 | 2003-03-20 | Eastman Kodak Company | Method for producing an image sensor assembly |
US6979894B1 (en) * | 2001-09-27 | 2005-12-27 | Marvell International Ltd. | Integrated chip package having intermediate substrate |
US6882546B2 (en) | 2001-10-03 | 2005-04-19 | Formfactor, Inc. | Multiple die interconnect system |
US6555917B1 (en) | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
US20030089998A1 (en) * | 2001-11-09 | 2003-05-15 | Chan Vincent K. | Direct interconnect multi-chip module, method for making the same and electronic package comprising same |
US6541870B1 (en) * | 2001-11-14 | 2003-04-01 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with stacked chips |
SG104293A1 (en) * | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
WO2003063242A1 (en) * | 2002-01-16 | 2003-07-31 | Alfred E. Mann Foundation For Scientific Research | Space-saving packaging of electronic circuits |
US6635970B2 (en) * | 2002-02-06 | 2003-10-21 | International Business Machines Corporation | Power distribution design method for stacked flip-chip packages |
US6768650B2 (en) * | 2002-02-07 | 2004-07-27 | International Business Machines Corporation | Method and structure for reduction of impedance using decoupling capacitor |
US6762076B2 (en) * | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
AU2002257013A1 (en) * | 2002-02-28 | 2003-10-20 | Nano Storage Pte Ltd | Micro-electro-mechanical systems packaging |
SG115459A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Flip chip packaging using recessed interposer terminals |
SG111935A1 (en) | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
SG115455A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Methods for assembly and packaging of flip chip configured dice with interposer |
US6975035B2 (en) | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
SG121707A1 (en) | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
SG115456A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
US20030178719A1 (en) * | 2002-03-22 | 2003-09-25 | Combs Edward G. | Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package |
US20030183934A1 (en) * | 2002-03-29 | 2003-10-02 | Barrett Joseph C. | Method and apparatus for stacking multiple die in a flip chip semiconductor package |
US7307293B2 (en) | 2002-04-29 | 2007-12-11 | Silicon Pipe, Inc. | Direct-connect integrated circuit signaling system for bypassing intra-substrate printed circuit signal paths |
US7750446B2 (en) | 2002-04-29 | 2010-07-06 | Interconnect Portfolio Llc | IC package structures having separate circuit interconnection structures and assemblies constructed thereof |
JP2003332360A (ja) * | 2002-05-17 | 2003-11-21 | Denso Corp | 半導体装置 |
US7573136B2 (en) * | 2002-06-27 | 2009-08-11 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor device components |
US6906415B2 (en) * | 2002-06-27 | 2005-06-14 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor devices and methods |
US20040012094A1 (en) * | 2002-07-18 | 2004-01-22 | Harper Timothy V. | Flip-chip integrated circuit package and method of assembly |
US6659512B1 (en) * | 2002-07-18 | 2003-12-09 | Hewlett-Packard Development Company, L.P. | Integrated circuit package employing flip-chip technology and method of assembly |
US7087988B2 (en) | 2002-07-30 | 2006-08-08 | Kabushiki Kaisha Toshiba | Semiconductor packaging apparatus |
US6891272B1 (en) | 2002-07-31 | 2005-05-10 | Silicon Pipe, Inc. | Multi-path via interconnection structures and methods for manufacturing the same |
US20040036170A1 (en) | 2002-08-20 | 2004-02-26 | Lee Teck Kheng | Double bumping of flexible substrate for first and second level interconnects |
US7205647B2 (en) * | 2002-09-17 | 2007-04-17 | Chippac, Inc. | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
US7064426B2 (en) * | 2002-09-17 | 2006-06-20 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages |
US20040061213A1 (en) * | 2002-09-17 | 2004-04-01 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
US7053476B2 (en) * | 2002-09-17 | 2006-05-30 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
US6972481B2 (en) * | 2002-09-17 | 2005-12-06 | Chippac, Inc. | Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages |
KR20050074961A (ko) | 2002-10-08 | 2005-07-19 | 치팩, 인코포레이티드 | 역전된 제 2 패키지를 구비한 반도체 적층형 멀티-패키지모듈 |
US7034387B2 (en) * | 2003-04-04 | 2006-04-25 | Chippac, Inc. | Semiconductor multipackage module including processor and memory package assemblies |
AU2003301632A1 (en) * | 2002-10-22 | 2004-05-13 | Unitive International Limited | Stacked electronic structures including offset substrates |
TW200411871A (en) * | 2002-12-30 | 2004-07-01 | Advanced Semiconductor Eng | Thermal-enhance package and manufacturing method thereof |
US7014472B2 (en) * | 2003-01-13 | 2006-03-21 | Siliconpipe, Inc. | System for making high-speed connections to board-mounted modules |
JP3981026B2 (ja) * | 2003-01-30 | 2007-09-26 | 株式会社東芝 | 多層配線層を有する半導体装置およびその製造方法 |
TWI236117B (en) * | 2003-02-26 | 2005-07-11 | Advanced Semiconductor Eng | Semiconductor package with a heat sink |
US20040201970A1 (en) * | 2003-04-10 | 2004-10-14 | International Business Machines Corporation | Chip interconnection method and apparatus |
TWI313049B (en) * | 2003-04-23 | 2009-08-01 | Advanced Semiconductor Eng | Multi-chips stacked package |
US7095103B1 (en) * | 2003-05-01 | 2006-08-22 | Amkor Technology, Inc. | Leadframe based memory card |
WO2004105134A1 (en) * | 2003-05-20 | 2004-12-02 | Infineon Technologies Ag | An integrated circuit package |
US20040262368A1 (en) * | 2003-06-26 | 2004-12-30 | Haw Tan Tzyy | Ball grid array solder joint reliability |
US7185821B1 (en) * | 2003-07-07 | 2007-03-06 | Cisco Technology, Inc. | Method and apparatus for delivering high-current power and ground voltages using top side of chip package substrate |
US7144640B2 (en) * | 2003-08-01 | 2006-12-05 | Agency For Science, Technology And Research | Tilted media for hard disk drives and magnetic data storage devices |
US7180165B2 (en) * | 2003-09-05 | 2007-02-20 | Sanmina, Sci Corporation | Stackable electronic assembly |
US7247517B2 (en) * | 2003-09-30 | 2007-07-24 | Intel Corporation | Method and apparatus for a dual substrate package |
US7061121B2 (en) * | 2003-11-12 | 2006-06-13 | Tessera, Inc. | Stacked microelectronic assemblies with central contacts |
KR100535181B1 (ko) * | 2003-11-18 | 2005-12-09 | 삼성전자주식회사 | 디커플링 커패시터를 갖는 반도체 칩 패키지와 그 제조 방법 |
JP4580730B2 (ja) * | 2003-11-28 | 2010-11-17 | ルネサスエレクトロニクス株式会社 | オフセット接合型マルチチップ半導体装置 |
US7394161B2 (en) * | 2003-12-08 | 2008-07-01 | Megica Corporation | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto |
US8970049B2 (en) * | 2003-12-17 | 2015-03-03 | Chippac, Inc. | Multiple chip package module having inverted package stacked over die |
US20070145548A1 (en) * | 2003-12-22 | 2007-06-28 | Amkor Technology, Inc. | Stack-type semiconductor package and manufacturing method thereof |
US7009296B1 (en) | 2004-01-15 | 2006-03-07 | Amkor Technology, Inc. | Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die |
TWI247371B (en) * | 2004-02-06 | 2006-01-11 | Advanced Semiconductor Eng | Semiconductor package and method for manufacturing the same |
JP5208500B2 (ja) | 2004-05-06 | 2013-06-12 | エヌエックスピー ビー ヴィ | 組込方法及びこの方法により製造されたアセンブリ |
US8552551B2 (en) * | 2004-05-24 | 2013-10-08 | Chippac, Inc. | Adhesive/spacer island structure for stacking over wire bonded die |
US20050258527A1 (en) * | 2004-05-24 | 2005-11-24 | Chippac, Inc. | Adhesive/spacer island structure for multiple die package |
US20050269692A1 (en) | 2004-05-24 | 2005-12-08 | Chippac, Inc | Stacked semiconductor package having adhesive/spacer structure and insulation |
US7253511B2 (en) * | 2004-07-13 | 2007-08-07 | Chippac, Inc. | Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package |
JP4489524B2 (ja) * | 2004-07-23 | 2010-06-23 | 株式会社ルネサステクノロジ | 半導体装置の製造方法およびペースト塗布装置 |
US7196411B2 (en) * | 2004-09-17 | 2007-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat dissipation for chip-on-chip IC packages |
US20060108676A1 (en) * | 2004-11-22 | 2006-05-25 | Punzalan Nelson V Jr | Multi-chip package using an interposer |
US8294279B2 (en) | 2005-01-25 | 2012-10-23 | Megica Corporation | Chip package with dam bar restricting flow of underfill |
TWI249831B (en) * | 2005-02-21 | 2006-02-21 | Touch Micro System Tech | Chip type micro connector and method of packaging the sane |
US7262494B2 (en) * | 2005-03-16 | 2007-08-28 | Freescale Semiconductor, Inc. | Three-dimensional package |
WO2006105514A2 (en) * | 2005-03-31 | 2006-10-05 | Stats Chippac Ltd. | Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides |
WO2006118720A2 (en) * | 2005-03-31 | 2006-11-09 | Stats Chippac Ltd. | Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides |
US7364945B2 (en) | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
JP4904601B2 (ja) * | 2005-04-28 | 2012-03-28 | エスティー‐エリクソン、ソシエテ、アノニム | 集積回路チップ上における電源及びグランドラインルーティングのための受動集積基板を有する集積回路組立体 |
US7429786B2 (en) * | 2005-04-29 | 2008-09-30 | Stats Chippac Ltd. | Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides |
US7354800B2 (en) | 2005-04-29 | 2008-04-08 | Stats Chippac Ltd. | Method of fabricating a stacked integrated circuit package system |
US7582960B2 (en) | 2005-05-05 | 2009-09-01 | Stats Chippac Ltd. | Multiple chip package module including die stacked over encapsulated package |
US7675151B1 (en) * | 2005-06-01 | 2010-03-09 | Rockwell Collins, Inc. | Silicon-based packaging for electronic devices |
US7394148B2 (en) * | 2005-06-20 | 2008-07-01 | Stats Chippac Ltd. | Module having stacked chip scale semiconductor packages |
KR100665217B1 (ko) * | 2005-07-05 | 2007-01-09 | 삼성전기주식회사 | 반도체 멀티칩 패키지 |
KR100721353B1 (ko) * | 2005-07-08 | 2007-05-25 | 삼성전자주식회사 | 칩 삽입형 매개기판의 구조와 제조 방법, 이를 이용한 이종칩의 웨이퍼 레벨 적층 구조 및 패키지 구조 |
DE102005039867B4 (de) * | 2005-08-23 | 2016-04-07 | Power Systems Technologies Gmbh | Eingangsschaltung für ein Schaltnetzteil |
CN100544546C (zh) * | 2005-10-27 | 2009-09-23 | 鸿富锦精密工业(深圳)有限公司 | 印刷电路板 |
CN100437958C (zh) * | 2005-11-03 | 2008-11-26 | 台湾应解股份有限公司 | 芯片封装结构及其制造方法 |
DE102005056907B3 (de) * | 2005-11-29 | 2007-08-16 | Infineon Technologies Ag | 3-dimensionales Mehrchip-Modul |
US7279795B2 (en) * | 2005-12-29 | 2007-10-09 | Intel Corporation | Stacked die semiconductor package |
US7768125B2 (en) * | 2006-01-04 | 2010-08-03 | Stats Chippac Ltd. | Multi-chip package system |
US7456088B2 (en) * | 2006-01-04 | 2008-11-25 | Stats Chippac Ltd. | Integrated circuit package system including stacked die |
DE102006001767B4 (de) * | 2006-01-12 | 2009-04-30 | Infineon Technologies Ag | Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben |
US7750482B2 (en) * | 2006-02-09 | 2010-07-06 | Stats Chippac Ltd. | Integrated circuit package system including zero fillet resin |
US8704349B2 (en) * | 2006-02-14 | 2014-04-22 | Stats Chippac Ltd. | Integrated circuit package system with exposed interconnects |
US7385299B2 (en) * | 2006-02-25 | 2008-06-10 | Stats Chippac Ltd. | Stackable integrated circuit package system with multiple interconnect interface |
JP2007324354A (ja) * | 2006-05-31 | 2007-12-13 | Sony Corp | 半導体装置 |
US20080001271A1 (en) * | 2006-06-30 | 2008-01-03 | Sony Ericsson Mobile Communications Ab | Flipped, stacked-chip IC packaging for high bandwidth data transfer buses |
US20080032451A1 (en) * | 2006-08-07 | 2008-02-07 | Sandisk Il Ltd. | Method of providing inverted pyramid multi-die package reducing wire sweep and weakening torques |
US20080042265A1 (en) * | 2006-08-15 | 2008-02-21 | Merilo Leo A | Chip scale module package in bga semiconductor package |
US7888185B2 (en) | 2006-08-17 | 2011-02-15 | Micron Technology, Inc. | Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device |
KR100840788B1 (ko) * | 2006-12-05 | 2008-06-23 | 삼성전자주식회사 | 칩 적층 패키지 및 그 제조 방법 |
US20080157322A1 (en) * | 2006-12-27 | 2008-07-03 | Jia Miao Tang | Double side stacked die package |
US7518226B2 (en) * | 2007-02-06 | 2009-04-14 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
US9466545B1 (en) | 2007-02-21 | 2016-10-11 | Amkor Technology, Inc. | Semiconductor package in package |
TW200840009A (en) * | 2007-03-27 | 2008-10-01 | Phoenix Prec Technology Corp | Multi-chip semiconductor package structure |
US8421244B2 (en) | 2007-05-08 | 2013-04-16 | Samsung Electronics Co., Ltd. | Semiconductor package and method of forming the same |
KR100923562B1 (ko) | 2007-05-08 | 2009-10-27 | 삼성전자주식회사 | 반도체 패키지 및 그 형성방법 |
JP5014016B2 (ja) * | 2007-08-08 | 2012-08-29 | 三菱電機株式会社 | 半導体装置 |
US7892885B2 (en) * | 2007-10-30 | 2011-02-22 | International Business Machines Corporation | Techniques for modular chip fabrication |
US8258614B2 (en) * | 2007-11-12 | 2012-09-04 | Stats Chippac Ltd. | Integrated circuit package system with package integration |
US7800212B2 (en) * | 2007-12-27 | 2010-09-21 | Stats Chippac Ltd. | Mountable integrated circuit package system with stacking interposer |
US8247893B2 (en) * | 2007-12-27 | 2012-08-21 | Stats Chippac Ltd. | Mountable integrated circuit package system with intra-stack encapsulation |
TW200933868A (en) * | 2008-01-28 | 2009-08-01 | Orient Semiconductor Elect Ltd | Stacked chip package structure |
US7832278B2 (en) * | 2008-05-29 | 2010-11-16 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | Multi-chip package |
JP2009302212A (ja) | 2008-06-11 | 2009-12-24 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
DE102008048420A1 (de) * | 2008-06-27 | 2010-01-28 | Qimonda Ag | Chip-Anordnung und Verfahren zum Herstellen einer Chip-Anordnung |
US7750455B2 (en) * | 2008-08-08 | 2010-07-06 | Stats Chippac Ltd. | Triple tier package on package system |
US8106520B2 (en) | 2008-09-11 | 2012-01-31 | Micron Technology, Inc. | Signal delivery in stacked device |
US8093700B2 (en) * | 2008-12-16 | 2012-01-10 | Freescale Semiconductor, Inc. | Packaging millimeter wave modules |
US7863100B2 (en) * | 2009-03-20 | 2011-01-04 | Stats Chippac Ltd. | Integrated circuit packaging system with layered packaging and method of manufacture thereof |
US8513792B2 (en) * | 2009-04-10 | 2013-08-20 | Intel Corporation | Package-on-package interconnect stiffener |
US8390035B2 (en) * | 2009-05-06 | 2013-03-05 | Majid Bemanian | Massively parallel interconnect fabric for complex semiconductor devices |
US20100314730A1 (en) * | 2009-06-16 | 2010-12-16 | Broadcom Corporation | Stacked hybrid interposer through silicon via (TSV) package |
US8227904B2 (en) | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
US8143097B2 (en) | 2009-09-23 | 2012-03-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP |
US9875911B2 (en) | 2009-09-23 | 2018-01-23 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interposer with opening to contain semiconductor die |
US8008121B2 (en) | 2009-11-04 | 2011-08-30 | Stats Chippac, Ltd. | Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate |
US8987896B2 (en) * | 2009-12-16 | 2015-03-24 | Intel Corporation | High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same |
KR101078740B1 (ko) * | 2009-12-31 | 2011-11-02 | 주식회사 하이닉스반도체 | 스택 패키지 및 그의 제조방법 |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US20110175218A1 (en) | 2010-01-18 | 2011-07-21 | Shiann-Ming Liou | Package assembly having a semiconductor substrate |
US20110186960A1 (en) | 2010-02-03 | 2011-08-04 | Albert Wu | Techniques and configurations for recessed semiconductor substrates |
JP5170134B2 (ja) * | 2010-03-16 | 2013-03-27 | 日本電気株式会社 | 半導体装置及びその製造方法 |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
CN102237342B (zh) * | 2010-05-05 | 2016-01-20 | 中兴通讯股份有限公司 | 一种无线通讯模块产品 |
US8076177B2 (en) | 2010-05-14 | 2011-12-13 | International Business Machines Corporation | Scalable transfer-join bonding lock-and-key structures |
US8288854B2 (en) * | 2010-05-19 | 2012-10-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for making the same |
KR101394205B1 (ko) * | 2010-06-09 | 2014-05-14 | 에스케이하이닉스 주식회사 | 반도체 패키지 |
US20120001339A1 (en) * | 2010-06-30 | 2012-01-05 | Pramod Malatkar | Bumpless build-up layer package design with an interposer |
US8553420B2 (en) | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US8378478B2 (en) | 2010-11-24 | 2013-02-19 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
KR101817159B1 (ko) | 2011-02-17 | 2018-02-22 | 삼성전자 주식회사 | Tsv를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법 |
US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8633576B2 (en) | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US8338963B2 (en) | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8481425B2 (en) | 2011-05-16 | 2013-07-09 | United Microelectronics Corp. | Method for fabricating through-silicon via structure |
US8822336B2 (en) | 2011-06-16 | 2014-09-02 | United Microelectronics Corp. | Through-silicon via forming method |
US8954948B2 (en) | 2011-06-17 | 2015-02-10 | Bae Systems Controls Inc. | Obsolescence tolerant flash memory architecture and physical building block (PBB) implementation |
KR20130007049A (ko) * | 2011-06-28 | 2013-01-18 | 삼성전자주식회사 | 쓰루 실리콘 비아를 이용한 패키지 온 패키지 |
US8828745B2 (en) | 2011-07-06 | 2014-09-09 | United Microelectronics Corp. | Method for manufacturing through-silicon via |
KR101774938B1 (ko) | 2011-08-31 | 2017-09-06 | 삼성전자 주식회사 | 지지대를 갖는 반도체 패키지 및 그 형성 방법 |
US20130082383A1 (en) * | 2011-10-03 | 2013-04-04 | Texas Instruments Incorporated | Electronic assembly having mixed interface including tsv die |
US8404520B1 (en) | 2011-10-17 | 2013-03-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8518823B2 (en) | 2011-12-23 | 2013-08-27 | United Microelectronics Corp. | Through silicon via and method of forming the same |
US9171823B2 (en) | 2011-12-30 | 2015-10-27 | Stmicroelectronics Pte Ltd | Circuit module with multiple submodules |
US8867231B2 (en) * | 2012-01-13 | 2014-10-21 | Tyco Electronics Corporation | Electronic module packages and assemblies for electrical systems |
US8609529B2 (en) | 2012-02-01 | 2013-12-17 | United Microelectronics Corp. | Fabrication method and structure of through silicon via |
US20130228916A1 (en) * | 2012-03-02 | 2013-09-05 | Texas Instruments Incorporated | Two-solder method for self-aligning solder bumps in semiconductor assembly |
US9613917B2 (en) | 2012-03-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) device with integrated passive device in a via |
US8691600B2 (en) | 2012-05-02 | 2014-04-08 | United Microelectronics Corp. | Method for testing through-silicon-via (TSV) structures |
US8901730B2 (en) | 2012-05-03 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for package on package devices |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US8691688B2 (en) | 2012-06-18 | 2014-04-08 | United Microelectronics Corp. | Method of manufacturing semiconductor structure |
US9275933B2 (en) | 2012-06-19 | 2016-03-01 | United Microelectronics Corp. | Semiconductor device |
US8900996B2 (en) | 2012-06-21 | 2014-12-02 | United Microelectronics Corp. | Through silicon via structure and method of fabricating the same |
US8525296B1 (en) | 2012-06-26 | 2013-09-03 | United Microelectronics Corp. | Capacitor structure and method of forming the same |
US8742597B2 (en) | 2012-06-29 | 2014-06-03 | Intel Corporation | Package substrates with multiple dice |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US20140042622A1 (en) * | 2012-08-10 | 2014-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fine Pitch Package-on-Package Structure |
KR20140020626A (ko) * | 2012-08-10 | 2014-02-19 | 삼성전기주식회사 | 3d 반도체 패키지 |
US9190390B2 (en) | 2012-08-22 | 2015-11-17 | Freescale Semiconductor Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
US9093457B2 (en) | 2012-08-22 | 2015-07-28 | Freescale Semiconductor Inc. | Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof |
US9064977B2 (en) | 2012-08-22 | 2015-06-23 | Freescale Semiconductor Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
US9165887B2 (en) | 2012-09-10 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with discrete blocks |
US9209156B2 (en) | 2012-09-28 | 2015-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three dimensional integrated circuits stacking approach |
US8912844B2 (en) | 2012-10-09 | 2014-12-16 | United Microelectronics Corp. | Semiconductor structure and method for reducing noise therein |
US9391041B2 (en) | 2012-10-19 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out wafer level package structure |
US9035457B2 (en) | 2012-11-29 | 2015-05-19 | United Microelectronics Corp. | Substrate with integrated passive devices and method of manufacturing the same |
US8716104B1 (en) | 2012-12-20 | 2014-05-06 | United Microelectronics Corp. | Method of fabricating isolation structure |
US8878353B2 (en) * | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9847284B2 (en) * | 2013-01-29 | 2017-12-19 | Apple Inc. | Stacked wafer DDR package |
US9299670B2 (en) | 2013-03-14 | 2016-03-29 | Freescale Semiconductor, Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
US8884398B2 (en) | 2013-04-01 | 2014-11-11 | United Microelectronics Corp. | Anti-fuse structure and programming method thereof |
US9287173B2 (en) | 2013-05-23 | 2016-03-15 | United Microelectronics Corp. | Through silicon via and process thereof |
US9524950B2 (en) | 2013-05-31 | 2016-12-20 | Freescale Semiconductor, Inc. | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof |
EP3019442A4 (en) | 2013-07-08 | 2017-01-25 | Motion Engine Inc. | Mems device and method of manufacturing |
WO2015042700A1 (en) | 2013-09-24 | 2015-04-02 | Motion Engine Inc. | Mems components and method of wafer-level manufacturing thereof |
US9123730B2 (en) | 2013-07-11 | 2015-09-01 | United Microelectronics Corp. | Semiconductor device having through silicon trench shielding structure surrounding RF circuit |
EP3028007A4 (en) | 2013-08-02 | 2017-07-12 | Motion Engine Inc. | Mems motion sensor and method of manufacturing |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9024416B2 (en) | 2013-08-12 | 2015-05-05 | United Microelectronics Corp. | Semiconductor structure |
US8916471B1 (en) | 2013-08-26 | 2014-12-23 | United Microelectronics Corp. | Method for forming semiconductor structure having through silicon via for signal and shielding structure |
US9048223B2 (en) | 2013-09-03 | 2015-06-02 | United Microelectronics Corp. | Package structure having silicon through vias connected to ground potential |
US9117804B2 (en) | 2013-09-13 | 2015-08-25 | United Microelectronics Corporation | Interposer structure and manufacturing method thereof |
US9025340B2 (en) | 2013-09-30 | 2015-05-05 | Freescale Semiconductor, Inc. | Devices and stacked microelectronic packages with in-trench package surface conductors and methods of their fabrication |
US9036363B2 (en) | 2013-09-30 | 2015-05-19 | Freescale Semiconductor, Inc. | Devices and stacked microelectronic packages with parallel conductors and intra-conductor isolator structures and methods of their fabrication |
US9373527B2 (en) | 2013-10-30 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip on package structure and method |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9263420B2 (en) | 2013-12-05 | 2016-02-16 | Freescale Semiconductor, Inc. | Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication |
US9305911B2 (en) | 2013-12-05 | 2016-04-05 | Freescale Semiconductor, Inc. | Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication |
US9343359B2 (en) | 2013-12-25 | 2016-05-17 | United Microelectronics Corp. | Integrated structure and method for fabricating the same |
JP6590812B2 (ja) | 2014-01-09 | 2019-10-16 | モーション・エンジン・インコーポレーテッド | 集積memsシステム |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US20150221570A1 (en) * | 2014-02-04 | 2015-08-06 | Amkor Technology, Inc. | Thin sandwich embedded package |
US10340203B2 (en) | 2014-02-07 | 2019-07-02 | United Microelectronics Corp. | Semiconductor structure with through silicon via and method for fabricating and testing the same |
US9653443B2 (en) | 2014-02-14 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US10056267B2 (en) | 2014-02-14 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10121768B2 (en) | 2015-05-27 | 2018-11-06 | Bridge Semiconductor Corporation | Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same |
US10354984B2 (en) | 2015-05-27 | 2019-07-16 | Bridge Semiconductor Corporation | Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same |
US11291146B2 (en) | 2014-03-07 | 2022-03-29 | Bridge Semiconductor Corp. | Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same |
US9269700B2 (en) * | 2014-03-31 | 2016-02-23 | Micron Technology, Inc. | Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods |
US20170030788A1 (en) | 2014-04-10 | 2017-02-02 | Motion Engine Inc. | Mems pressure sensor |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US11674803B2 (en) | 2014-06-02 | 2023-06-13 | Motion Engine, Inc. | Multi-mass MEMS motion sensor |
JP6371122B2 (ja) * | 2014-06-05 | 2018-08-08 | 株式会社日立製作所 | パワー半導体装置および樹脂封止型モータ |
US11287486B2 (en) | 2014-12-09 | 2022-03-29 | Motion Engine, Inc. | 3D MEMS magnetometer and associated methods |
US10388607B2 (en) | 2014-12-17 | 2019-08-20 | Nxp Usa, Inc. | Microelectronic devices with multi-layer package surface conductors and methods of their fabrication |
CA3220839A1 (en) | 2015-01-15 | 2016-07-21 | Motion Engine Inc. | 3d mems device with hermetic cavity |
US20160240457A1 (en) * | 2015-02-18 | 2016-08-18 | Altera Corporation | Integrated circuit packages with dual-sided stacking structure |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
TWI582916B (zh) * | 2015-04-27 | 2017-05-11 | 南茂科技股份有限公司 | 多晶片封裝結構、晶圓級晶片封裝結構及其製程 |
KR20170001238A (ko) * | 2015-06-26 | 2017-01-04 | 에스케이하이닉스 주식회사 | 계단형 기판을 포함하는 반도체 패키지 |
US9893058B2 (en) | 2015-09-17 | 2018-02-13 | Semiconductor Components Industries, Llc | Method of manufacturing a semiconductor device having reduced on-state resistance and structure |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9576942B1 (en) | 2015-12-18 | 2017-02-21 | Intel Corporation | Integrated circuit assembly that includes stacked dice |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9754822B1 (en) | 2016-03-02 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
DE102016206607B4 (de) * | 2016-04-19 | 2021-09-16 | Robert Bosch Gmbh | Elektronisches Bauelement und Verfahren zum Herstellen eines elektronischen Bauelements |
DE102016110862B4 (de) * | 2016-06-14 | 2022-06-30 | Snaptrack, Inc. | Modul und Verfahren zur Herstellung einer Vielzahl von Modulen |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10199500B2 (en) | 2016-08-02 | 2019-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer film device and method |
KR102592640B1 (ko) * | 2016-11-04 | 2023-10-23 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
US9935079B1 (en) | 2016-12-08 | 2018-04-03 | Nxp Usa, Inc. | Laser sintered interconnections between die |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
TWI654727B (zh) * | 2017-11-09 | 2019-03-21 | 上海兆芯集成電路有限公司 | 晶片封裝方法 |
US10741532B2 (en) | 2018-03-12 | 2020-08-11 | International Business Machines Corporation | Multi-chip modules |
US10356903B1 (en) * | 2018-03-28 | 2019-07-16 | Apple Inc. | System-in-package including opposing circuit boards |
KR102094068B1 (ko) * | 2018-04-05 | 2020-03-26 | 윤혜진 | 공간 편집용 자리 및 그를 이용한 자리 조립체 |
US11195789B2 (en) * | 2018-11-30 | 2021-12-07 | International Business Machines Corporation | Integrated circuit module with a structurally balanced package using a bottom side interposer |
US20210134690A1 (en) * | 2019-11-01 | 2021-05-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages and methods of manufacturing the same |
US20240030113A1 (en) | 2022-07-21 | 2024-01-25 | Deca Technologies Usa, Inc. | Quad flat no-lead (qfn) package without leadframe and direct contact interconnect build-up structure |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0174224B1 (en) * | 1984-07-27 | 1990-06-13 | Fujitsu Limited | Chip on chip type integrated circuit device |
US5399898A (en) * | 1992-07-17 | 1995-03-21 | Lsi Logic Corporation | Multi-chip semiconductor arrangements using flip chip dies |
US5109320A (en) * | 1990-12-24 | 1992-04-28 | Westinghouse Electric Corp. | System for connecting integrated circuit dies to a printed wiring board |
US5434453A (en) * | 1991-04-26 | 1995-07-18 | Hitachi, Ltd. | Semiconductor integrated circuit device and computer system using the same |
JP2501266B2 (ja) * | 1991-11-15 | 1996-05-29 | 株式会社東芝 | 半導体モジュ―ル |
US5323060A (en) * | 1993-06-02 | 1994-06-21 | Micron Semiconductor, Inc. | Multichip module having a stacked chip arrangement |
US5446247A (en) * | 1993-11-19 | 1995-08-29 | Motorola, Inc. | Electrical contact and method for making an electrical contact |
EP0658937A1 (en) * | 1993-12-08 | 1995-06-21 | Hughes Aircraft Company | Vertical IC chip stack with discrete chip carriers formed from dielectric tape |
US5456004A (en) * | 1994-01-04 | 1995-10-10 | Dell Usa, L.P. | Anisotropic interconnect methodology for cost effective manufacture of high density printed circuit boards |
US5455445A (en) * | 1994-01-21 | 1995-10-03 | Kulite Semiconductor Products, Inc. | Multi-level semiconductor structures having environmentally isolated elements |
US5541449A (en) * | 1994-03-11 | 1996-07-30 | The Panda Project | Semiconductor chip carrier affording a high-density external interface |
KR0137826B1 (ko) * | 1994-11-15 | 1998-04-28 | 문정환 | 반도체 디바이스 패키지 방법 및 디바이스 패키지 |
US5495394A (en) * | 1994-12-19 | 1996-02-27 | At&T Global Information Solutions Company | Three dimensional die packaging in multi-chip modules |
US5608262A (en) * | 1995-02-24 | 1997-03-04 | Lucent Technologies Inc. | Packaging multi-chip modules without wire-bond interconnection |
US5677567A (en) * | 1996-06-17 | 1997-10-14 | Micron Technology, Inc. | Leads between chips assembly |
US5760478A (en) * | 1996-08-20 | 1998-06-02 | International Business Machines Corporation | Clock skew minimization system and method for integrated circuits |
US5790384A (en) * | 1997-06-26 | 1998-08-04 | International Business Machines Corporation | Bare die multiple dies for direct attach |
-
1998
- 1998-06-26 US US09/105,419 patent/US5977640A/en not_active Expired - Lifetime
-
1999
- 1999-05-17 TW TW088107987A patent/TW423082B/zh not_active IP Right Cessation
- 1999-05-17 KR KR10-1999-0017553A patent/KR100404373B1/ko not_active IP Right Cessation
- 1999-05-27 CN CNB991070917A patent/CN1148804C/zh not_active Expired - Fee Related
- 1999-05-31 JP JP11151409A patent/JP3096459B2/ja not_active Expired - Fee Related
- 1999-07-06 US US09/350,274 patent/US6294406B1/en not_active Expired - Lifetime
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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CN101803020B (zh) * | 2007-09-18 | 2012-05-23 | 奥林巴斯株式会社 | 叠层安装结构体和叠层安装结构体的制造方法 |
CN101519183B (zh) * | 2008-01-31 | 2011-09-21 | 台湾积体电路制造股份有限公司 | 具有集成电路管芯的微机电系统封装 |
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US10008475B2 (en) | 2012-09-27 | 2018-06-26 | Intel Corporation | Stacked-die including a die in a package substrate |
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Also Published As
Publication number | Publication date |
---|---|
JP2000156461A (ja) | 2000-06-06 |
US5977640A (en) | 1999-11-02 |
JP3096459B2 (ja) | 2000-10-10 |
US6294406B1 (en) | 2001-09-25 |
CN1148804C (zh) | 2004-05-05 |
KR100404373B1 (ko) | 2003-11-05 |
KR20000005670A (ko) | 2000-01-25 |
TW423082B (en) | 2001-02-21 |
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