CN1241235C - 半导体结构及形成具有缩小间距的晶体管的方法 - Google Patents
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Abstract
本发明提供一种形成具有缩小间距的晶体管的方法,其利用现有的微影工艺即可以使所形成的器件间距缩小至公知器件的一半。因为器件间距的缩小,器件集成度便可以提高,以使集成电路更小且更快。在一较佳实施例中,在一基底上形成导电层、终止层以及多晶硅层,且在多晶硅层上形成光阻层,并在光阻层表面上形成第一高分子材料层。接着利用第一高分子材料层作为蚀刻罩幕定义多晶硅层、终止层以及导电层。之后在基底上形成氧化层,并且回蚀刻氧化层直到多晶硅层暴露出来。随后移除多晶硅层,并且在氧化层的表面上形成第二高分子材料层。然后利用第二高分子材料层作为蚀刻罩幕定义导电层,再将第二高分子材料层移除。
Description
技术领域
本发明是有关于一种半导体器件的制造方法,且特别是有关于一种具有缩小间距的晶体管器件的制造方法。
背景技术
现今集成电路包含许多结构,其包括导电材料、半导体材料(例如以掺杂作为导电定义区域)。例如,晶体管器件一般是以半导体材料来制作,诸如在半导体基底上之一相对薄的栅介电层上形成多晶硅材料,此多晶硅材料将会在基底上被图案化成多个分开的栅极导电物。沿着栅极导电物,基底被暴露的区域将会被植入杂质以形成源极/漏极接面。倘若形成源极/漏极区的掺杂物为n型,则将形成NMOSFET(n沟道)晶体管器件。相反的,若形成源极/漏极区的掺杂物为p型,则将形成PMOSFET(p沟道)晶体管器件。而无论是单独的n沟道器件、单独的p沟道器件或是两者结合使用的器件都会应用在集成电路中。
而晶体管的栅极导电物是利用公知的微影技术定义出的。通常光阻膜,其例如是先将一光阻旋涂至多晶硅材料上,之后利用投射光线(典型的是紫外光)穿透光罩上透光区域,以将影像转移至至光阻上。之后利用光化学反应改变光阻层被曝光的区域的溶解度,再利用溶剂,诸如显影液清洗光阻,以移除其高溶解度的区域,然后再烘烤保留下来的光阻。而这些保留下来的光阻将具有高的抗蚀刻能力,而能移除多晶硅材料。多晶硅材料未被光阻层覆盖的区域将会被蚀刻,而定义出晶体管器件的栅极导电物。
然而,器件尺寸的最小值将受到光阻特征图案的限制,其可能影响的因素包括投射系统的分辨率,所谓分辨率指的是光学系统分辨靠近的两物体的距离。另外,当光通过光罩上狭缝似的透光区域时,绕射效应也可能会非预期的发生,此外,光的散射也可能会影响光学系统的分辨率。如此一来,光罩上的图案将可能无法成功的转移到光阻,而造成光阻特征图案产生偏斜。因此,微影工艺限制了公知集成电路的特征图案的最小宽度。这就是为何利用微影工艺来定义时,要缩小两晶体管的栅极导电物的线宽或距离会如此困难的因素。
由于微影工艺的限制,以公知方法要缩小晶体管器件之间距并无法轻易的达到。在此,所谓间距指的是两相邻且相同型态的结构,譬如是相邻的栅极导电物,其相同点之间的距离。由于器件的间距无法轻易的缩小,因此器件的集成度便无法提高,以符合集成电路小尺寸且速度快的需求。
因此集成电路中的器件间距缩小化的需求是存在的。另一种需求也是存在的,即发展出一种制造集成电路的方法,以使栅极导电物之间的距离或其宽度不再受到微影工艺的限制。
发明内容
本发明提出一种形成具有缩小间距的晶体管器件的方法。利用目前的微影工艺即可以使器件的间距缩小至公知器件的一半,由于器件的间距可以缩小,器件集成度便可以提升,以使集成电路可以更小且更快。
在一较佳实施例中,于一基底上形成一导电层、一终止层以及一多晶硅层,且在多晶硅层上形成一图案化的光阻层,并在光阻层表面上形成一第一高分子材料层。接着利用第一高分子材料层作为蚀刻罩幕定义多晶硅层、终止层以及导电层。之后在基底上形成氧化层,并且回蚀刻氧化层直到多晶硅层暴露出来。随后移除多晶硅层,并且在氧化层的表面上形成第二高分子材料层。然后利用第二高分子材料层作为蚀刻罩幕定义导电层。再将第二高分子材料层移除。
依据本发明的目的,晶体管利用多个工艺步骤而形成的。首先在一半导体基底上连续沉积一第一导电层、一终止层以及一第二导电层。其中第一以及第二导电层可以是一导电或是半导体材料构成,其较佳的是多晶硅。而终止层可以是一介电材料,其蚀刻速率小于第二导电层的蚀刻速率,也就是即当使用一蚀刻剂(蚀刻液)时,对第二导电层具有较高的蚀刻选择性。例如是,导电层包括多晶硅,终止层可以是氮化硅或是氮氧化硅。接着,利用一微影工艺图案化第二导电层上的一光阻层。之后,第一介电层将会选择性的形成在光阻层的表面上。第一介电层可以是由一高分子材料所构成,其利用电浆增益型化学气相沉积法所形成。随后,利用第一介电层做为一蚀刻罩幕定义第二导电层,然后再将光阻层以及第一介电层移除。
接着,在基底上方沉积一绝缘层,其形成至第二导电层上方。绝缘层可以是由氧化硅所构成,其例如是一旋涂氧化层,且其蚀刻速率小于第二导电层的蚀刻速率,意即当使用一蚀刻物时,其对第二导电层具有高的蚀刻选择性。之后,移除绝缘层至第二导电层的上表面,以使第二导电层暴露出来。移除绝缘层的方法可以利用干式蚀刻工艺或是化学机械研磨工艺。随后,移除第二导电层,暴露出终止层,然后再于绝缘层的表面上形成第二介电层,其例如是一高分子材料层,以作为一蚀刻罩幕。形成第二介电层的方法可以是利用电浆增益型化学气相沉积法。之后,移除未被第二介电层覆盖的终止层以及第一导电层。
移除第二介电层,而留下一基底上分离开来的数个栅极导电物,以及位于栅极导电物上的蚀刻终止材料。在基底以及数个栅极导电物之间还包括形成有一栅极介电层。而后续在栅极导电物之间的基底中植入杂质以形成源极/漏极,即可以形成晶体管器件。而每一栅极导电物的宽度实质上小于公知特征图案(图案化光阻层)的宽度。另外,栅极导电物之间的间距实质上小于公知特征图案(图案化光阻层)之间的间距。依据本发明的方法所形成的晶体管器件的间距相较于公知晶体管器件的间距明显缩小许多。
任何结合本发明特征的特征都包含在本发明的范围之内。为让本发明的上述和其它目的、特征、和优点能更明显易懂,下文特举一较佳实施例,并配合附图,作详细说明。
附图说明
图1是公知硅基底上具有栅氧化层以及多晶硅层的剖面示意图,其依照公知制造方法将一光阻层在多晶硅层上图案化;
图2是描绘图1的剖面示意图,其利用光阻层作为一蚀刻罩幕以定义多晶硅层;
图3是一硅基底的剖面示意图,其中在硅基底上形成有一栅氧化层/第一多晶硅层终止层/第二多晶硅层的堆栈薄膜结构,且其依照本发明一较佳实施例将一光阻层在堆栈膜层上图案化;
图4是描绘图3的剖面示意图,其依照本发明一较佳实施例而将一第一高分子材料层形成在光阻层的表面上;
图5是描绘图4的剖面示意图,其依照本发明一较佳实施例而利用第一高分子材料层作为一蚀刻罩幕以定义第一多晶硅层、终止层以及第二多晶硅层;
图6是描绘图5的剖面示意图,其依照本发明一较佳实施例而在基底上方形成一氧化层;
图7是描绘图6的剖面示意图,其依照本发明一较佳实施例而移除绝缘层至第二多晶硅层的上表面;
图8是描绘图7的剖面示意图,其依照本发明一较佳实施例而移除第二多晶硅层以暴露出终止层;
图9是描绘图8的剖面示意图,其依照本发明一较佳实施例而在氧化层的表面上形成一第二高分子材料层;以及
图10是描绘图9的剖面示意图,其依照本发明一较佳实施例而利用第二高分子材料层作为蚀刻罩幕,以定义第一多晶硅层以及终止层。。
标示说明
2、10:基底 4、12:栅氧化层
6、14、18:多晶硅层 8、20:光阻层
16:终止层 22、26:高分子材料层
24:氧化层 a、b:间距
具体实施方式
下文特举本发明较佳的实施例,并配合所附图式作详细说明。在此,图标中相似或相同的构件以相同的标号表示。值得注意的是,图标为简图,其并非实际的尺寸比例。为了使本发明更加明显易懂,方向,诸如顶部、底部、左边、右边、上面、下面、上方、下方、底下、后方以及前方都是以图标为基准,上述的方向并不限本发明的范围。
虽然在本实施例中以特定图标以详细说明之,但并非用以限定本发明。以下详细的描述,虽然为一较佳实施例,但在不脱离本发明的精神和范围内,当可作些许之更动与润饰,因此本发明的保护范围当视权利要求书所界定者为准。例如一熟习该项技术的人依据本发明实行本发明的半导体制造方法包括选择性蚀刻一导电多晶硅层,其对蚀刻物具有一选择性大于底下的终止层的选择性(对于相同依蚀刻物而言),因此不同的导电材料,不同的终止层材料、不同的蚀刻物以及不同的组合,皆可以依据本发明而执行。
在此所描述的工艺步骤以及结构并非一完整的流程以制造一晶体管器件。本发明可以与许多公知已在使用的集成电路制造技术结合,且一般已在实行的工艺步骤亦包括在本发明中。
请参照图1以及图2,其绘示是公知制造晶体管器件的栅极导电物的剖面图。请参照图1,一栅氧化层4包括二氧化硅,形成在一硅基底2上。形成栅氧化层4的方法利用热氧化法以在基底2的表面成长出二氧化硅层,意即加热基底并使其暴露在氧气中而形成。之后,通入硅烷气体源而利用化学气相沉积法(CVD)在栅氧化层4上形成一多晶硅层6。接着,进行一微影工艺以在多晶硅层6上图案化一光阻层8。但是,微影工艺限制了光阻特征图案8的最小尺寸。
之后,请参照图2,利用一蚀刻技术,诸如干式蚀刻、电浆蚀刻,以移除未被光阻层8覆盖的多晶硅层6,其中光阻层8具有高的抗蚀刻能力而对多晶硅具有高蚀刻选择性。意即在图案化多晶硅层6的过程中,光阻层8作为一蚀刻罩幕。在此,定义的多晶硅层6即为栅极导电层,且其宽度大致等于光阻特征图案的宽度。在蚀刻工艺之后,光阻层将会由多晶硅层6的表面剥除。在图2中,两栅极导电物的垂直左侧表面之间的距离”a”,表示栅极导电物的间距,其为公知晶体管器件的间距。而间距“a”的最小值受限于微影工艺的限制,因此无法轻易的利用公知制造方法缩小间距。
请参照图3,绘示形成一图案化光阻层于一多层堆栈膜层的图标。较详细的说明是,一栅氧化层12、一第一多晶硅层14、一终止层16以及一第二多晶硅层18依序形成在一基底10上。虽然基底10较佳的是包括单晶硅材质,但是基底10也可以以氮化镓、砷化镓或是公知技术中其它任何适用的材质取代。基底10可以轻微掺杂有p型杂质(例如砷、磷以及锑),或是n型杂质(例如硼以及二氟化硼)。栅氧化层12较佳的是包括二氧化硅,其利用热氧化法形成。在热氧化工艺过程中,基底10被暴露在氧气相关的环境中,以在基底表面形成二氧化硅。在另一实施例中,栅氧化层12亦可以以公知技术中其它适合的介电材料取代。
而第一多晶硅层14以CVD方法沉积在栅氧化层12上,且第二多晶硅层18亦可以以CVD方法沉积在终止层16上。多晶硅层的CVD包括将硅烷气体分解成固态硅以及氢气。基底10将被放置在一CVD反应的腔室中,并控制反应气体的状况,之后硅烷气体将会通入反应腔室中,而在基底的表面形成一固态硅层。同样的,多晶硅层14、18也可以以其它导电或半导体材料取代。而多晶硅层14在沉积过程或是沉积之后可以掺杂p型或是n型的杂质,以提高多晶硅层14的导电性。
终止层16材质的蚀刻速率需小于多晶硅层18的蚀刻速率,亦即当使用一蚀刻物时,其必须对多晶硅具有高蚀刻选择性。较佳的是,终止层16的材质包括氮化硅,其利用含有二氯硅烷以及氨气或是氮气的电浆以CVD沉积而形成。此外,终止层16亦可以是氮氧化硅,其利用含有硅烷以及氨气或一氧化二氮的电浆以CVD沉积而形成。另外,终止层16亦可以是氧化硅。
利用光学微影工艺在第二多晶硅层18上形成图案化的光阻层20。在一般公知技术中,其先将一光阻层旋涂到晶圆上,之后将晶圆放置在一图案化的工具中,诸如步进机,且对齐于一光罩,并以紫外光照射以曝光之,此光罩的尺寸可以是只足够大到覆盖晶圆的一小部份,因此需步进且多次的对晶圆进行曝光,直到晶圆整个部分或是预定的部分都被紫外光曝光为止;之后晶圆会被移至一显影溶液中以溶解未被紫外光曝光的光阻,即可形成图案化的光阻层20。在本实施例中,图案化光阻层20的最小间距”a”为微影工艺允许的最小值。
请参照图4,一第一高分子材料层22选择性的形成在光阻层20的表面上,其以电浆增益型化学气相沉积法所形成。第一高分子材料层22可以利用如美国申请案第09/978,546号所公开的方法及设备来形成。关于第一高分子材料层22的形成,可以是用蚀刻机来进行,其工艺参数在反应中控制其沉积/蚀刻率,以使第一高分子材料22形成在光阻层20的顶部及/或侧壁。在此,反应气体较佳的是使用与底下的多晶硅层18(图4)或终止层16(图9)不反应的气体。在本实施例中,第一高分子材料层22是在双重电浆蚀刻机台中使用二氟化碳以及八氟化四碳作为反应气体而形成的。
请参照图5,第一高分子材料层22作为一蚀刻罩幕以图案化多晶硅层14、18以及终止层16,而暴露出部分栅介电层12。图案化多晶硅层14、18以及终止层16利用已知的蚀刻技术。在一较佳实施例中,是使用非等向高压电浆蚀刻(离子轰击在垂直方向大于水平方向)来蚀刻多晶硅层以及终止层,其对高分子材料层的蚀刻相对低。在本实施例中,蚀刻反应在栅氧化层12被移除之前就可以终止。较适当的实例中,蚀刻化学物是碳氟化合物/氧气/氢气。然而,其它材料,诸如其它介电材料,亦可以取代第一高分子材料层22,而这些材料可以选择性的形成在光阻层20上且可以作为蚀刻罩幕。在定义多晶硅层14、18以及终止层16之后,晶圆将会被移至一化学浴溶液中,以移除第一高分子材料层22以及光阻层20,而形成图5的结构。
接着,请参照图6,在图5的结构上形成一氧化层24,覆盖多晶硅层14、18以及终止层16。氧化层24可以是一旋涂氧化层,其以旋转涂怖的方式而形成在第二多晶硅层18上方。而氧化层24的蚀刻速率较佳的是小于第二多晶硅层18的蚀刻速率,意即当使用一蚀刻物时,其对多晶硅层具有高蚀刻选择性。在另一实施例中,其它材料,诸如其它绝缘材料,也可以用来取代绝缘层24。
请参照图7,回蚀刻氧化层24直到第二多晶硅层18暴露出来,其是将晶圆放置在干式蚀刻机台中以移除氧化层24,而蚀刻物可以是四氟化碳/氩气电浆。另外,氧化层24可以利用化学机械研磨(CMP)工艺移除至第二多晶硅层18的上表面。CMP工艺是在含有胶体硅(二氧化硅研磨料的悬浮物)以及蚀刻剂(例如稀释氢氟酸)的碱性研磨液中机械性的磨耗晶圆。在此,可达到全面性的平坦表面,如图7所绘示。
之后,请参照图8,利用原位工艺移除第二多晶硅层18,其中晶圆留在先前用来移除氧化系24的蚀刻机台中。较详细的说明是,利用电浆而非等向性的蚀刻第二多晶硅层18,其例如是使用相较于介电材料,对硅具有高蚀刻选择性的溴化氢/氦气/氧气。在较佳实施例中,选择性电浆对第二多应硅层18具有高选择性,其相较于氧化层24以及终止层16而言。换言之,蚀刻第二多晶硅层18时能有充分的时间以完全移除第二多晶硅层,而且在终止层16被移除之前,就会终止电浆蚀刻步骤。
请参照图9,第二高分子材料层26形成在氧化层24的表面上,其同样是以先前所述的电浆增益型化学气相沉积法所形成。之后利用第二高分子材料层26作为一蚀刻罩幕图案化终止层16以及第一多晶硅层14,其例如是利用四氟化碳/氧气/氢气电浆的非等向性高压电浆蚀刻工艺。此蚀刻物较佳的是对底下的第二高分子材料层26不反应。此蚀刻步骤可以选择在移除栅氧化层26之前就终止。同样的,第二高分子材料层26可以以其它材料取代,例如其它介电材料,其只要是可以选择性形成在氧化层24上,且能作为蚀刻罩幕之用即可。
之后,移除第二高分子材料层26,其例如是利用灰化技术,而留下复数个具有缩小间距的栅极导电物,如图10所示。接下来,移除终止层16以及氧化层24,并且在第一多晶硅14的栅极导电物之间的基底10中植入杂质以形成源极/漏极,即形成晶体管器件。在本实施例中,两相邻栅极导电物之间隙几乎相同,而距离”b”表示栅极导电物的间距,而形成依据本发明的晶体管器件。比较图2的间距“a”与图10的间距“b”,间距“b”几乎只有间距“a”的一半。另外,还可以比较图2、图3以及图10,本发明的栅极导电物的宽度小于微影工艺允许的最小宽度。因此,本发明提供一种利用现有微影工艺以形成缩小晶体管器件间距的方法,其相较于公知晶体管器件的间距明显缩小许多。由于器件的间距可以缩小,因此器件的集成度便可以提升。
虽然本发明已以较佳实施例公开如上,然其并非用以限定本发明,任何熟悉此技术者,在不脱离本发明的精神和范围内,当可作些许之更动与润饰,因此本发明的保护范围当视权利要求书所界定者为准。
Claims (14)
1.一种形成具有缩小间距的晶体管的方法,其特征在于,包括:
提供一基底,该基底上已形成有一第一导电层、一终止层以及一第二导电层;
在该第二导电层上形成一图案化的光阻层;
在该光阻层的表面上形成一第一介电层;
利用该第一介电层为一蚀刻罩幕定义该第一导电层、该终止层以及该第二导电层;
移除该光阻层以及该第一介电层;
在该基底上方形成一绝缘层;
移除该绝缘层至该第二导电层的上表面,以使该第二导电层暴露出来;
移除该第二导电层;
在该绝缘层的表面上形成一第二介电层;
利用该第二介电层作为一蚀刻罩幕定义该终止层以及该第一导电层;以及
移除该第二介电层。
2.如权利要求1所述的方法,其特征在于,移除该第二导电层的方法包括蚀刻该第二导电层,其中该绝缘层的蚀刻速率小于该第二导电层的蚀刻速率。
3.如权利要求2所述的方法,其特征在于,该终止层选自氧化硅、氮化硅以及氮氧化硅所组成的族群其中之一。
4.如权利要求1所述的方法,其特征在于,该第一以及第二导电层包括多晶硅。
5.如权利要求1所述的方法,其特征在于,该第一以及第二介电层包括一高分子材料层,其于一蚀刻机台中形成。
6.如权利要求5所述的方法,其特征在于,该绝缘层包括氧化层。
7.如权利要求1所述的方法,其特征在于,移除该第二导电层的方法包括利用一干式蚀刻工艺。
8.如权利要求1所述的方法,其特征在于,移除该绝缘层的方法包括利用一干式蚀刻工艺。
9.如权利要求1所述的方法,其特征在于,移除该绝缘层的方法包括利用化学机械研磨工艺研磨该绝缘层。
10.一种半导体结构,其特征在于,包括:
数个栅极导电物,分开配置在一基底上,其中该些栅极导电物是利用权利要求1所述方法制作的;以及
一蚀刻终止材料,配置在该些栅极导电物上,
其中每一该些栅极导电物的宽度实质上小于一微影工艺允许的最小值。
11.如权利要求10所述的结构,其特征在于,该些栅极导电物包括多晶硅。
12.如权利要求10所述的结构,其特征在于,该蚀刻终止材料选自氧化硅、氮化硅以及氮氧化硅所组成的族群其中之一。
13.如权利要求10所述的结构,其特征在于,还包括一栅极介电层,配置在该基底以及该些栅极导电物之间。
14.如权利要求13所述的结构,其特征在于,还包括一绝缘材料,其配置在交替的该些栅极导电物之间。
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2002
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CN1471129A (zh) | 2004-01-28 |
TWI220266B (en) | 2004-08-11 |
TW200307986A (en) | 2003-12-16 |
US6734107B2 (en) | 2004-05-11 |
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