CN1258216C - 形成多层导电线的方法 - Google Patents

形成多层导电线的方法 Download PDF

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CN1258216C
CN1258216C CNB02160424XA CN02160424A CN1258216C CN 1258216 C CN1258216 C CN 1258216C CN B02160424X A CNB02160424X A CN B02160424XA CN 02160424 A CN02160424 A CN 02160424A CN 1258216 C CN1258216 C CN 1258216C
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manufacturing process
conductive line
barrier layer
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CN1466191A (zh
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金东俊
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MagnaChip Semiconductor Ltd
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    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

本发明涉及一种在半导体装置内形成多层导电线的方法。在一下方导电线的接点的一部分，是选择性地蚀刻一给定的厚度。然后一牺牲阻挡层形成在该下方导电线的蚀刻的部分。利用此结构，可在后续的绝缘膜制造工艺中防止该下方导电线的氧化或该下方导电线材料的扩散。同时，在清洗一接点区域的制造工艺中所产生的一下方导电线的侧壁扩散，即可由该牺牲阻挡层来防止。因此，可降低在上方及下方导电线之间所发生的漏电流。

Description

形成多层导电线的方法
技术领域
本发明总体上涉及一种在半导体装置中形成一多层导电线的方法，更具体地说，涉及一种形成多层导电线的方法，其可改善该半导体装置的可靠性，其是藉由防止由于铜杂质造成的污染问题，以及防止由于在一双重金属镶嵌图案中铜的重新沉积造成的导电线到导电线的漏电。
背景技术
一般而言，在一半导体装置、电子装置或类似者中，使用导电薄膜的技术，像是铝(Al)、钨(W)或类似者，其沉积在一绝缘膜上，然后该导电膜即由常用的光刻制造工艺及干蚀刻制造工艺来图案化来形成一导电线，其已经广泛地使用为一种形成导电线的技术。特别是，对于努力要来降低需要高速的半导体装置的逻辑装置中的RC延迟时间，最近亦在研究使用具有低阻抗的金属，例如铜(Cu)，来取代铝(Al)或钨(W)来做为导电线。
但是在使用铜(Cu)来形成导电线的制造工艺中，因为铜的图案化制造工艺相比于铝或钨的制造工艺较困难，一种形成沟槽，然后将该沟槽埋入来形成该线的制造工艺即被应用，其称之为金属镶嵌制造工艺。该金属镶嵌制造工艺可分类成单一金属镶嵌制造工艺和双重金属镶嵌制造工艺，在单一金属镶嵌制造工艺中，形成一贯通孔，该贯通孔填充以一导电材料，然后形成用作导电线的沟槽，以掩埋该导电线；在双重金属镶嵌制造工艺中，形成贯穿孔及沟槽，且贯穿孔及用作导电线的沟槽同时填入用作导电线的材料。
如果在一构成该双重金属镶嵌制造工艺的一单元制造工艺中使用双重金属镶嵌制造工艺来形成该多层导电线，当执行一化学机械研磨(CMP)制造工艺来形成一下方导电线，及一双频率蚀刻制造工艺来预先清洗该下方导电线及一上方导电线之间的接点部份，该下方导电线的污染物，例如在使用铜来形成下方导电线时的铜(Cu)污染物，其会停留在该层间绝缘膜的表面上，并在该双重金属镶嵌图案内的侧壁上(即包括一贯穿孔及一沟槽)。这些铜杂质可降低该半导体装置的漏电特性。因此，为了制造出一可靠的半导体装置，非常需要一有效的制造工艺控制。再者，因为该半导体装置的层间绝缘膜是由在一高密度SiO2系列中具有多孔性的低介电常数的薄膜所取代，由于铜杂质造成半导体装置的可靠性降低的问题变得更加地重要。因此，为了解决上述的问题，已经提出一清洗制造工艺及一形成抗扩散膜的制造工艺成为制造该多层导电线的制造工艺中的重要问题。
发明内容
本发明用来解决以上的问题，而本发明的任务是要改善半导体装置的可靠性，以防止由于铜杂质造成的污染问题，以及由于在该双重金属镶嵌图案中铜的重新沉积造成的导电线到导电线的漏电。
本发明另一任务是要防止当形成一多层导电线时增加的介电常数而增加了RC延迟。
本发明又另一任务是要抑制一介层窗孔的成品率降低，藉由当形成该多层导电线时防止在该介层窗孔内产生空洞。
本发明又另一任务是要改善该铜导电线的成品率，藉由抑制该介层窗孔的成品率降低，亦防止铜原子的扩散。
本发明的另一任务为防止由于一后续退火制造工艺的铜原子的穿透，其藉由防止在常用氩(Ar)溅射制造工艺期间重新沉积铜原子在该介层窗孔的内侧壁上。
为了实现以上的任务，根据本发明的形成该多层导电线的方法的特征在于，其包括在一其中形成有一下方层的半导体基板上形成一下方导电线的步骤，执行一湿式清洗制造工艺来移除遗留在整个结构上的杂质并蚀刻该下方导电线的曝光的部份，执行一选择性成长制造工艺来在该下方导电线的蚀刻部份处形成一牺牲阻挡层，其是在执行该湿式清洗制造工艺的步骤中蚀刻，形成一层间绝缘膜在整个结构上，藉由一双重金属镶嵌制造工艺来蚀刻该层间绝缘膜，所以可暴露该牺牲阻挡层，以形成一双重金属镶嵌图案，并沉积一电镀膜来埋入该双重金属镶嵌图案，然后执行一化学机械研磨制造工艺来形成一上方导电线，其中该下方导电线及该上方导电线为铜导电线。
附图说明
本发明的前述观点与其它特征将配合附图说明如下，其中：
图1到图10所示为用以解释根据本发明一优选具体实施例的形成一多层导电线的方法的半导体装置的横截面图；
图11所示为根据本发明一优选具体实施例来执行一湿式清洗制造工艺的方法。
具体实施方式
本发明将利用一优选具体实施例并参考附图来详细说明，其中相似的参考号码可用来代表相同或相似的零件。
图1到图10所示为用以解释根据本发明一优选具体实施例的形成一多层导电线的方法的半导体装置的横截面图。
现在请参考图1，一绝缘膜(以下称之为「第一层间绝缘膜」)104做为一低介电常数的绝缘膜，其是沉积在一半导体基板102上，其中使用碳、含氟低介电氧化硅或类似者来形成一给定的下方层(未示出)。举例而言，该下方层可为一线层、一绝缘层及一阻挡层中任何一个，或具有其中至少两个或更多的堆栈结构。
接着，一硬掩模(以下称之为「第一硬掩模」)106即使用一密集薄膜来形成在该第一层间绝缘膜104上，所以并未曝光该第一层间绝缘膜104。此时，考虑到与后续的第二层间绝缘膜114(参见图5)的黏结力，并藉以防止由于一后序H2等离子处理造成该低介电常数的第一层间绝缘膜104的劣化(参见图3)，该第一硬掩模106使用具有一对于H2有保护能力的薄膜所形成。
然后，一光致抗蚀剂覆盖在整个结构上。然后一光致抗蚀剂图案(未示出)即藉由使用一光掩模的一曝光制造工艺及一显影制造工艺来形成。接下来，该第一层间绝缘膜104藉由使用该光致抗蚀剂图案做为一光掩模的蚀刻制造工艺来蚀刻，藉此形成一接触孔(未示出)，透过其来曝光该下方层，或由该双重金属镶嵌制造工艺及该单一金属镶嵌制造工艺中的一种来形成一金属镶嵌图案。然后该光致抗蚀剂图案藉由一剥离制造工艺来移除。
然后，一种具有防止铜扩散的功能的阻挡层108(以下称之为「第一阻挡层」)即形成在整个结构上，包括该接触孔的一内表面(即包括一内侧及一下方侧)。此时，该第一阻挡层108可使用Ta、TaN、TaAlN、TaSiN、TaSi2、Ti、TiN、TiSiN、WN、Co及CoSi2中任何一个来形成。
接着，一种子层(未示出)(以下称之为「第一种子层」)即沉积在该第一阻挡层108上。此时该第一种子层可使用Cu、Pt(铂)、Pd(钯)、Ru(铷)、Sr(锶)、Rh(铑)及Co(钴)中任一个来形成。
然后，一电镀制造工艺(EP)或一化学气相沉积(CVD)制造工艺即对于整个结构来执行，所以该接触孔，藉此即形成一铜电镀膜(以下称之为「第一电镀膜」)(未示出)。
然后，对于该第一电镀膜执行一热处理制造工艺，例如一退火制造工艺，以结晶化该第一电镀膜。形成在该第一硬掩模106及该第一电镀膜之上的第一阻挡层108即藉由一化学机械研磨(CMP)制造工艺来移除，藉此形成一下方导电线110。
请参考图2，为了移除遗留在该第一硬掩模106的上表面之上的铜杂质(参见图11)，并蚀刻该下方导电线110一给定的厚度，其执行如图11之湿式清洗制造工艺。
如图11所示，该湿式清洗制造工艺由沉浸该晶片(也就是形成该下方导电线的半导体基板)到一清洗容器200中，其中填有一硝酸溶液300。此时，对于该硝酸蚀刻溶液300，一溶液是以比例2∶1∶10来混合HNO3、HF及H2O，一溶液是有比例1∶10来混合HF及H2O，及一溶液以比例1∶5来混合HNO3及H2O，其依序来使用。此时，该湿式清洗制造工艺可藉由沉浸该晶片到含有一溶液的该清洗容器200，其中HNO3、HF及H2O的混合比例为2∶1∶10，或首先沉浸该晶片到含有一溶液的清洗容器200，其中HF及H2O的混合比例为1∶10，其次沉浸该晶片到含有一溶液的清洗容器200，其中HNO3及H2O的混合比例为1∶5。
虽然该湿式清洗制造工艺中，该下方导电线110的上方部份的一部份是蚀刻/移除一给定厚度，如‘A’所示。此时，其优选地是该清洗制造工艺即执行来蚀刻该下方导电线110之上方部份约50到100的厚度。
请参考图3，为了藉由曝光及移除不需要的材料等来移除遗留在该下方导电线110的上表面上的一氧化铜(CuO)薄膜，例如遗留在该整个结构上的污染物及粒子，执行使用H2等离子的预清洗制造工艺。
请参考图4，在该处理室中于该下方导电线110上的原处形成一牺牲阻挡层112，其中执行该预清洗制造工艺。
该牺牲阻挡层112形成在一部份中，其中该下方导电线110的部份即由图2的清洗制造工艺来蚀刻。为此，在沉积该牺牲阻挡层112之前，该下方导电线110的上表面即经历使用H2或SiH4气体的表面处理制造工艺，其温度为250到400℃，所以可启动该下方导电线110。因此，因为启动该下方导电线110，而非加速该第一硬掩模106，该牺牲阻挡层112仅在一后续的选择性成长制造工艺中形成在该下方导电线110处。
同时，该牺牲阻挡层112即在原处在该处理室中使用化学气相沉积(CVD)的选择性成长制造工艺，其中执行该表面处理制造工艺，其是在执行该表面处理制造工艺之后。一般而言，一种在该半导体制造工艺中可靠地形成该选择性阻挡层的方法，如果其使用藉由CVD制造工艺的钨(W)系列的阻挡时即有可能。因此，钨(W)是成长在该下方导电线110上，以形成该牺牲阻挡层112。除了钨之外，因为所有可以执行选择性成长制造工艺的金属材料皆可使用，而可能有许多类型的阻挡。
现在请参考图5，一绝缘膜(以下称之为「第二层间绝缘膜」)114使用一低介电常数的绝缘膜来沉积于整个结构上，其使用例如氧化硅、含氟氧化硅、含氟的氧化物等。一般而言，碳或含氟的氧化硅之介电常数比氧化硅要低。碳或含氟的氧化硅之介电常数可藉由调整碳或氟的量来控制。此时，因为图2所示的A部份是由该牺牲阻挡层112所隔离，用于防止铜的扩散的绝缘膜(例如一介电阻挡)，其在当后续沉积绝缘膜时并不需要。因此，因为在该常用制造工艺中插入的绝缘膜并不需要，其可降低整体的介电常数。
同时，最佳地是该第二层间绝缘膜114使用一低介电常数的单一绝缘膜所形成，其视为整体的介电常数，如图5所示。但是，考虑到一后续的双重金属镶嵌制造工艺，该第二层间绝缘膜114包括定义一后续的介层窗孔(参见图6中的118)的低介电常数的下方绝缘膜，定义一后续沟槽(参见图6中的120)的低介电常数的上方绝缘膜，及在一低介电常数的下方绝缘膜及一低介电常数的上方绝缘膜之间形成沟槽的蚀刻中止层。
接着，一硬掩模(以下称之为「第二硬掩模」)116即使用一密集薄膜来形成在该第二层间绝缘膜114上，所以并未曝光该第二层间绝缘膜114。此时，该第二硬掩模116可使用例如用于第一硬掩模106的相同的材料。
请参考图6，该第二硬掩模116及该第二层间绝缘膜114由该双重金属镶嵌制造工艺来蚀刻。然后该介层窗孔118及该沟槽120藉由该双重金属镶嵌图案所形成。此时，在该双重金属镶嵌制造工艺中，其可使用一预介层窗模式，其中首先形成该介层窗孔118，然后形成该沟槽120，以及一厚介层窗模式，其中首先形成该沟槽120，然后形成该介层窗孔118。一般而言，其优选地是该双重金属镶嵌制造工艺系在该预介层窗模式中执行，而非在该后介层窗模式，藉以得到具有下方导电线110的稳固接口。
请参考图7，为了降低一接触阻抗，对于该牺牲阻挡层7执行使用氩(Ar+)的溅射制造工艺，其可在该蚀刻制造工艺或在空气中氧化其间被氧化。该牺牲阻挡层112的一部份藉由Ar溅射制造工艺来蚀刻。藉此蚀刻的该牺牲阻挡层112的该部份的材料即重新沉积在该介层窗孔118的内侧壁(‘B’部份)上，做为该介层窗孔118的保护膜。藉由此方法，不仅可以防止由于常用的产生铜沉积在该介层窗孔的侧壁上所造成的该装置中的劣化，亦可控制该牺牲阻挡层112的厚度来具有一目标厚度。藉此原因，其有可能最小化在该接触区域处的绝缘膜的劣化及阻抗值的增加。
现在请参考图8，一阻挡层122(以下称之为「第二阻挡层」)，其具有一功能来防止铜的扩散形成在整个结构上，其包括该介层窗孔118及该沟槽120之内表面(即包括一内侧及一下方侧)。此时，该第二阻挡层122可使用Ta、TaN、TaAlN、TaSiN、TaSi2、Ti、TiN、TiSiN、WN、Co及CoSi2中任一个来形成。
接着，一种子层124(以下称之为「第二种子层」)即沉积在该第二阻挡层122上。此时该第二种子层124可使用Cu、Pt(铂)、Pd(钯)、Ru(铷)、Sr(锶)、Rh(铑)及Co(钴)中任一个来形成。
请参考图9，该电镀制造工艺对于整个结构来执行，所以埋入有该介层窗孔118及该沟槽120，藉此形成一铜电镀膜(以下称之为「第二电镀膜」)126。然后该第二电镀膜126即由一热处理制造工艺结晶化，例如一退火制造工艺。
请参考图10，该第二电镀膜126经历该CMP制造工艺来依序地移除该第二电镀膜126、该第二种子层124及该第二阻挡层122，其是沉积在该第二层间绝缘膜114，藉此形成一上方导电线128。
如上所述，根据本发明，于形成该上方导电线之前，该牺牲阻挡层形成在该下方导电线，以降低做为一常用介电阻挡的绝缘膜。因此，本发明具有的优选效果，其可降低该绝缘材料的整体介电常数。同时，在该预清洗期间，在该接触区域形成一自我对准的阻挡。本发明可防止在该接点上的横向扩散。
再者，在本发明中，由于该介层窗孔的误对准之下方导电线之蚀刻即可藉由形成该牺牲阻挡层来事先防止。因此，本发明具有一优越的效果为，其可当该下方导电线的材料由于该下方导电线的蚀刻而重新沉积在该层间绝缘膜上时，即可防止在该层间绝缘膜的绝缘特性发生劣化。
同时，在本发明中，于形成该牺牲阻挡层之前，遗留在该下方导电线的上方表面上及该第一层间绝缘膜的上方表面上的铜杂质即藉由执行该下方导电线的清洗制造工艺来移除。因此，本发明具有一优越的好处为，其可降低该上方及下方导电线之间所产生的漏电流。
此外，根据本发明，该下方导电线的上方部份的一部份即蚀刻一给定厚度，然后执行一选择性成长制造工艺来在该下方导电线的蚀刻的部份处选择性地形成该牺牲阻挡层。因此，本发明的有利的效果为其可排除额外的光刻及蚀刻制造工艺。
再者，于本发明中，于形成该牺牲阻挡层之前，即对于该下方导电线执行一H2等离子制造工艺。因此，本发明可改善该下方导电线及该牺牲阻挡层之间的接口特性。
同时，在本发明中，于该双重金属镶嵌制造工艺之后，该牺牲阻挡层藉由一氩溅射制造工艺来蚀刻，以变薄该牺牲阻挡层的厚度。因此，本发明可降低整体介电常数。
附带地，根据本发明，该牺牲阻挡层即蚀刻，而构成该蚀刻的牺牲阻挡层的材料可藉由该氩溅射制造工艺来同时重新沉积在该介层窗孔的内侧壁上。因此，本发明具有一有利的效果为其可改进在该介层窗孔内该阻挡层的梯级覆盖。
同时，本发明具有一有利的效果为，其由于改进了该介层窗孔内的梯级覆盖来在使用电镀的沉积制造工艺时而改进该电镀膜之间隙填入能力。
本发明已配合参考一特定应用与一特定具体实施例加以说明。对于取得本发明说明的本领域的技术人员而言应了解本发明范畴内的其它修改与应用。
因此随附权利要求的范围用来涵盖本发明范畴内的任何与所有此类应用、修改以及具体实施例。

Claims (7)

1.一种形成多层导电线的方法，其包括以下步骤：
(a)在一已形成下方层的半导体基板上形成一下方导电线；
(b)执行一湿式清洗制造工艺来移除遗留在该整个结构上的杂质，并蚀刻该下方导电线的曝露的部份；
(c)执行一选择性成长制造工艺来在该下方导电线的在步骤(b)中被蚀刻的部分处形成一牺牲阻挡层；
(d)在该整个结构上形成一层间绝缘膜；
(e)藉由一双重金属镶嵌制造工艺来蚀刻该层间绝缘膜，以暴露该牺牲阻挡层，以形成一双重金属镶嵌图案；及
(f)沉积一电镀膜，以掩埋该双重金属镶嵌图案，然后执行一化学机械研磨制造工艺来形成一上方导电线，
其中，该下方导电线及该上方导电线为铜导电线。
2.如权利要求1所述的方法，进一步包括在该步骤(c)之前的步骤，其对下方导电线的一上方部分执行一表面处理工艺，藉以活化形成有牺牲阻挡层的该下方导电线。
3.如权利要求2所述的方法，其中该表面处理制造工艺使用H2或SiH4气体来执行，其温度在250到400℃。
4.如权利要求2所述的方法，其中该表面处理及选择性成长制造工艺是在相同处理室内的原处来执行。
5.如权利要求1所述的方法，其中该选择性成长制造工艺使用一化学气相沉积来执行。
6.如权利要求1所述的方法，其中该牺牲阻挡层使用钨来形成。
7.如权利要求1所述的方法，进一步包括在该步骤(e)之后的步骤，对于该牺牲阻挡层执行一氩溅射制造工艺，从而该牺牲阻挡层的一部分被腐蚀，然后该腐蚀掉的牺牲阻挡层的材料重新被沉积在该双重金属镶嵌图案的内侧壁上。
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JP2001284449A (ja) * 2000-03-31 2001-10-12 Sony Corp 半導体装置の製造方法

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CN1466191A (zh) 2004-01-07
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