CN1278365A - 具有高密度输入/输出数量的集成器件的电接口 - Google Patents
具有高密度输入/输出数量的集成器件的电接口 Download PDFInfo
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Abstract
一种用于电互连两个集成电路器件的装置和方法包括面对面的安装两个器件。例如把第一器件安装到基底或引线结构。第一器件包括优选地沿一边排列的多重电气/物理安装结构。安装结构提供了电互连和物理安装。第二器件包括相应的多重安装结构,该结构构成了在第一器件上的安装结构的镜象。在第二器件上的安装结构也沿着它的一边排列使得一旦安装结构以面对面关系放在一起,第二器件能悬离第一器件的边。在特定环境下,把虚拟块安装到邻近第一器件的基底上,作为第二器件的支杆或支撑。安装结构能互相充分靠近使用于I/O的表面积最小。另一套电互连结构在与安装结构相对边缘的第二器件的表面上形成。使用传统技术例如载带自动键合来形成这些气互连结构。
Description
本发明涉及制作到集成电路器件的电连接。具体地讲,本发明涉及利用反型接口(inverted interface)集成电路制作到集成电路的大量电连接。
与制作集成电路一样重要的是向集成电路提供电信号并从集成电路接收电信号的能力。通常,集成电路管芯具有相对较大的外露金属面积,称为键合焊盘,该电接口就是通过该区域实现的。通常这些金属区域是由铝或铝合金制作的,例如5平方密耳(mil)。
在商业上,这种电接口是利用几种众知技术实现的。一种这样的众知技术通常称为引线键合。完成的管芯安装到与封装集成在一起的引线框架上,例如双列直插式封装(DIP),网格插针阵列封装(PGA),或其它同样众知的封装。封装包括用于通过焊接、插座或其它众知的方式连接到外部电路或电路板的独立管脚或其它电接触设备。通过连接这些触点之间的薄引线,在键合焊盘和引线框架之间制作电接触。通过将引线加热或超声焊接到焊盘上,将引线连接到键合焊盘和引线框架上。不幸的是,由于键合引线的厚度和长度,键合引线将阻抗引入电信号的通路中。键合引线起电感的作用。该阻抗将噪声叠加到信号上,由此降低了包含键合引线的系统的总体工作效率。此外,由于引线的物理要求和在相邻引线之间的不期望接触的电位,间隔要求是严格的。键合焊盘位于管芯的边缘附近,以便使键合引线的路径最短。键合引线还起天线的作用。
另一种众知的技术通常是倒装芯片键合。根据倒装芯片键合,基底例如印刷电路板包括形成集成电路键合焊盘的镜像的导电焊接区。通常,键合焊盘覆以焊料层。集成电路和基底面对面地安装,焊料热熔化后,将键合焊盘和相应的焊接区连接起来。这样,键合焊盘和焊接区必要地提供了由集成电路到基底的电接触。不幸的是,在印刷电路板上的两个集成电路之间的电互连,其中每个管芯使用倒装芯片键合,都需要沿基底的信号线。例如位于印刷电路板上的这些线,将阻抗引入电信号的通路中,使信号的传输减慢,由此降低了该系统的总体工作效率。
还有人提出芯片-芯片键合技术。例如,授予Rostoker的美国专利5,399,303公开了一种利用倒装芯片管芯的多芯片半导体结构。Rostoker利用在两边均具有突起凸缘的双侧倒装芯片和在一边具有突起凸缘的单侧倒装芯片实现这种结构。双侧倒装芯片安装在基底上,单侧倒装芯片以最小的重叠跨接在双侧倒装芯片之间的间隙上。Rostoker的发明的缺点是在实现过程中有一些困难。例如,上集成电路必需安装为两个集成电路管芯之间的桥梁。这要求该组件在基底例如印刷电路板上占据相当大的表面,或者需要异常大的集成电路封装来容纳该组件。另外,上集成电路必需利用穿过集成电路体区制作导电过孔的复杂工艺技术制作。该技术复杂且实现费用高。到该组件的电连接利用例如传统的引线键合技术制作在上集成电路的背面。
还有人提出减小体积因此表面积可由多个集成电路器件所使用的技术。一种这样的技术见于授予Nicewarner Jr。的美国专利5,491,612。该技术没有涉及集成电路之间的互连数目,而是考虑多个集成电路所占据的空间体积。Nicewarner提出了集成电路的三维模块组件。芯片背对背地安装,并安装在主基底的两个面上,且位于两个副基底中的每个和主基底之间。根据设计,主基底和第一副基底之间的芯片阵列必需是主基底和第二副基底之间的芯片阵列的镜像。
还有人提出将集成电路一个接另一个堆积起来。该技术包括沿着堆积的边缘制作互连。在堆积内部,集成电路的散热将成为一个问题。
一种正在形成的技术围绕用于制作显示器的半导体微加工。用于这种显示器的器件公开在美国阵列5,311,360中,并将其全部内容在此引用作为参考。
根据’360专利的讲述,衍射光栅由如图1所示的多个反光带结构制作。多个可变形带结构100的图形以一定的间隔关系制作在基底102上。所有的带和在带之间的基底均覆以光反射材料,例如铝膜。当带处于松弛、上状态时,带100上的反射材料104表面和基底102上的反射材料表面之间设计的高度差是λ/2。如果波长为λ的光线照射到该结构上,并垂直于基底102的表面,那么来自带100表面的反射光将与来自基底102的反射光同相。这是因为照射到基底上的光线要比照射到带上的光线多传播λ/2,然后返回时又多出λ/2,总计是一个完整的波长λ。由此,当波长为λ的光束照射到其上时,该结构呈现为一个平面镜。
向带100和基底102施加适当的电压,带100可以向基底弯曲,并与基底102接触,如图2所示。带的厚度设计为λ/4。如果波长为λ的光线照射到该结构上,且垂直于基底102的表面,那么来自带100表面的的反射光将完全与来自基底102的反射光反相。这将在来自带的光线和来自基底的光线之间引起干涉,由此,基底将衍射光线。由于衍射,反射光将与基底表面垂直成θ角。
在研究了’360专利技术之后,本领域的普通技术人员可以理解,图1所示的结构可以用作显示器的单个像素。一般的显示器包含1024×1280个配置在行列阵列中的像素。利用图1所示的像素、且具有1024×1280个像素的半导体器件可以具有尺寸大约为1×1.3英寸的阵列。该器件将至少需要2310个I/O结构(1024+1280+6)。附加的6个I/O管脚用于特定的偏置。利用传统的引线键合的键合焊盘结构,制作到这种器件的连接所需的表面将超过有效显示面积的几倍。因为制作该器件的成本主要在于有效显示面积,所以这种表面积的浪费太大了,是不期望的。
为了解决这一问题,不期望将驱动器结构制作在作为有效显示面积的相同半导体基底上。这是由于两个主要原因。第一,利用传统众知的技术,在有效显示面积中制作该器件的成本高于为制作驱动器而制作电路元件的费用。第二,制作电路元件的工艺步骤与制作有效显示面积的工艺步骤不同。由此,该器件的工艺要求极其复杂。这将降低该结构的产量,由此增加了成本。鉴于这些原因,期望将驱动电子元件安置在独立的集成电路中。
与这种器件的互连既不需要导电过孔,又不需要Rostoker讲述的跨接技术。此外,该互连结构无法用堆积结构实现,因为光线将无法照射到有效显示面积的表面上。
所需的是直接提供由一个集成电路到另一个的电连接的方法和装置。
还需要的是为I/O需求极高的集成电路提供电连接的方法和装置。
还需要的是在不遮蔽集成电路表面的前提下提供电连接的方法和装置。
电连接两个集成电路器件的方法和装置包括面对面地安装两个器件。第一器件安装到例如基底或引线框架上。第一器件包括多个优选地位于一个边缘上的电子/物理安装结构。安装结构提供电连接和物理安装。第二器件包括多个相应地配置为第一器件上的安装结构的镜像的安装结构。第二器件上的安装结构沿着一个边缘配置,这样,一旦安装结构以面对面的方式放在一起,第二器件将悬离第一器件的边缘。在特定条件下,虚拟块(dummy block)可以安装到邻近第一器件的基底上,起加固或支撑第二器件的作用。在其它的特定条件下,环氧树脂封装化合物可以用来提供结构性支撑。安装结构可以相互靠得足够近,使I/O所占据的表面最小。另一组电连接结构可以制作在第二器件表面上的与安装结构相对的边缘上。利用传统技术的电连接,例如载带自动键合(TAB)或柔性连接,可以形成这些电连接结构。
图1示出来自现有技术的半导体微加工显示器件的像素结构。
图2示出处于偏置条件下的图1结构。
图3示出本发明优选实施方案的分解部分透视图。
图4示出本发明第一实施方案的侧视图。
图5示出本发明第二实施方案的侧视图。
图6示出本发明第三实施方案的侧视图。
图3表示了本发明优选实施方案的分解部分视图。第一半导体器件300大体上是平面的并包括主表面302和第二面304,集成电路器件(未示出)形成在第一半导体器件300的主表面302上。在第一半导体器件300上形成的集成电路可以是任意电路类型,但最好是半导体微加工显示器件。然而,对本领域的研究人员来说明显的是第一集成电路器件300可以是另一种传统电路例如微处理器、控制器、PAL、PLA、动态或非易失性的内存以及类似物。
第一半导体器件300通过第二面304固定到基底306上,如点划线所表示的。基底可以是任意方便的形式例如印刷电路板、陶瓷或IC封装。多重电气/物理安装结构形成在半导体器件300的主表面的一边附近。安装结构308最好使用传统半导体工艺技术由金属形成。安装结构308使用导电线(金属的或搀杂半导体)电连接到集成电路(未示出)。安装结构308能由铝或铝合金方便的形成。其它金属也可使用。
第二半导体器件310大体上是平面的并包括主表面312和第二面314,集成电路器件(未示出)形成在第二半导体器件300的主表面312上。在第二半导体器件300上形成的集成电路可以是任意电路类型,但最好是半导体微加工显示器件。然而,对本领域的研究人员来说明显的是第二集成电路器件310可以是另一种传统电路例如微处理器、控制器、PAL、PLA、动态或非易失性的内存以及类似物。
把第二半导体器件310的主表面312固定到第一半导体器件300的主表面302上,如点折线所表示的。容易看到第二半导体器件310以悬挂的方式悬出第一半导体器件300的边缘。这限制了第一半导体器件300的主表面302被形成到半导体器件300上集成电路的电连接而使用的数量。因为这里描述的技术,安装结构308的尺寸在一边上能达到50微米那么小。在相邻安装结构308之间的间隔能限制到50微米。
多重电气/物理安装结构318形成在半导体器件310的主表面312上的一边附近。安装结构318和沿着它们各自的引线的第二半导体器件310的部分是看不见的,如虚线表示的指出这些结构。安装结构318最好使用传统半导体工艺技术由金属形成。安装结构318使用导电线(金属的或搀杂半导体的)电连接到集成电路(未示出)。安装结构318可由金或可焊接的合金方便的形成。其它金属也可使用。
形成在第二半导体器件310上的安装结构318构成了相对于形成在第一半导体器件300上的安装结构308的镜象。这样,当第一半导体器件300和第二半导体器件310面对面连接时,安装结构308和318将电气地和物理地连接到一起。
图4表示了图3结构的侧视图。其中使用同样的参考数字用于指示同样的结构,以避免在外部细节上模糊本发明。注意第一半导体器件300的大部分是暴露的。这对于本发明的优选是理想的,其中集成电路是半导体微加工显示器件。在这样的环境下,基本上把集成电路暴露以接收和反射或衍射光。
除了上面相对图3讨论的结构因素,图4也表示从其它系统到第二半导体器件310的电连接。第二多重安装结构310形成在第二半导体器件310的主表面312上。安装结构最好位于安装结构318的相对面的一边上。如示出的,第二多重安装结构320的尺寸和间隔不必与安装结构318相同。柔性带连接322包括一套相应的构成相对安装结构320镜象的安装结构324。柔性带连接322以传统的方法连接到第二半导体器件310上。
形成图3和4结构的工艺在下面。第一和第二半导体器件300和310各自使用已知的和在别处详细描述的工艺步骤形成。安装结构308或安装结构318或两者包括安装物质例如焊料。一旦完成了,第一半导体器件300将安装到基底306上。柔性带连接322各自安装到第二半导体器件310上。一旦形成了这两种子组件,具有柔性带连接322的第二半导体器件310将连到第一半导体器件300。安装物质通过热或超声熔化以电气和物理地连接安装结构308和318。
在一定环境下,可以断定已连接的安装结构308和318的强度不足以支撑第二半导体器件310。在这样的环境下,使用了支撑结构330,如图5中示出的。支撑结构330在邻近相对第二半导体器件310的第一半导体器件300的边缘安装。支撑结构330可以由虚拟半导体材料块形成或由例如第一半导体器件300的有缺陷/非功能性器件形成。希望支撑结构330的高度接近第一半导体器件300的高度。把粘接材料332放在支撑结构330的上表面以适当的支撑第二半导体器件310。粘接剂最好由压缩材料形成以便与理想的高度一致以支撑第二半导体器件310。
图5中认为连接安装结构308和318的强度不足以适当的支撑第二半导体器件310,作为图5示出的结构的可选方案,如图6中所示使用了嵌铸化合物340。根据这样化合物的优选方案,使用了环氧嵌铸化合物。在这样的环境下,使用的支撑结构330如图5所示。支撑结构330在邻近相应安装第二半导体器件310的第一半导体器件300的边缘安装。在使用嵌铸化合物之前,把电连接322连接到第二半导体器件310上。嵌铸化合物340限制在第二半导体器件310下的区域,并能向上延展和超过第二半导体器件310,如在参考数字340’或之间所示的。因为本发明的优选方案用于第一半导体器件300用于反射光的应用,在这样的应用中重要的是嵌铸化合物340和/或340’没有覆盖第一半导体器件300。
依照包括细节的特定方案描述了本发明,以使发明的意义和操作的原理容易理解。这里参考特定方案和细节,其中不限于附加的权利要求的范围。对本领域的技术人员来说是明显的,在不偏离发明的宗旨和范围下在所选的方案中可以进行修订。对在本领域的技术人员来说是明显的,本发明的器件可以用几种不同的方法实现,上面公布的装置仅仅是本发明优选方案的图示,决不是限制。例如在发明的范围内改变这里公布的不同元件的材料和结构。
Claims (21)
1.一种从电气和结构上把两个集成电路连接到一起的方法,包括步骤:
a.提供具有第一面和第二面的第一平面半导体基底,具有在第一面上形成的第一集成电路和具有沿着第一面的第一边排列的多个第一集成电路电接触;
b.提供具有第三面和第四面的第二平面半导体基底,具有在第三面上形成的第二集成电路和具有沿着第三面的第二边排列的多个第二集成电路电接触,第三面具有相对于第二边的第三边;和
c.把第一集成电路电接触与第二集成电路电接触以面对面关系并列放置,使第一平面半导体基底仅仅在第一和第二集成电路电接触的区域覆盖第二平面基底,但是基本不覆盖其他区域,使得第二边基本来得到支撑。
2.依照权利要求1的方法,其中第一集成电路包括一个微加工显示器件的象素结构和其中第二集成电路包括形成在第三面上的用于连接和控制第一集成电路的驱动电路。
3.依照权利要求1的方法,进一步包括安装第一平面基底的第二面到第三平面基底的步骤。
4.依照权利要求1的方法,其中多个第三集成电路电接触沿第二平面基底的第三边排列用以连接柔性带结构。
5.依照权利要求1的方法,其中多个第一和第二电接触的每一个相互充分接近排列使得输入/输出电路使用的表面积最小。
6.依照权利要求1的方法,进一步包括提供在第二平面基底下物理连接的非导电支撑结构,用于适当支撑第二平面基底。
7.依照权利要求6的方法,其中非导电支撑结构由半导体材料块形成。
8.依照权利要求6的方法,其中非导电支撑结构由嵌铸化合物形成。
9.依照权利要求8的方法,其中嵌铸化合物是环氧嵌铸化合物。
10.一个电系统,包括:
a.具有第一主表面的第一平面基底,具有形成在第一主表面上第一集成电路,和具有与第一主表面相对的副表面,其中沿着第一主表面的第一边排列多个第一集成电路电接触;
b.具有第二主表面的第二平面基底,具有形成在第二主表面上第二集成电路,第二主表面具有与第二边相对的第三边,其中沿着第二主表面的第二边排列多个第二集成电路电接触;
c.用于把多个第一集成电路电接触以面对面的关系与多个第二集成电路电接触并列排列的电接口,使得第一平面基底仅仅在第一和第二集成电路电接触的区域覆盖第二集成电路,但在其他区域基本不覆盖,使得第三边基本未得到支撑。
11.依照权利要求10的电系统,其中第一集成电路包括多个反光带结构和其中第二集成电路包括连接和控制第一集成电路的驱动电路。
12.依照权利要求10的电系统,进一步包括第三平面基底,其中安装第一副表面到第三平面基底上。
13.依照权利要求10的电系统,进一步包括沿第三边排列用于连接柔性带结构的多个第三集成电路电接触。
14.依照权利要求10的电系统,其中把多个第一和第二集成电路电接触互相充分近的放置使输入/输出电路使用的表面积最小。
15.依照权利要求10的电系统,进一步包括在第二平面基底下连接和安装的不导电支撑结构,用于适当支撑第二平面基底。
16.悬臂倒装-芯片组件,用于暴露形成在半导体基底表面上的多重反光带结构和用于连接多重反光结构到驱动电路,其中多重反光带结构由驱动电路控制,悬臂倒装-芯片组件包括:
a.具有第一表面的第一平面基底,在第一表面上形成了包括多重反光带结构的电路元件,其中沿着第一主表面的第一边排列多个第一集成电路电接触并连接到第一电路元件;和
b.具有第二表面的第二平面基底,在第二表面上形成了包括驱动电路的第二电路元件,第二主表面具有与第二边相对的第三边,其中沿着第二主表面的第二边排列多个第二集成电路电接触并以面对面的关系连接到多个第一集成电路电接触,使得第二平面基底在多个第一和第二集成电路电接触的区域部分覆盖第二集成电路,但是在其他区域基本不覆盖多重反光带结构,使得多重反光带结构被暴露出来以接收、反射和衍射光。
17.依照权利要求16的悬臂倒装-芯片组件,进一步包括沿第二平面基底的第三边排列的多个第三集成电路电接触,用于连接柔性带结构和用于制作与其它集成电路的外部连接。
18.依照权利要求16的悬臂倒装-芯片组件,进一步包括在第二平面基底下连接和安装的不导电支撑结构,用于适当支撑第二平面基底。
19.依照权利要求16的悬臂倒装-芯片组件,其中不导电支撑结构由半导体材料块形成。
20.依照权利要求19的悬臂倒装-芯片组件,其中不导电支撑结构由嵌铸化合物形成。
21.依照权利要求20的悬臂倒装-芯片组件,其中嵌铸化合物使环氧嵌铸化合物。
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-
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-
1998
- 1998-06-23 AU AU79879/98A patent/AU7987998A/en not_active Abandoned
- 1998-06-23 KR KR1020007002223A patent/KR20010023575A/ko not_active Application Discontinuation
- 1998-06-23 CN CN98810695A patent/CN1278365A/zh active Pending
- 1998-06-23 JP JP2000509117A patent/JP2001515276A/ja active Pending
- 1998-06-23 WO PCT/US1998/013220 patent/WO1999012208A1/en not_active Application Discontinuation
- 1998-06-23 EP EP98930504A patent/EP1021834A1/en not_active Withdrawn
-
2000
- 2000-02-08 US US09/500,118 patent/US6452260B1/en not_active Expired - Lifetime
- 2000-03-01 NO NO20001038A patent/NO20001038D0/no not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100416807C (zh) * | 2004-10-20 | 2008-09-03 | 力晶半导体股份有限公司 | 半导体封装结构及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
WO1999012208A1 (en) | 1999-03-11 |
EP1021834A1 (en) | 2000-07-26 |
NO20001038L (no) | 2000-03-01 |
US6452260B1 (en) | 2002-09-17 |
NO20001038D0 (no) | 2000-03-01 |
US6096576A (en) | 2000-08-01 |
AU7987998A (en) | 1999-03-22 |
KR20010023575A (ko) | 2001-03-26 |
JP2001515276A (ja) | 2001-09-18 |
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