CN1289147A - 树脂封装的半导体器件 - Google Patents

树脂封装的半导体器件 Download PDF

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Publication number
CN1289147A
CN1289147A CN00124859A CN00124859A CN1289147A CN 1289147 A CN1289147 A CN 1289147A CN 00124859 A CN00124859 A CN 00124859A CN 00124859 A CN00124859 A CN 00124859A CN 1289147 A CN1289147 A CN 1289147A
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China
Prior art keywords
metal interconnected
semiconductor device
semiconductor chip
metallic plate
mold pressing
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CN00124859A
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English (en)
Inventor
市濑理彦
泷泽朋子
本多广一
方庆一郎
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NEC Corp
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NEC Corp
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Publication of CN1289147A publication Critical patent/CN1289147A/zh
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Abstract

一种形成模压封装的半导体器件的方法,包括下列步骤:在具有金属互连图形的金属板上安装半导体芯片;将半导体芯片封装于金属互连图形上;通过腐蚀去除金属板的底部,露出金属互连图形;和在金属互连图形的底部上形成外部端子。该方法可减小半导体器件的厚度以及平面尺寸。

Description

树脂封装的半导体器件
本发明涉及树脂封装的半导体器件，特别涉及适于栅格焊球阵列(BGA:ball-grid-array)半导体器件的树脂封装的半导体器件。本发明还涉及制造这种半导体器件的方法。
为了减小半导体器件的尺寸，近来已越来越多地使用BGA半导体器件。图1表示常规BGA半导体器件的结构，其中半导体芯片31被安装于插入(interposer)衬底32中心区域，并将半导体芯片31的底部表面固定并粘附于插入衬底32上。插入衬底32由诸如聚酰亚胺、玻璃环氧树脂、BT树脂之类的有机绝缘衬底构成，并在其上设置由例如铜构成的金属化互连图形34。
插入衬底32在其外周边附近(即在安装半导体芯片31的区域外部)具有多个键合焊盘34。键合焊盘34的内侧35被称为缝合(stitch)区域并用于与键合引线40连接，而键合焊盘34的外侧36被称为焊区(land area)，在该焊区上形成焊球38。插入衬底32的有机绝缘体37具有用于焊区36的开口，在焊区36的底部表面上形成焊球38。焊球38用作供最终用户在印刷电路板上安装半导体器件用的外部端子。
如以下所述那样进行在插入衬底32上安装半导体芯片31。首先，从多喷嘴涂敷器将规定量的粘合剂33滴落在插入衬底32的预定位置上，然后在其上安装半导体芯片31，通过加热使粘合剂33固化，将半导体芯片31固定于插入衬底32上。接着，使用由Au和Cu制备的键合引线40，用布线键合技术将芯片铝电极39和键合焊盘34的缝合区域35电连接在一起。然后，使用环氧树脂为其主要成份的模压树脂41，用传递模压技术将插入衬底32的顶部表面与半导体芯片31一起封装，由此保护半导体芯片31不被机械损伤和渗入湿气。
随后，在插入衬底32上的键合焊盘34的焊区36的底部表面上形成构成外部端子的焊球38。在该步骤中，预先将焊剂(flux)涂敷于焊区36上，接着将焊球38放在焊区36上，随后使焊球38热回流，从而形成外部端子38。外部端子38由例如包含作为主要成分的锡和铅的焊料制成。
在如上所述的常规BGA半导体器件中，包括有机绝缘体和金属互连图形的两层插入衬底结构防碍具有插入衬底的BGA半导体器件的厚度减小。
专利公开JP-A-2-240940、JP-A-10-116935和JP-A-11-195733披露了通过抛光由树脂构成的插入衬底的底部表面，来减小半导体器件厚度的技术。
在所披露的技术中，存在一个缺陷，即允许形成含有较高杂质的金属互连层的电解镀敷技术难以在树脂插入衬底上使用。虽然有通过在树脂衬底上设置电极膜从而在树脂衬底上可使用电解镀敷的技术，但电极膜必须延伸到树脂衬底的外周边，并由此会在不需要金属互连图形的外周边形成金属互连图形。
此外，在常规半导体器件中，在确定用于键合引线的缝合区域布局之后，在缝合区域外相应地确定用于键合焊盘的焊区(land)的位置。这对外部端子的设置强加了一大限制，对其上安装半导体器件的电子设备或电子电子零部件的平面尺寸的减小造成障碍。
特别是，随着近年来电子设备和电子零部件尺寸的减小，也要求减小半导体器件中外部端子的间距。在这方面，尽管由于光刻技术的发展在金属互连图形中键合焊盘的间距减小已达到某一程度，但由于形成焊球需要较大的空间，因而还没有成功地实现外部端子间距的减小。
因此，本发明的目的在于，通过改进常规BGA半导体器件的结构，减小其总尺寸，在预定位置形成具有良好连接能力的金属互连图形，来解决上述问题、减小成本和BGA半导体器件的尺寸。
本发明的第一方面提供一种半导体器件，该半导体器件包括：其上具有芯片电极的半导体芯片；金属互连图形，其顶部表面与芯片电极连接并且支撑半导体芯片，金属互连图形的至少顶部表面由电解镀敷技术形成；具有通孔的绝缘膜，其覆盖金属互连图形底部表面；形成在通孔中金属互连图形的底部表面上的多个外部端子；以及模压树脂，其将半导体芯片封装于金属互连图形和绝缘膜的顶部表面上。
按照本发明的半导体器件，使用其中在半导体芯片的底部表面上仅形成薄绝缘膜和电解镀敷的互连图形的结构，与具有插入衬底的常规半导体器件相比，可减小半导体器件的总厚度。
此外，电解镀敷的互连图形的可靠性得到了改进，从而对于其上配置半导体器件的电子设备或电子零部件来说，可提高质量和减小尺寸以及降低成本。
本发明的第二方面提供一种形成半导体器件的方法，该方法包括下列各步骤：形成具有金属板和在金属板的顶部表面上形成的金属互连图形的框架衬底；在该互连图形上安装半导体芯片；用模压树脂将半导体芯片封装于框架衬底上；和去除金属板的至少一部分底部表面，露出金属互连图形的至少一部分。
按照本发明的方法，在用模压树脂封装半导体芯片之后去除框架衬底的金属板以露出互连图形的工艺方法，可确保封装前半导体器件的良好刚性和减小封装之后半导体器件的总厚度。
图1是具有插入衬底的常规BGA半导体器件的剖视图。
图2是本发明实施例的半导体器件的剖视图。
图3A至3D是图2所示框架衬底的剖面图，展示其制造方法的连续步骤。
图4A至4D是图2所示框架衬底的剖面图，展示其另一种制造方法的连续步骤。
图5A至5G是图1所示半导体器件的剖视图，展示按照本发明第一实施例的制造方法的连续步骤。
图6A至6G是半导体器件的剖视图，展示按照本发明第二实施例的制造方法的连续步骤。
图7A至7F是半导体器件的剖视图，展示按照本发明第三实施例的制造方法的连续步骤。
图8A至8F是半导体器件的剖视图，展示按照本发明第四实施例的制造方法的连续步骤。
图9A至9F是半导体器件的剖视图，展示按照本发明第五实施例的制造方法的连续步骤。
图10A至10F是半导体器件的剖视图，展示按照本发明第六实施例的制造方法的连续步骤。
图11A至11D是半导体器件的剖视图，展示按照本发明第七实施例的制造方法的连续步骤。
图12A至12D是半导体器件的剖视图，展示按照本发明第八实施例的制造方法的连续步骤。
图13是按照本发明另一实施例的半导体器件的剖视图。
图14是按照本发明另一实施例的半导体器件的剖视图。
图15是按照本发明另一实施例的半导体器件的剖视图。
下面，参照附图更具体地描述本发明，其中，类似的结构元件用在一定程度上类似的参考标号来表示。
参照图2，按照本发明实施例的半导体器件包括使用模压树脂17用传递模压技术封装的半导体芯片15。利用绝缘粘合层20，将半导体芯片15的底部固定于金属膜图形14上的方式，将半导体芯片15固定于金属膜图形14上，或将管芯(die)固定于其中心区域。
形成于半导体芯片15上的各芯片电极26连接到设置于半导体芯片15外侧的金属膜图形14的缝合区域。多个焊区图形13设置于金属膜图形14的底部表面上。通过构图金属板，形成焊区图形13，在各焊区图形13的底部上形成焊球18。在除焊区图形13之外的半导体器件的整个底部表面上进行涂敷，形成绝缘粘合层19。使用以金属互连图形14支撑半导体芯片15的结构，可明显地减小最终半导体器件的总厚度。
在另一个实施例中，可省略焊区图形13，而在金属互连图形14底部上直接设置焊球18，由此还可进一步减小最终半导体器件的总厚度。
在半导体芯片15正下方的金属互连图形14的内侧上设置一些焊球(第一焊球)18，而在半导体芯片15外部的金属互连图形14的外侧上设置另外的焊球(第二焊球)18，这可在半导体器件的底部表面上观察到。
第一焊球18和第二焊球18彼此交替地设置。第一焊球18设置在半导体芯片15的外周边正下方。第二焊球18设置在与键合引线16连接的缝合区域正下方。第一焊球18和第二焊球18的交替排列允许焊球18有更小的间距，而不会彼此干扰。
图3A至3D表示形成用于制造图2的半导体器件的框架衬底的工艺方法。图3A中，首先制备金属板11，通过涂敷方式在其上形成光致抗蚀剂膜12，然后对其进行构图，形成相对于预定互连图形为负的负光致抗蚀剂图形12，如图3B所示。然后如图3C所示，用镀敷技术在金属板11的裸露表面上形成金属互连图形14，随后去除负光致抗蚀剂图形12，如图3D所示，获得在金属板11上形成金属互连图形14的框架衬底。
图4A至4D表示形成用于制造图2的半导体器件的框架衬底的另一个工艺方法。图4A中，首先制备金属板11，随后在其上形成相对于预定互连图形为正的正光致抗蚀剂膜12。然后，用正光致抗蚀剂膜12作为腐蚀掩模，对金属板11进行腐蚀，如图4C所示，随后从金属板11去除正光致抗蚀剂膜12。这样，获得框架衬底，其中在金属板11的顶部表面上形成作为金属互连图形的焊区图形14。
图5A至5G表示本发明第一实施例的制造半导体器件的制造工艺方法。在图5A中，用例如图3A至3D所示的工艺方法制备框架衬底(或可称为临时插入衬底)，其中在金属板11上形成金属图形14。如图5B所示，将底部涂敷粘合剂20的半导体芯片15安装到框架衬底上，使半导体芯片15的外周边放置在框架衬底的金属图形14的内侧。随后，利用键合引线16，将半导体芯片15上的芯片电极26电连接到设置于金属图形147外侧的缝合区域上，如图5C所示，然后使用模压树脂17，用传递模压技术，将半导体芯片15封装在框架衬底的顶部表面上。
然后，如图5E所示，利用湿式腐蚀或等离子体腐蚀，去除底部表面的框架衬底的金属板11，在金属互连图形14的底部表面上保留焊区图形13。在金属互连图形14的外侧或内侧可容易地形成焊区图形13，从而可改进用于焊区图形13定位的设计选择。
在构图金属板11之后，将绝缘粘合剂涂敷于已构图的表面上，形成粘合层19，如图5F所示，焊区图形13穿透该粘合层19。然后，在各焊区图形13上形成焊球18，获得如图5G所示的结构。
在本实施例中，焊球18交替地设置于金属图形14的内侧和外侧。在另一个实施例中，焊球18可按棋盘格形式图形设置在底部表面上。该结构允许把外部端子设置在半导体器件基本上整个底部的区域中，从而减小半导体器件的平面尺寸。
在以上的工艺方法中，涂敷绝缘粘合剂19和形成焊球18的顺序可以与所述顺序相反。此外，可省略焊球18，利用另一种已知技术把电子设备或电子零部件的端子直接安装焊区图形13上。
在以上工艺方法的变形例中，可用CMP工艺方法抛光金属板11而不留下焊区图形13。在这种情况下，焊球18可直接形成在金属互连图形14的底部表面上。
图6A至6G以连续方式表示本发明第二实施例的制造半导体器件的另一个工艺方法。该工艺方法包括形成框架衬底的步骤。在图6A中，通过涂敷方式在金属板11上形成绝缘粘合层21，随后进行构图，如图6B所示，在粘合层21上形成开口22。在将要放置半导体芯片的外周边之下设置一行用于接收焊球的开口22，在其上将要安装半导体芯片的区域外设置另一行开口22。按交错排列的方式设置两行开口22。
此后，如图6C所示，将金属膜23粘附于绝缘粘合层21上，如图6D所示，随后构图金属膜23，在其中形成中心开口24并由此形成金属互连图形。
然后，在中心开口22中涂敷绝缘粘合层25，和在金属互连图形23上放置底部已涂敷有类似的绝缘粘合剂25的半导体芯片15，以便半导体芯片15的中心与开口22的中心对准。在固化绝缘粘合剂25之后，如图6E所示，利用键合引线16，将半导体芯片15上的芯片电极26电连接到金属互连图形23上。
然后如图6F所示，使用模压树脂17，用传递模压技术，把半导体芯片15封装在金属互连图形23和绝缘膜11的顶部表面上。然后，通过腐蚀，例如使用腐蚀剂的化学腐蚀、等离子体腐蚀、使用研磨剂的化学机械抛光(CMP)等，去除金属板11。并且，如图6G所示，通过各开口22在金属互连图形23的底部上形成焊球18。焊球18交替排列或交错地设置于金属互连图形23的内侧和外侧。
在以上的实施例中，与第一实施例相比，可更容易地通过开口22形成焊球18。此外，在去除金属板11之后省去了形成绝缘粘合层的步骤减少了制造步骤数量。应该指出，在本发明该实施例中焊球18的排列仅仅是示例，可对其进行修改。
图7A至7G连续地表示本发明第三实施例的制造半导体器件的方法。在图7A中，对金属板或Cu板51的顶部表面进行腐蚀，形成互连图形52，该图形52包括用作支撑半导体芯片的支撑部件的图形部分。该图形部分位于Cu板51的中心区域。
随后，如图7B所示，在Cu板51顶部在中心图形部分涂敷绝缘粘合剂53，随后在其上安装将被粘接的半导体芯片54。如图7C所示，利用键合引线56，将半导体芯片54上的芯片电极55连接到互连图形52上。随后，如图7D所示，使用模压树脂57实施传递模压工艺处理，把半导体芯片54和键合引线56封装在Cu板51的顶部上。
此后，如图7E所示，对Cu板51底部表面进行抛光，去除不是互连图形52的Cu板部分。如图7F所示，然后将绝缘板58粘接到互连图形52的底部上，接着在互连图形52上形成金属凸点59，金属凸点59在通孔处穿透绝缘板58。金属凸点59位于半导体芯片54的外部和半导体芯片54的周边正下方。
在以上的实施例中，由Cu板51的顶部直接形成互连图形52。在另一个实施例中，利用下列步骤可形成互连图形：在金属板上形成用于互连图形的具有正图形的凹槽，利用电解镀敷技术，用金属镀敷膜填充该凹槽。随后通过抛光和有选择地湿式腐蚀，去除金属板的底部。
图8A至8F连续地表示本发明第四实施例的制造半导体器件的方法。该实施例与第三实施例相同，只是在本实施例中，仅使用金属图形52的中心部分来支撑半导体芯片，把金属图形52的周边部分用作外部电极，并且为了保证抛光之后的机械强度，要使其厚度稍微厚一些。金属图形52的周边部分用机械方法构成，并且为了在制造的最后步骤中在其上形成绝缘膜60，要进行涂敷。该周边部分被用作外部引线。
图9A至9F连续地表示本发明第五实施例的制造半导体器件的方法。在图9A中，通过腐蚀在金属板51上形成互连图形52。在金属板51上安装具有面朝下结构的半导体芯片54，如图9B所示，使半导体芯片54上的芯片电极55与互连图形52接触。在如图9C所示利用模压树脂57把半导体芯片54封装在金属板51上之后，利用机械研磨，如图9D所示，去除模压树脂57的顶部以及半导体芯片54的顶部。如图9E所示，还利用机械研磨去除金属板51的底部，保留互连图形52，然后，如图9F所示，在互连图形52的底部上粘接绝缘片58亦在其上形成金属凸点59。
图10A至10F以连续的方式展示本发明第六实施例的制造半导体器件的方法。该实施例与第五实施例相同，只是在本实施例中，与第四实施例类似地，将互连图形52用作外部端子引线。
图11A至11D表示本发明第七实施例的制造半导体器件的方法。该实施例与第五实施例相同，只是在本实施例中，在半导体芯片54的芯片电极55上设置用于与金属板51上的互连图形52连接的金属凸点61。
图12A至12D连续地表示本发明第八实施例的制造半导体器件的方法。该实施例与第六实施例相同，只是在本实施例中，在金属板51的中心形成注入孔62。在形成互连图形52之前或之后形成注入孔62，然后利用注入孔62注入模压树脂。
参照图13，按照本发明再一实施例的半导体器件包括安装于互连图形52顶部上且用普通模压树脂57A封装的第一半导体芯片54A和第二半导体芯片54B。此外，第三半导体芯片54C与第一半导体芯片54A相对地安装于互连图形52的底部上。用另一模压树脂57B封装第三半导体芯片54C。与半导体芯片54C类似，与第二半导体芯片54B相对地安装第四半导体芯片54D，并且用另一模压树脂57C进行封装。
在以上的各实施例中，通过腐蚀金属板51的顶部，直接在金属板51上形成互连图形52。在利用腐蚀去除金属板51底部的步骤中，可能会发生过腐蚀，还可能去除金属互连图形52。这样，对于去除金属板51的腐蚀步骤来说，最好是用不同的金属分别构成金属互连图形52和金属板51。在这种情况下，用湿式腐蚀步骤可有选择地从金属互连图形52去除金属板51，在另一个实施例中，对于用相同金属构成的金属板51和金属互连图形52来说，用添加剂添加入金属板51和金属互连图形52中，从而使它们在共用腐蚀剂中具有不同的腐蚀率。
参照图14，按照本发明又一实施例的半导体器件包括金属板51，其底部层51a由第一金属构成，而其顶部层51b由第二金属构成。金属互连图形52也由第一金属构成。可用不同的腐蚀剂来腐蚀第一金属和第二金属。在用第一腐蚀剂腐蚀底部层51a之后，用第二腐蚀剂从金属互连图形52有选择地腐蚀底部层。金属互连图形52在其底部可具有用于增强刚度的另一金属膜。
参照图15，对图14的实施例进行改型的半导体器件包括：由第一金属构成的单个金属板51、和包括由第二金属构成的薄底部层52a及由第三金属构成的厚顶部层52b的金属互连图形52。例如用电解镀敷技术形成第二和第三金属。从所获得膜的较低成本和较高杂质来看，电解镀敷技术优于无电镀敷技术。较高的杂质提供较好的连接能力。
图15中，通过化学腐蚀、物理(化学机械)抛光、机械研磨、机械剥离等可去除金属板51。机械剥离与具有不同热膨胀系数或不同熔点的不同金属的配置有关。
在以上各实施例中，例如可由Cu、Ni或Fe构成金属板或金属层。粘合剂或模压树脂最好包括可热固化的环氧树脂作为其主要成份。作为外部端子，可使用包括Sn和Pb作为其主要成份的焊球。
如果用电解镀敷技术形成金属互连图形，那么在本发明实施例中采用的框架衬底具有优于常规插入衬底的优点，详述如下。
用电解镀敷技术形成的金属互连图形通常具有较高的杂质和可实现较高的连接能力。在包括树脂衬底和金属互连图形的常规插入衬底中，利用形成于树脂衬底上的电极，用电解镀敷技术形成金属互连图形。在这种情况下，电极层必须延伸到树脂衬底的外周边用以在镀敷期间供电。因而，在不需要互连图形的周边上形成金属互连图形。形成在周边上的金属互连图形在模压树脂的表面上露出，可能会进入水。这降低了绝缘性能，或侵蚀所获得的半导体器件中的金属互连图形。另一方面，可用电解镀敷技术在金属板上的预定位置形成本发明的金属互连图形。这可防止常规插入衬底中出现的劣化或侵蚀。
由于仅仅以示例的方式描述了以上的实施例，因而本发明并不限于以上的实施例，本领域的技术人员由此可容易地进行各种改型或替换而不脱离本发明的范围。

Claims (20)

1．一种半导体器件，包括：
其上具有芯片电极的半导体芯片；
金属互连图形，其具有与所述芯片电极连接并且支撑所述半导体芯片的顶部表面，所述金属互连图形的至少顶部由电解镀敷技术形成；
具有通孔的绝缘膜，其覆盖所述金属互连图形底部表面；
形成在所述通孔中在所述金属互连图形的所述底部表面上的多个外部端子；以及
模压树脂，将所述半导体芯片封装于所述金属互连图形和所述绝缘膜的所述顶部表面上。
2．如权利要求1所述的半导体器件，还包括安装在所述金属互连图形的所述顶部表面上并且用所述模压树脂封装的另一个半导体芯片。
3．如权利要求1所述的半导体器件，还包括安装在所述金属互连图形的所述底部表面上的另一个半导体芯片，和将所述另一个半导体芯片封装在所述金属互连图形的所述底部表面上的另一种模压树脂。
4．如权利要求1所述的半导体器件，其中所述外部端子的至少一部分位于所述半导体芯片正下方。
5．如权利要求1所述的半导体器件，其中所述外部端子的至少一部分位于所述半导体芯片的外部。
6．如权利要求1所述的半导体器件，其中所述外部端子的一部分位于所述半导体芯片的正下方，所述外部端子的其余部分位于所述半导体芯片的外部。
7．如权利要求1所述的半导体器件，其中所述金属互连图形具有下层和顶部电解镀敷层。
8．如权利要求1所述的半导体器件，其中所述芯片电极和所述金属互连图形用键合引线进行连接。
9．如权利要求1所述的半导体器件，其中所述芯片电极和所述金属互连图形直接连接。
10．如权利要求1所述的半导体器件，其中所述金属互连图形未设置在所述模压树脂周边的附近。
11．一种形成模压封装的半导体器件的方法，包括下列步骤：
形成具有金属板和在所述金属板上形成的金属互连图形的框架衬底；
在所述金属互连图形上安装半导体芯片；
用模压树脂将所述半导体芯片封装于所述框架衬底上；以及
去除底部表面的所述金属板的至少一部分，露出所述金属互连图形的至少一部分。
12．如权利要求11所述的方法，其中用电解镀敷技术形成至少所述金属互连图形的顶部。
13．如权利要求11所述的方法，其中通过腐蚀所述金属板形成所述金属互连图形。
14．如权利要求11所述的方法，其中所述金属互连图形被粘附于所述金属板的所述顶部表面上。
15．如权利要求11所述的方法，其中所述去除步骤保留所述金属板的一部分作为焊区图形。
16．如权利要求11所述的方法，其中所述封装步骤利用形成于所述金属板中的注入孔来注入所述模压树脂。
17．如权利要求11所述的方法，还包括将绝缘膜粘附于所述金属互连图形的裸露表面上的步骤。
18．如权利要求11所述的方法，其中所述去除步骤包括化学腐蚀、化学机械抛光、机械研磨和机械剥离中的至少一种。
19．如权利要求11所述的方法，其中所述去除步骤包括与利用不同热膨胀系数或不同热熔点有关的机械剥离。
20．如权利要求11所述的方法，还包括通过研磨去除所述模压树脂和所述半导体芯片的顶部的步骤。
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Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7053476B2 (en) * 2002-09-17 2006-05-30 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040061213A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US7064426B2 (en) * 2002-09-17 2006-06-20 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US7205647B2 (en) * 2002-09-17 2007-04-17 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US7034387B2 (en) 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
TWI322448B (en) * 2002-10-08 2010-03-21 Chippac Inc Semiconductor stacked multi-package module having inverted second package
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JP2004281919A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP3680839B2 (ja) * 2003-03-18 2005-08-10 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
JP4096774B2 (ja) * 2003-03-24 2008-06-04 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法
JP2004349495A (ja) * 2003-03-25 2004-12-09 Seiko Epson Corp 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
JP2005129752A (ja) * 2003-10-24 2005-05-19 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP5197961B2 (ja) * 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
US20050258527A1 (en) 2004-05-24 2005-11-24 Chippac, Inc. Adhesive/spacer island structure for multiple die package
US8552551B2 (en) 2004-05-24 2013-10-08 Chippac, Inc. Adhesive/spacer island structure for stacking over wire bonded die
US20050269692A1 (en) * 2004-05-24 2005-12-08 Chippac, Inc Stacked semiconductor package having adhesive/spacer structure and insulation
US7253511B2 (en) * 2004-07-13 2007-08-07 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
JP2008535273A (ja) * 2005-03-31 2008-08-28 スタッツ・チップパック・リミテッド 上面および下面に露出した基板表面を有する半導体積層型パッケージアセンブリ
TWI442520B (zh) * 2005-03-31 2014-06-21 Stats Chippac Ltd 具有晶片尺寸型封裝及第二基底及在上側與下側包含暴露基底表面之半導體組件
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7298052B2 (en) * 2005-04-22 2007-11-20 Stats Chippac Ltd. Micro chip-scale-package system
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7429786B2 (en) * 2005-04-29 2008-09-30 Stats Chippac Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7582960B2 (en) * 2005-05-05 2009-09-01 Stats Chippac Ltd. Multiple chip package module including die stacked over encapsulated package
US7394148B2 (en) * 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
US7456088B2 (en) 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7768125B2 (en) 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
DE102006001767B4 (de) * 2006-01-12 2009-04-30 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben
US7750482B2 (en) 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
KR100823224B1 (ko) * 2006-08-02 2008-04-18 주식회사 심텍 마이크로 범프를 형성하는 반도체 패키지 인쇄회로기판 및 그 제조 방법
US7638863B2 (en) * 2006-08-31 2009-12-29 Semiconductor Components Industries, Llc Semiconductor package and method therefor
JP4605177B2 (ja) * 2007-04-20 2011-01-05 日立化成工業株式会社 半導体搭載基板
JP4605176B2 (ja) * 2007-04-20 2011-01-05 日立化成工業株式会社 半導体搭載基板及び半導体パッケージの製造方法並びに半導体パッケージ
TWI416688B (zh) * 2009-01-13 2013-11-21 Dainippon Printing Co Ltd A wiring device for a semiconductor device, a composite wiring member for a semiconductor device, and a resin-sealed semiconductor device
US8133759B2 (en) * 2009-04-28 2012-03-13 Macronix International Co., Ltd. Leadframe
KR101163222B1 (ko) * 2010-09-13 2012-07-06 에스케이하이닉스 주식회사 반도체 패키지 및 그 제조방법
TWI445100B (zh) 2011-05-20 2014-07-11 Subtron Technology Co Ltd 封裝結構及其製作方法
CN102376672B (zh) * 2011-11-30 2014-10-29 江苏长电科技股份有限公司 无基岛球栅阵列封装结构及其制造方法
US9324641B2 (en) 2012-03-20 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with external interconnect and method of manufacture thereof
CN103681557B (zh) * 2012-09-11 2017-12-22 恩智浦美国有限公司 半导体器件及其组装方法
US20160317068A1 (en) * 2015-04-30 2016-11-03 Verily Life Sciences Llc Electronic devices with encapsulating silicone based adhesive
US10622340B2 (en) * 2016-11-21 2020-04-14 Samsung Electronics Co., Ltd. Semiconductor package
US20200203242A1 (en) * 2018-12-19 2020-06-25 Texas Instruments Incorporated Low cost reliable fan-out fan-in chip scale package

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02151496A (ja) * 1988-12-05 1990-06-11 Matsushita Electric Ind Co Ltd 集積回路装置の製造方法
JPH02240940A (ja) 1989-03-15 1990-09-25 Matsushita Electric Ind Co Ltd 集積回路装置の製造方法
EP0582052A1 (en) * 1992-08-06 1994-02-09 Motorola, Inc. Low profile overmolded semiconductor device and method for making the same
US5592025A (en) * 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
JP3247384B2 (ja) 1994-03-18 2002-01-15 日立化成工業株式会社 半導体パッケージの製造法及び半導体パッケージ
US5637914A (en) * 1994-05-16 1997-06-10 Hitachi, Ltd. Lead frame and semiconductor device encapsulated by resin
JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
JPH08115989A (ja) * 1994-08-24 1996-05-07 Fujitsu Ltd 半導体装置及びその製造方法
JP2546192B2 (ja) * 1994-09-30 1996-10-23 日本電気株式会社 フィルムキャリア半導体装置
JPH08236586A (ja) * 1994-12-29 1996-09-13 Nitto Denko Corp 半導体装置及びその製造方法
JP3225457B2 (ja) * 1995-02-28 2001-11-05 株式会社日立製作所 半導体装置
KR0159987B1 (ko) * 1995-07-05 1998-12-01 아남산업주식회사 솔더볼을 입출력 단자로 사용하는 볼그리드 어레이(bga) 반도체 패캐지의 열 방출구조
JP3176542B2 (ja) * 1995-10-25 2001-06-18 シャープ株式会社 半導体装置及びその製造方法
US5847455A (en) * 1995-11-07 1998-12-08 Vlsi Technology, Inc. Molded leadframe ball grid array
JP3189703B2 (ja) 1996-10-08 2001-07-16 富士通株式会社 半導体装置及びその製造方法
JPH09283925A (ja) 1996-04-16 1997-10-31 Toppan Printing Co Ltd 半導体装置及びその製造方法
US5990545A (en) * 1996-12-02 1999-11-23 3M Innovative Properties Company Chip scale ball grid array for integrated circuit package
JPH10284544A (ja) 1997-04-10 1998-10-23 Hitachi Ltd 半導体装置およびその製造方法
JP3487411B2 (ja) * 1997-10-13 2004-01-19 富士通株式会社 突起電極の形成方法
JP3521758B2 (ja) 1997-10-28 2004-04-19 セイコーエプソン株式会社 半導体装置の製造方法
TW434646B (en) * 1997-11-21 2001-05-16 Rohm Co Ltd Semiconductor device and method for making the same
JP3876953B2 (ja) * 1998-03-27 2007-02-07 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP3351355B2 (ja) * 1998-09-29 2002-11-25 株式会社デンソー 電子部品の実装構造
JP2001127246A (ja) * 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100390982C (zh) * 2004-09-06 2008-05-28 精工爱普生株式会社 半导体装置及半导体装置的制造方法
CN100442465C (zh) * 2005-09-15 2008-12-10 南茂科技股份有限公司 不具核心介电层的芯片封装体制程
CN102044444A (zh) * 2007-02-15 2011-05-04 三星电机株式会社 制造封装板的方法
CN103311222A (zh) * 2012-03-08 2013-09-18 英飞凌科技股份有限公司 半导体封装件及其形成方法
CN103311222B (zh) * 2012-03-08 2016-08-31 英飞凌科技股份有限公司 半导体封装件及其形成方法

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