CN1296642A - 射频电路模块 - Google Patents
射频电路模块 Download PDFInfo
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- CN1296642A CN1296642A CN99804934A CN99804934A CN1296642A CN 1296642 A CN1296642 A CN 1296642A CN 99804934 A CN99804934 A CN 99804934A CN 99804934 A CN99804934 A CN 99804934A CN 1296642 A CN1296642 A CN 1296642A
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Abstract
射频电路模块具备安装在第1介质电路基板1的被壁3包围的空腔4内的第1射频半导体器件19和安装在放置在壁3上的第2介质电路基板2的第2射频半导体器件29。在第1介质电路基板1上设置金属基底11,在壁3内设置埋设成以其一端电连接到金属基底11上而另一端露出的、把空腔4包围在内并配置了多个通路孔等的埋设导体13金属罩12密封粘接在第1介质电路基板1上,覆盖第2介质基板2及第2射频半导体器件29,同时在壁3的上表面处电连接多个埋设导体13。从而,能够提供在对第1及第2射频半导体器件分别进行电屏蔽的同时进行气密密封,实现小型化、高性能化的射频电路模块。金属罩是板形的,第1介质基板是高温烧结基板,第2介质基板是低温烧结基板,介质基板之间的连接可以是焊锡凸点、各向异性导电性薄片。金属基底11在空腔中露出,可以在第1介质基板上安装发送系统电路,在第2介质基板上安装接收系统电路。也可以把不需要气密密封的射频电路器件配置在金属罩的外部。
Description
技术领域
本发明涉及射频电路模块,主要涉及在VHF频段、UHF频段、微波段以及毫米波段中使用的射频电路模块。
背景技术
图11中作为现有的射频电路模块的例子示出特开平8-148800号公报中所示的射频电路模块。在图11中,31是多层的第1介质基板,32是多层的第2介质基板,33是作为连接部件的通路孔,34是作为第1射频半导体器件的射频电路元件,35是作为第2射频半导体器件的表面安装用部件,36是直流线路,37是作为接地导体的接地图形,38是为了把第1介质基板31的直流线路31a与第2介质基板32的直流线路32a连接而在第1介质基板31上设置的连接部,39是空腔。在空腔39中安装了射频电路元件34的同时,第2介质基板32配置在空腔39的上表面,第2介质基板32背面的接地图形37与空腔39周围的通路孔33相连接。另外,在第2介质基板32上安装了表面安装用部件35。在连接部38中第1介质基板31的直流线路31a与第2介质基板32的直流线路32a通过使各自的直流线路31a及32a相重合而连接。
在该图中所示的射频电路模块的结构中,通过把第2介质基板32背面的接地图形37与空腔39周围的通路孔33相连接,能够在电屏蔽空腔39的同时进行气密密封。另外,由于能够在第2介质基板32上安装表面安装用部件35,因此具有能够提高电路的安装密度的特征。
然而,现有的射频电路模块由于像以上那样构成,因此虽然能够对于安装在空腔39内的射频电路元件34进行气密密封,但是不能够对于第2介质基板32上的电路进行气密密封,因此只有分别密封安装在第2介质基板32上的表面安装用部件35。
另外,由于为了把第1介质基板31的直流线路31a与第2介质基板32的直流线路32a相连接而需要设置连接部38,因此存在电路变大且制造成本提高的问题。
本发明是了解决这样的问题而产生的,其目的在于获得能够容易地把第1介质基板及第2介质基板上的作为射频半导体器件的射频电路元件电屏蔽的同时进行气密密封,实现了小型化、高性能化的射频电路模块。
发明的公开
与本发明有关的射频电路模块具备:在上层形成了被壁围绕的空腔的多层的第1介质基板;在空腔内安装在第1介质基板上的第1射频半导体器件;在壁的上表面与第1介质基板连接,在背面具有接地导体的至少一层以上的第2介质基板;安装在第2介质基板上表面的第2射频半导体器件;以及覆盖第2介质基板及第2射频半导体器件,在壁处与第1介质基板连接,把第2射频半导体器件电屏蔽的同时气密密封第1及第2射频半导体器件的金属罩。
另外,与本发明有关的射频电路模块的特征在于:第1介质基板具有围绕第2介质基板的介质,金属罩是板形的。
进而,按照本发明,射频电路模块具备:被壁包围,在第1面上具有布线了的空腔的第1介质电路基板;安装在第1介质电路基板的空腔内的第1射频半导体器件;放置在第1介质电路基板的壁上的第2介质电路基板;安装在第2介质电路基板上的第2射频半导体器件;设置在第1介质电路基板的第2面上的金属基底;以分别以其一端电连接到金属基底,以另一端露出到第1面上并且埋设在壁内,包围空腔的方式配置的多个埋设导体;以及密封粘接到第1介质电路基板上,覆盖第2介质基板及第2射频半导体器件,在壁的上表面电连接多个埋设导体,进而分别在把第1及第2射频半导体器件电屏蔽的同时气密密封第1及第2射频半导体器件的金属罩。
另外,壁还可以具备形成包围并收容第2介质基板及第2射频半导体器件的第2空腔的延长部,可以把金属罩做成平板形的。
另外,与本发明有关的射频电路模块的特征在于,第1介质基板是高温烧结基板,第2介质基板是低温烧结基板。
另外,与本发明有关的射频电路模块的特征在于,第1介质基板与第2介质基板通过焊锡凸点连接。
另外,与本发明有关的射频电路模块的特征在于,第1介质基板与第2介质基板通过各向异性导电性薄片连接。
另外,与本发明有关的射频电路模块的特征在于,具备在金属罩的外侧安装在第1介质基板上并且不需要气密密封的射频电路器件。
另外,与本发明有关的射频电路模块的特征在于,第1介质基板具备安装射频电路器件的阶梯部。
另外,与本发明有关的射频电路模块的特征在于,第1介质基板具备金属基底,金属基底在空腔的底面上露出。
另外,与本发明有关的射频电路模块的特征在于,在第1介质基板上安装发送系统电路,在第2介质基板上安装接收系统电路。
附图的简单说明
图1是示出本发明实施形态1的射频电路模块结构的组装图。
图2是示出本发明实施形态1的射频电路模块的剖面图。
图3是示出本发明实施形态2的射频电路模块的剖面图。
图4是示出本发明实施形态3的射频电路模块的剖面图。
图5是示出本发明实施形态4的射频电路模块的剖面图。
图6是示出本发明实施形态5的射频电路模块的剖面图。
图7是示出本发明实施形态6的射频电路模块的剖面图。
图8是示出本发明实施形态7的射频电路模块的剖面图。
图9是示出本发明实施形态8的射频电路模块的剖面图。
图10是示出本发明实施形态9的射频电路模块的电路的电路结构图。
图11是示出现有的射频电路模块的剖面图。
用于实施发明的最佳形态实施形态1
图1是示出作为本发明实施形态的射频电路模块100的结构的组装图,图2是示出射频电路模块100的剖面图。
在图1及图2中,由陶瓷构成的多层介质所组成的第1介质基板1具有作为上表面的第1面和作为下表面的第2面,在第2面上设置作为导电体的平板形的金属基底11。在第1介质基板1中,通过部分地去除从中层到上层的介质把叠层的部分残留在金属基底11上,形成了作为凹洼的空腔4。在该空腔4的周围形成了第1介质基板1的作为壁的壁3,使其围绕空腔4。在该壁3中遍及全周设置从底部的金属基底11延伸到壁3的上端的多个通路孔13。
在空腔4的内部,在第1介质基板1上安装第1射频半导体器件19,通过导线10把设置在空腔4内的第1介质基板1上的直流线路17与第1射频半导体器件19电连接。在壁3的上表面,放置并且连接了在作为背面的底部上具有接地导体5的多层的第2介质基板2。在第2介质基板2上配置直流线路27,并且通过作为连接部件的通路孔8电连接第1介质基板1的直流线路17。在第2介质基板2上也安装第2射频半导体器件29,通过导线20电连接设置在第2介质基板2上的直流线路27与第2射频半导体器件29。这样,第1及第2介质基板1及2是第1及第2介质电路基板。
设置在第1介质基板1上并且覆盖第2介质基板2的是底部开口的长方形的由金属制造的板形体构成的箱体形金属罩12。金属罩12在其端部12a通过导电性粘接剂等在壁3的上表面上粘接第1介质基板1,同时与设置在第1介质基板1的壁3上而且连接到金属基底11的多个通路孔13电连接。
从而,第1及第2射频半导体器件19及29由相互电连接的金属基底11、通路孔13以及金属罩12进行电屏蔽,另外,第1及第2射频半导体器件19及29由相互气密密封的第1、第2介质基板1、2以及金属罩12密封。
另外,射频电路模块100的组装如图1所示,在安装了第1射频半导体器件19的第1介质基板1上放置并且连接安装了第2射频半导体器件29的第2介质基板2以后,把金属罩12连接到第1介质基板1上。
如以上那样构成本实施形态的射频电路模块100,由于层叠地安装了第1射频半导体器件19的第1介质基板1与安装了第2射频半导体器件29的第2介质基板,把金属罩12密封粘接在第1介质基板1的壁3的上表面,同时,通过第2介质基板2的空腔4周围的通路孔13电连接金属基底11,因此在把第1射频半导体器件19及第2射频半导体器件29电屏蔽的同时进行气密密封。实施形态2
图3是示出作为本发明其它实施形态的射频电路模块200的剖面图。以后,对与图1及2相同或者同等的部件及部位标注相同的符号,省略重复的说明。
图3的射频电路模块200与图1中所示的射频电路模块100的不同点在于:具备在第1介质基板1的壁3上延长部1a,由陶瓷构成,具有对应于通路孔13被电连接了的多个通路孔,形成包围并收容第2介质基板2及第2射频半导体器件29的第2空腔;以及金属罩112是平坦的平板形。其它的结构相同。
在壁3上,围绕第2介质基板2形成延长部1a。在延长部1a上设置金属罩112,使用导电性粘接剂等与延长部1a连接。在延长部1a的内部延伸设置着通路孔13,对金属基底11与金属罩112进行电连接。
由于如以上那样构成本实施形态的射频电路模块200,因此具有与图1及图2中所示的射频电路模块相同的优点,同时,由于金属罩112是板形的,因此可以提高金属罩112安装的可操作性。实施形态3
图4是示出作为本发明其它实施形态的射频电路模块300的剖面图。第1介质基板101和第2介质基板102的材料与图2不同。第1介质基板101是多层的高温烧结基板,热传导率高,例如把氮化铝作为基板材料。第2介质基板102是多层的低温烧结基板。所谓低温烧结基板是对于通常的基板用较低的温度烧结的,由于烧结温度低,因此作为在基板上布线的布线材料,可以使用金或铜等熔点低的材料。
这样,本实施形态的射频电路模块300除去具有与图1及2中所示的射频电路模块相同的优点以外,由于高温烧结基板的热传导率好,因此作为安装在第1介质基板101上的射频半导体器件19即使使用发热量大的器件,也能够容易地进行散热。另外,如果使用低温烧结基板作为第2介质基板102,则可以使用金或铜的布线材料作为2介质基板102的直流线路27,而由于这些布线材料的电阻率低,因此能够减小直流线路27的电阻。从而,能够抑制由于第2介质基板102的直流线路27引起的电压降。实施形态4
图5是示出作为本发明其它实施形态的射频电路模块400的剖面图。图中,在第1介质基板1与第2介质基板2之间插入了焊锡凸点118这一点与图2不同。在第1介质基板1的壁3的上表面与第2介质基板2背面的接地导体5之间插入着球形焊锡即焊锡凸点118。
这样,本实施形态的射频电路模块400除去具有与图1及2中所示的射频电路模块相同的优点以外,进而由于通过通路孔8及焊锡凸点118进行第1介质基板1的直流线路17与第2介质基板2的直流线路27的连接,以及第1介质基板1与第2介质基板2的接地导体5的连接,因此与对直流线路17与27重合的连接部进行加工的情况相比能够使射频电路模块小型化。实施形态5
图6是示出作为本发明其它实施形态的射频电路模块500的剖面图。图中,在第1介质基板1与第2介质基板2之间插入各向异性导电性薄片119这一点与图2不同。所谓各向异性导电性薄片是根据薄片材料的方向其性质不同的材料,是使得第1介质基板1与第2介质基板2相对方向的导电粒子易于移动而提高了导电率的材料。
这样,本实施形态的射频电路模块500除去具有与图5中所示的射频电路模块相同的优点以外,由于能够通过各向异性导电性薄片119进行第1介质基板1的直流线路17与第2介质基板2的直流线路27的连接,及第1介质基板1与第2介质基板2的接地导体5的连接,因此为了连接第1介质基板1与第2介质基板2不需要焊锡回流,因此在提高组装可操作性的同时,还容易进行第2介质基板2的替换作业。实施形态6
图7是示出作为本发明其它实施形态的射频电路模块600的剖面图。图中,与图2不同点在于在金属罩12外侧的第1介质基板1上配置不需要进行气密密封的片形电容器等射频电路器件120。
这样,本实施形态中的射频电路模块600除去具有与图2中所示的射频电路模块相同的优点以外,能够减小空腔4的占有面积,容易抑制不需要的波导模。即,由于在空腔4的周围具有金属基底11,通路孔13,接地导体5,因此形成近似地被金属壁包围了四个面的波导管那样的构造。从而,如果在空腔4内配置不需要气密密封的片形电容器等射频电路器件120,则由于加大空腔4的占有面积,加大该近似波导管的横向宽度,故更易于产生使频率低(波长长)的电波传输的不需要的波导模,然而,通过在金属罩12的外侧配置不需要气密密封的射频电路器件120,能够减小空腔4的占有面积,容易抑制不需要的波导模。实施形态7
图8是示出作为本发明其它实施形态的射频电路模块700的剖面图。图中,第1介质基板201的安装射频电路器件120的部位形状与图7不同。
在第1介质基板201中,在金属罩12的外侧,从中层到上层部分地去除介质,形成阶梯部201a。在该阶梯部201a的第1介质基板201的高度降低了部位上配置片形电容器等不需要气密密封的射频电路器件120。
这样,本实施形态的射频电路模块700除去具有与图7中所示的射频电路模块相同的优点以外,关于片形电容器等不需要气密密封的射频器件120由于在金属罩12的外侧,在第1介质基板201的高度降低了的部位上能够配置射频电路器件120,因此能够降低射频电路模块700的总体高度。实施形态8
图9是示出作为本发明其它实施形态的电路块800的剖面图。图中,第1介质基板301的安装射频半导体器件19的部位形状与图2不同。
从下层到上层去除第1介质基板301的一部分,使得金属基底11露出在空腔4的底面上,在空腔4内的金属基底11上安装了第1射频半导体器件19。
这样,本实施形态的射频电路模块800除去具有与图2中所示的射频电路模块相同的优点以外,由于在热导电性良好的金属基底11上安装了第1射频半导体器件19,因此能够容易地进行来自第1射频半导体器件19的散热。实施形态9
图10是示出作为本发明其它实施形态的射频电路模块的电路结构图。
图中,121是开关,122是大功率放大器,123是低噪声放大器,124是发送系统电路,125是接收系统电路,126是射频线路,127是直流线路,128是控制电路侧端子,129是天线侧端子,130是输入输出端子。
如果为了方便地说明包括该电路的射频电路模块而取图1及图2中所示的射频电路模块100为例,则把包括图10中所示的大功率放大器122、开关121的发送系统电路124安装在第1介质基板1上。把包括低噪声放大器123的接收系统电路125安装在第2介质基板2上。另外,用于控制发送系统电路124的大功率放大器122的直流线路17与用于控制接收系统电路125的低噪声放大器123的直流线路27连接,经过第2介质基板2连接到控制电路侧端子128。天线侧端子129、输入输出端子130经过第1介质基板1连接。
这样,在本实施形态的射频电路模块中,由于把发送系统电路124及接收系统电路125分别分离安装,因此能够容易地完成射频电路模块的电路结构。
产业上的可利用性
如果依据本发明 的射频电路模块,具备:在上层形成了被壁围绕的空腔的多层的第1介质基板;在空腔内安装在第1介质基板上的第1射频半导体器件;在壁的上表面与第1介质基板连接,在背面具有接地导体的至少一层以上的第2介质基板;安装在第2介质基板上表面的第2射频半导体器件;以及覆盖第2介质基板及第2射频半导体器件,在壁处与第1介质基板连接,把第2射频半导体器件电屏蔽的同时气密密封第1及第2射频半导体器件的金属罩。
另外,本发明的射频电路模块具备:被壁包围,在第1面上具有布线了的空腔的第1介质电路基板;安装在第1介质电路基板空腔内的第1射频半导体器件;放置在第1介质电路基板的壁上的第2介质电路基板;安装在第2介质电路基板上的第2射频半导体器件;设置在第1介质电路基板的第2面上的金属基底;以分别以其一端电连接到金属基底,以另一端露出到第1面上并且埋设在壁内,包围空腔的方式配置的多个埋设导体;以及密封粘接到第1介质电路基板上,覆盖第2介质基板及第2射频半导体器件,在壁的上表面电连接多个埋设导体,进而分别在对第1及第2射频半导体器件进行电屏蔽的同时气密密封第1及第2射频半导体器件的金属罩。
从而,按照本发明,能够提供可以容易地在对第1介质基板1及第2介质基板上的射频半导体器件进行电屏蔽的同时进行气密密封,实现了小型化、高性能化的射频电路模块。
另外,如果依据本发明的射频电路模块,第1介质基板具备围绕第2介质基板的介质,金属罩是板形的。或者壁具备形成包围并收容第2介质基板及第2射频半导体器件的第2空腔的延长部,金属罩是平板形的,因此将提高金属罩的安装可操作性。
另外,如果依据本发明的射频电路模块,由于第1介质基板是高温烧结基板,热传导率优良,因此能够容易地进行在第1介质基板上安装的射频半导体器件的散热。另外,由于第2介质基板是低温烧结基板,因此作为基板的布线材料能够使用低熔点而且电阻小的材料,能够抑制电压降低。
另外,如果依据本发明的射频电路模块,由于通过焊锡凸点连接第1介质基板与第2介质基板,因此能够用简单的结构进行第1介质基板与第2介质基板的连接,能够使射频电路模块进一步小型化。
另外,如果依据本发明的射频电路模块,由于使用各向异性导电性薄片连接第1介质基板与第2介质基板,因此为了连接第1介质基板与第2介质基板不需要焊锡回流,提高了组装的可操作性。另外,第2介质基板的替代作业也很容易。
另外,如果依据本发明的射频电路模块,由于把不需要气密密封的射频电路器件安装在金属罩外侧的第1介质基板上,因此能够减小空腔的占有面积,能够抑制不需要的波导模。
另外,如果依据本发明的射频电路模块,由于第1介质基板具备安装射频电路器件的阶梯部,因此能够降低射频电路模块的总体高度。
另外,如果依据本发明的射频电路模块,由于第1介质基板具备金属基底,并且金属基底露出到空腔的底面,因此能够把第1射频半导体器件直接安装在金属基底上,提高来自第1射频半导体器件的散热性。
另外,如果依据本发明的射频电路模块,由于把发送系统电路安装在第1介质基板上,把接收系统电路安装在第2介质基板上,因此容易实现射频电路模块的电路结构。
Claims (11)
1.一种射频电路模块,其特征在于,具备:
在上层形成了被壁围绕的空腔的多层的第1介质基板;
在上述空腔内安装在上述第1介质基板上的第1射频半导体器件;
在上述壁的上表面与上述第1介质基板连接,在背面具有接地导体的至少1层以上的第2介质基板;
安装在上述第2介质基板上表面的第2射频半导体器件;以及
覆盖上述第2介质基板及上述第2射频半导体器件,在上述壁的上表面处与上述第1介质基板连接,在对上述第2射频半导体器件进行电屏蔽的同时气密密封上述第1及第2射频半导体器件的金属罩。
2.如权利要求1所述的射频电路模块,其特征在于:
上述第1介质基板具有围绕上述第2介质基板的介质,上述金属罩是板形的。
3.一种射频电路模块,其特征在于,具备:
被壁包围在第1面上,具有布线了的空腔的第1介质电路基板;
安装在上述第1介质电路基板的上述空腔内的第1射频半导体器件;
放置在上述第1介质电路基板的上述壁上的第2介质电路基板;
安装在上述第2介质电路基板上的第2射频半导体器件;
设置在上述第1介质电路基板的第2面上的金属基底;
分别以其一端电连接到上述金属基底,以另一端露出到上述第1面上并且埋设在上述壁内,以包围上述空腔的方式配置的多个埋设导体;以及
密封粘接到上述第1介质电路基板上,覆盖上述第2介质基板及上述第2射频半导体器件,在上述壁的上表面电连接多个上述埋设导体,进而分别在对上述第1及第2射频半导体器件进行电屏蔽的同时气密密封上述第1及第2射频半导体器件的金属罩。
4.如权利要求1所述的射频电路模块,其特征在于:
上述壁具备形成包围并收容上述第2介质基板及上述第2射频半导体器件的第2空腔的延长部,上述金属罩是平板形的。
5.如权利要求1至4的任一项中所述的射频电路模块,其特征在于:
上述第1介质基板是高温烧结基板,上述第2介质基板是低温烧结基板。
6.如权利要求1至5的任一项中所述的射频电路模块,其特征在于:
上述第1介质基板与上述第2介质基板通过焊锡凸点连接。
7.如权利要求1至5的任一项中所述的射频电路模块,其特征在于:
上述第1介质基板与上述第2介质基板通过各向异性导电性薄片连接。
8.如权利要求1至7的任一项中所述的射频电路模块,其特征在于:
具备在上述金属罩的外侧安装到上述第1介质基板上的不需要气密密封的高频电路器件。
9.如权利要求8中所述的射频电路模块,其特征在于:
上述第1介质基板具备安装上述高频电路器件的阶梯部。
10.如权利要求1至9的任一项中所述的射频电路模块,其特征在于:
上述第1介质基板具备金属基底,上述金属基底露出在上述空腔的底面上。
11.如权利要求5或10中所述的射频电路模块,其特征在于:
在上述第1介质基板上安装发送系统电路,在第2介质基板上安装接收系统电路。
Applications Claiming Priority (2)
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JP35026598A JP3538045B2 (ja) | 1998-12-09 | 1998-12-09 | Rf回路モジュール |
JP350265/1998 | 1998-12-09 |
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CN1296642A true CN1296642A (zh) | 2001-05-23 |
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CN99804934A Pending CN1296642A (zh) | 1998-12-09 | 1999-06-17 | 射频电路模块 |
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US (1) | US6335669B1 (zh) |
EP (1) | EP1056133A1 (zh) |
JP (1) | JP3538045B2 (zh) |
KR (1) | KR20010040800A (zh) |
CN (1) | CN1296642A (zh) |
WO (1) | WO2000035015A1 (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100353552C (zh) * | 2003-10-15 | 2007-12-05 | 台湾积体电路制造股份有限公司 | 在无线频率集成电路中提供护罩用以降低噪声耦合的一种装置及方法 |
CN100372241C (zh) * | 2003-07-30 | 2008-02-27 | 奇美通讯股份有限公司 | 以多层陶瓷形成的射频收发模块 |
US7715203B2 (en) | 2003-12-30 | 2010-05-11 | Lg Electronics Inc. | RF module structure of a mobile communication terminal |
CN101800215B (zh) * | 2009-02-11 | 2012-07-04 | 日月光半导体制造股份有限公司 | 无线通讯模组封装构造 |
CN103367349A (zh) * | 2012-03-28 | 2013-10-23 | 富士通株式会社 | 堆叠模块 |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6542720B1 (en) | 1999-03-01 | 2003-04-01 | Micron Technology, Inc. | Microelectronic devices, methods of operating microelectronic devices, and methods of providing microelectronic devices |
JP3976297B2 (ja) * | 1999-09-29 | 2007-09-12 | 株式会社ルネサステクノロジ | 高周波回路モジュールおよび通信装置 |
US6631555B1 (en) * | 2000-02-08 | 2003-10-14 | Cardiac Pacemakers, Inc. | Method of thin film deposition as an active conductor |
US6360431B1 (en) * | 2000-09-29 | 2002-03-26 | Intel Corporation | Processor power delivery system |
US6462950B1 (en) * | 2000-11-29 | 2002-10-08 | Nokia Mobile Phones Ltd. | Stacked power amplifier module |
US7075112B2 (en) * | 2001-01-31 | 2006-07-11 | Gentex Corporation | High power radiation emitter device and heat dissipating package for electronic components |
JP3612031B2 (ja) * | 2001-03-29 | 2005-01-19 | Tdk株式会社 | 高周波モジュール |
US6627987B1 (en) * | 2001-06-13 | 2003-09-30 | Amkor Technology, Inc. | Ceramic semiconductor package and method for fabricating the package |
US20070133001A1 (en) * | 2001-09-12 | 2007-06-14 | Honeywell International Inc. | Laser sensor having a block ring activity |
US7015457B2 (en) * | 2002-03-18 | 2006-03-21 | Honeywell International Inc. | Spectrally tunable detector |
JP3662219B2 (ja) * | 2001-12-27 | 2005-06-22 | 三菱電機株式会社 | 積層高周波モジュール |
US7470894B2 (en) * | 2002-03-18 | 2008-12-30 | Honeywell International Inc. | Multi-substrate package assembly |
US7276798B2 (en) * | 2002-05-23 | 2007-10-02 | Honeywell International Inc. | Integral topside vacuum package |
TWM248187U (en) * | 2003-01-15 | 2004-10-21 | Abocom Sys Inc | Printed circuit board structure of RF transmission device |
US6971162B2 (en) * | 2003-05-13 | 2005-12-06 | Motorola, Inc. | Localized enhancement of multilayer substrate thickness for high Q RF components |
JP3858854B2 (ja) | 2003-06-24 | 2006-12-20 | 富士通株式会社 | 積層型半導体装置 |
JP2005026263A (ja) * | 2003-06-30 | 2005-01-27 | Nec Compound Semiconductor Devices Ltd | 混成集積回路 |
US6982879B1 (en) * | 2003-07-19 | 2006-01-03 | Intel Corporation | Apparatus to provide connection between a microelectronic device and an antenna |
US20050231922A1 (en) * | 2004-04-16 | 2005-10-20 | Jung-Chien Chang | Functional printed circuit board module with an embedded chip |
US7902534B2 (en) * | 2004-09-28 | 2011-03-08 | Honeywell International Inc. | Cavity ring down system having a common input/output port |
US7586114B2 (en) * | 2004-09-28 | 2009-09-08 | Honeywell International Inc. | Optical cavity system having an orthogonal input |
JP4822900B2 (ja) * | 2005-06-15 | 2011-11-24 | 京セラ株式会社 | 電子部品モジュール |
US7656532B2 (en) * | 2006-04-18 | 2010-02-02 | Honeywell International Inc. | Cavity ring-down spectrometer having mirror isolation |
US7649189B2 (en) * | 2006-12-04 | 2010-01-19 | Honeywell International Inc. | CRDS mirror for normal incidence fiber optic coupling |
US7444737B2 (en) * | 2006-12-07 | 2008-11-04 | The Boeing Company | Method for manufacturing an antenna |
EP1956652A1 (en) * | 2007-02-08 | 2008-08-13 | Nederlandse Organisatie voor Toegepast-Natuuurwetenschappelijk Onderzoek TNO | Sealed ball grid array package |
WO2009096542A1 (ja) * | 2008-01-30 | 2009-08-06 | Kyocera Corporation | 接続端子及びこれを用いたパッケージ並びに電子装置 |
JP5047357B2 (ja) * | 2008-05-12 | 2012-10-10 | 三菱電機株式会社 | 高周波収納ケースおよび高周波モジュール |
GB2461882B (en) * | 2008-07-15 | 2012-07-25 | Thales Holdings Uk Plc | Integrated microwave circuit |
US7663756B2 (en) * | 2008-07-21 | 2010-02-16 | Honeywell International Inc | Cavity enhanced photo acoustic gas sensor |
TWI381510B (zh) * | 2008-10-07 | 2013-01-01 | Advanced Semiconductor Eng | 具有屏蔽蓋體之晶片封裝結構 |
US7864326B2 (en) | 2008-10-30 | 2011-01-04 | Honeywell International Inc. | Compact gas sensor using high reflectance terahertz mirror and related system and method |
US8198590B2 (en) * | 2008-10-30 | 2012-06-12 | Honeywell International Inc. | High reflectance terahertz mirror and related method |
US8072056B2 (en) | 2009-06-10 | 2011-12-06 | Medtronic, Inc. | Apparatus for restricting moisture ingress |
KR101695846B1 (ko) * | 2010-03-02 | 2017-01-16 | 삼성전자 주식회사 | 적층형 반도체 패키지 |
US8437000B2 (en) | 2010-06-29 | 2013-05-07 | Honeywell International Inc. | Multiple wavelength cavity ring down gas sensor |
US8269972B2 (en) | 2010-06-29 | 2012-09-18 | Honeywell International Inc. | Beam intensity detection in a cavity ring down sensor |
US8322191B2 (en) | 2010-06-30 | 2012-12-04 | Honeywell International Inc. | Enhanced cavity for a photoacoustic gas sensor |
US8666505B2 (en) | 2010-10-26 | 2014-03-04 | Medtronic, Inc. | Wafer-scale package including power source |
US8424388B2 (en) | 2011-01-28 | 2013-04-23 | Medtronic, Inc. | Implantable capacitive pressure sensor apparatus and methods regarding same |
JP5449237B2 (ja) * | 2011-03-09 | 2014-03-19 | 古河電気工業株式会社 | 基板および基板の製造方法 |
JP5921077B2 (ja) * | 2011-03-30 | 2016-05-24 | 三菱電機株式会社 | 高周波パッケージ |
ITTO20110577A1 (it) * | 2011-06-30 | 2012-12-31 | Stmicroelectronics Malta Ltd | Incapsulamento per un sensore mems e relativo procedimento di fabbricazione |
WO2013128305A1 (en) * | 2012-03-02 | 2013-09-06 | Aselsan Elektronik Sanayi Ve Ticaret Anonim Sirketi | A microwave component package |
WO2014011808A1 (en) | 2012-07-13 | 2014-01-16 | Skyworks Solutions, Inc. | Racetrack design in radio frequency shielding applications |
JP5716972B2 (ja) | 2013-02-05 | 2015-05-13 | 株式会社デンソー | 電子部品の放熱構造およびその製造方法 |
JP6015508B2 (ja) * | 2013-03-18 | 2016-10-26 | 富士通株式会社 | 高周波モジュール |
JP2015149650A (ja) * | 2014-02-07 | 2015-08-20 | 株式会社東芝 | ミリ波帯用半導体パッケージおよびミリ波帯用半導体装置 |
JP2015149649A (ja) * | 2014-02-07 | 2015-08-20 | 株式会社東芝 | ミリ波帯用半導体パッケージおよびミリ波帯用半導体装置 |
TWM499394U (zh) * | 2014-12-19 | 2015-04-21 | Bothhand Entpr Inc | 電子裝置之封裝盒 |
WO2018044326A1 (en) * | 2016-09-02 | 2018-03-08 | Intel Corporation | An apparatus with embedded fine line space in a cavity, and a method for forming the same |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2876773B2 (ja) * | 1990-10-22 | 1999-03-31 | セイコーエプソン株式会社 | プログラム命令語長可変型計算装置及びデータ処理装置 |
JPH04219966A (ja) * | 1990-12-20 | 1992-08-11 | Fujitsu Ltd | 半導体素子 |
US5266912A (en) * | 1992-08-19 | 1993-11-30 | Micron Technology, Inc. | Inherently impedance matched multiple integrated circuit module |
JP2682477B2 (ja) | 1994-11-16 | 1997-11-26 | 日本電気株式会社 | 回路部品の実装構造 |
US5633530A (en) * | 1995-10-24 | 1997-05-27 | United Microelectronics Corporation | Multichip module having a multi-level configuration |
JPH10135406A (ja) * | 1996-11-01 | 1998-05-22 | Nec Corp | 半導体装置の実装構造 |
KR100280398B1 (ko) * | 1997-09-12 | 2001-02-01 | 김영환 | 적층형 반도체 패키지 모듈의 제조 방법 |
-
1998
- 1998-12-09 JP JP35026598A patent/JP3538045B2/ja not_active Expired - Fee Related
-
1999
- 1999-06-17 WO PCT/JP1999/003236 patent/WO2000035015A1/ja not_active Application Discontinuation
- 1999-06-17 EP EP99973352A patent/EP1056133A1/en not_active Withdrawn
- 1999-06-17 CN CN99804934A patent/CN1296642A/zh active Pending
- 1999-06-17 KR KR1020007008694A patent/KR20010040800A/ko not_active Application Discontinuation
- 1999-07-27 US US09/361,213 patent/US6335669B1/en not_active Expired - Lifetime
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Publication number | Priority date | Publication date | Assignee | Title |
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CN100353552C (zh) * | 2003-10-15 | 2007-12-05 | 台湾积体电路制造股份有限公司 | 在无线频率集成电路中提供护罩用以降低噪声耦合的一种装置及方法 |
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CN101800215B (zh) * | 2009-02-11 | 2012-07-04 | 日月光半导体制造股份有限公司 | 无线通讯模组封装构造 |
CN103367349A (zh) * | 2012-03-28 | 2013-10-23 | 富士通株式会社 | 堆叠模块 |
Also Published As
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JP3538045B2 (ja) | 2004-06-14 |
US6335669B1 (en) | 2002-01-01 |
JP2000174204A (ja) | 2000-06-23 |
EP1056133A1 (en) | 2000-11-29 |
WO2000035015A1 (fr) | 2000-06-15 |
KR20010040800A (ko) | 2001-05-15 |
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