CN1299201C - 通过响应高速缓存缺失而切换任务来提高基于高速缓存的嵌入式处理器的处理能力的方法和装置 - Google Patents
通过响应高速缓存缺失而切换任务来提高基于高速缓存的嵌入式处理器的处理能力的方法和装置 Download PDFInfo
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Abstract
提供一种用于操作包括处理器和高速缓冲存储器的嵌入式处理器系统的方法和装置。该方法包括用与第一任务相关的数据填充高速缓冲存储器中的一条或多条列,执行第一任务,以及响应于第一任务执行期间的高速缓存缺失,执行高速缓存列填充操作,并在高速缓存列填充操作期间执行第二任务。高速缓冲存储器通过产生处理器中断,或通过通知运行在处理器中的任务调度程序来通知列填充操作的处理器。
Description
相关申请
本申请以2001年8月29日提交的申请号为60/315,655的临时申请为在先申请,并将其全部合并入本申请作为参考。
技术领域
本发明涉及数字处理系统,特别是通过响应高速缓存缺失而切换任务来提高处理器性能的方法和装置。
背景技术
诸如用于无线应用中的嵌入式处理器,可以在单个芯片上包括数字信号处理器、微控制器和存储器。在无线应用中,由于需要维持与无线系统时序的同步,所以处理速度是关键因素。低成本,嵌入式处理器系统面临的唯一的性能挑战,其中之一是使用低成本的慢存储器而维持高处理能力。
在无线应用的例中,数字信号处理器(DSP)经常用于执行计算密集的任务。在这种系统中,低成本、芯片外闪速存储器形成系统的大容量储存能力。然而,闪速存储器的访问时间远大于数字信号处理器的最小周期时间。为了在DSP上获得高性能,应该从远快于芯片外闪速存储器的本地存储器上执行。
嵌入式处理器系统可以代替或在简单RAM基础上,利用某些形式的满足请求的高速缓冲存储器来实现本地存储器,这需要另外的处理器或直接存储器访问(DMA)控制器,用来在处理器需要代码和/或数据之前或之后,将代码和/或数据载入本地存储器中。
当DSP遇到高速缓存缺失,高速缓存硬件必须从存储器体系中的较慢存储器来填充高速缓存列。这种高速缓存满足请求的方面经常意味当高速缓存列全部或部分填充的期间,DSP停止。
因此,需要用来提高基于高速缓存的嵌入式处理器的处理能力的方法和装置。
发明内容
根据本发明的第一方面,提供一种方法,用于操作包括处理器和高速缓冲存储器的嵌入式处理器系统。该方法包括:用与第一任务相关的数据填充高速缓冲存储器的一条或多条列;执行第一任务,该任务包括访问高速缓冲存储器中的数据;响应于第一任务执行期间的高速缓存缺失,执行高速缓存列填充操作;将与高速缓存列填充操作相关的地址与特定的地址范围比较;仅在地址范围比较的结果符合基于特定地址范围的预定的标准时,向处理器通知高速缓存列操作;以及响应于通知处理器,在高速缓存列填充操作期间执行第二任务
根据本发明的又一方面,一种嵌入式处理器系统包括用于存储与第一任务相关的数据的高速缓冲存储器,和用于执行第一任务的处理器。高速缓冲存储器包括高速缓存控制器,用于检测高速缓存缺失,响应高速缓存缺失而执行高速缓存列填充操作,将与高速缓存列填充操作相关的地址与特定的地址范围比较,并且仅在地址范围比较结果符合基于所述特定的地址范围的预定标准时产生高速缓存缺失通知。处理器响应于执行第一任务期间的高速缓存缺失通知,在高速缓存列填充操作期间执行第二任务。
附图说明
为了更好地理解本发明,参照以下附图:
图1是现有技术的嵌入式处理器系统的简化框图;
图2是根据本发明一个实施例的嵌入式处理器系统的简化框图;
图3是图2所示的高速缓冲存储器的实施例的框图;
图4是根据本发明一个实施例的由高速缓存控制器实现的程序的流程图。
具体实施方式
图1表示现有技术的数字处理系统的框图。如数字信号处理器(DSP)10这样的处理器和高速缓冲存储器12位于单处理芯片14上。高速缓冲存储器12可以是指令高速缓存或数据高速缓存。一些系统包括数据高速缓存和指令高速缓存。芯片外闪速存储器20连接至高速缓冲存储器12。处理芯片14可以包括其他元件,比如芯片内存储器、用于执行微控制器指令的微控制器、直接存储器访问(DMA)控制器和各种至芯片外设备的接口。
高速缓冲存储器12与闪速存储器20构成存储器体系,其中高速缓冲存储器12具有相对低的潜伏时间和相对低的容量,闪速存储器20具有相对高的潜伏时间和相对高的容量。在操作中,DSP 10执行指令并访问高速缓冲存储器12中的数据和/或指令。除非发生高速缓存缺失,否则低潜伏时间的高速缓冲存储器12都能提供高性能。在高速缓存缺失的情况下,高速缓存列填充操作需要从闪速存储器20加载所请求的数据。从闪速存储器20加载高速缓存列的时间可能是DSP 10的几百个时钟周期。在列填充操作中,DSP 10停止,因此性能降低。
图2表示根据本发明一个实施例的数字处理系统的简化框图。图1和图2中相同的要素标以相同的参考数字。一个适用的DSP的例子在2000年11月16日公开的PCT公开号为WO 00/687783中公开。然而,本发明不限定于任何数字信号处理器。此外,DSP 10可以替换为微控制器、通用微控制器和其他任何处理器。
根据本发明的特征,代替DSP 10在高速缓存列填充操作期间停止,重新安排DSP 10执行另外的软件任务,比如中断服务程序(ISR)。当高速缓存列填充操作结束后,第一软件任务的处理可以在稍后的时间再继续。参照图2,高速缓存缺失中断发生器30检测高速缓存列填充操作,当高速缓存12从闪速存储器20执行高速缓存列填充操作时,产生至DSP 10的中断。作为响应,DSP 10在高速缓存列填充操作期间执行第二软件任务。公开的方法通过利用处理器的时间来提高性能,否则的话,在该时间内,处理器将停止以等待高速缓存列填充操作的结束。
将软件组织为多个独立线程,这些独立线程由操作系统(OS)调度程序管理的软件组织,也能够利用这个方法。在这种情况下,在高速缓存列填充操作期间可以启动新的软件进程。多线程软件组织可以看作是主程序/中断服务程序模型的更广泛的扩展集。主/ISR模型包括两个软件线程,并且处理器中断硬件执行任务调度程序的功能。
使用这种方法的系统的元素有:(1)处理器,具有比它所访问的存储器子系统更快的周期时间;(2)处理器序列发生器组织,当识别到比当前任务优先级更高的中断声明时,中止已经进入指令流水线的指令并重定位到开始新任务的指令。这个功能允许开始并发生存储器访问,但然后中止,允许开始另外的任务;(3)代码和/或数据高速缓存,位于处理器与较慢存储器子系统之间;和(4)软件模块性,这样在任何时间,独立的任务(例如,中断处理或多线程)可以被利用而运行在处理器上。
系统可以选择地包括电路,用来发信号通知操作系统已经发生了高速缓存缺失,从而允许操作系统开始新的未决的软件任务/线程。如果没有这种电路,处理器以常规的方式在高速缓存缺失时停止,除非在处理器停止期间发生不相关的中断。如果有附加的电路,系统可以保证高速缓存缺失时总是产生中断。另外的观点是包括地址范围检查电路,这样仅在与高速缓存缺失相关的地址在规定的地址范围内的时候,产生关于高速缓存缺失的中断。地址范围可以是固定的或者是可编程的。作为嵌入式系统的可选择的增强,该嵌入式系统具有多个存储器子系统,并具有不同的访问潜伏期(例如,芯片外闪速存储器和芯片内SRAM存储器),高速缓存能够使用多个列填充和拷回(copyback)缓冲器以进一步增强总处理能力。这种增强也需要高速缓存控制器与每个存储器系统之间单独的总线,或者使用无次序列填充协议的共同的总线(例如,总线数据标记)。
再参照图2,当DSP 10产生一缺失高速缓冲存储器12但是可以被高速缓存的存储器访问时,高速缓存控制器产生至芯片外闪速存储器20的高速缓存列填充操作。从闪速存储器读取整个高速缓存列的访问时间会是几百个处理器周期。
高速缓存缺失中断发生器30确定高速缓存控制器已经请求高速缓存列填充操作,并产生至DSP 10的中断。一检测出中断,DSP 10就中止流水线中的指令,它中止产生高速缓存列缺失的指令并开始执行中断服务程序。
中断服务程序确定接下来的适当的步骤。例如,ISR会确定驻留在本地存储器系统中的可以运行的高优先级别的任务。只要ISR选中本地高速缓存(或者,如经常发生的那样,ISR在本地RAM以外执行,该访问与本地高速缓存并行),那么在完成高速缓存列填充操作所需时间内DSP 10不停止。当ISR从运行到完成,则返回执行产生高速缓存缺失的低优先级别的任务。
在更一般的多线程软件模型中,中断调用操作系统调度程序,该调度程序安排执行当前高优先级别的软件线程,该软件线程可以在本地存储器资源中运行。假定高速缓存列填充操作现在已经完成,该软件线程或者(a)从运行到完成,或者(b)在一些点被调度程序先占,从而另一个线程可以运行,就象由于高速缓存缺失而被先占的线程。
图3表示用于实现本发明的高速缓冲存储器的实施例的框图。图3的高速缓冲存储器相当于图2的高速缓冲存储器12和高速缓存缺失中断发生器30。按照常规,高速缓冲存储器包括标志阵列100、数据阵列102、命中/缺失逻辑104、存储缓冲器106、和写缓冲器108。高速缓冲存储器还包括高速缓存控制器110,它具有用于产生高速缓存缺失信号的电路;一个或多个列填充缓冲器112A和112B;一个或多个拷回缓冲器114A和114B。高速缓冲存储器还包括地址范围比较电路120。
当DSP 10在执行第一任务或线程期间产生读访问时,读地址被提供给命中/缺失逻辑104。标志阵列100中存储高位地址比特,用来标识由高速缓存列代表的存储器中特定的地址源。将标志与读地址比较,确定所请求的数据是否在高速缓存中。如果在,将读数据提供给DSP10。如果缺失,将缺失信号提供给高速缓存控制器110并启动高速缓存列填充操作。在高速缓存列填充操作中,从闪速存储器20读出包含所请求数据的高速缓存列。通过列填充缓冲器112,将高速缓存列载入标志阵列100和数据阵列102,并且可以由DSP 10使用。
在高速缓存缺失的情况下,高速缓存控制器110向DSP 10提供高速缓存缺失信号,用来启动DSP 10执行第二任务或线程。在高速缓存缺失的情况下,被代替的高速缓存列通过拷回缓冲器114A、114B被复制到闪速存储器20。可选择的,高速缓冲存储器可以包括两个或多个列填充缓冲器112A、112B和两个或多个copyback缓冲器114A、114B,用来增强在高速缓存列填充操作期间执行第二软件任务的性能。
可以选择地提供地址范围比较电路120,用来限制地址范围,该地址范围是在高速缓存列填充操作期间在其上执行第二任务。特别是,地址范围比较电路120接收高位地址限制和低位地址限制,该地址限制可以是固定的或可编程的。地址范围比较电路120也接收在高速缓存列填充操作期间提供给闪速存储器20的存储器载入地址。地址范围比较电路120可以配置为确定存储器载入地址是否在高位地址限制和低位地址限制之间,或者在其内或者在其外。在另一种方法中,地址范围比较电路120可以确定存储器载入地址是否在高位地址限制和低位地址限制之外。在任何一种情况下,如果满足特定的比较标准,将提供给高速缓存控制器110一个信号,该信号用于使高速缓存缺失信号能提供给DSP 10。
图4表示通过响应高速缓存缺失操作而切换任务来提高处理器性能的程序的流程图。在步骤200中,处理器(DSP 10)通过参考高速缓冲存储器12中的操作数与/或指令来执行任务A。在步骤202,高速缓冲存储器12确定是否发生了高速缓存缺失。如果没发生高速缓存缺失,处理器继续执行步骤200中的任务。在发生了高速缓存缺失的情况下,高速缓冲存储器12开始执行步骤204中的高速缓存列填充操作。高速缓存列填充操作将包含所请求数据的高速缓存列从闪速存储器20载入到高速缓冲存储器12。在步骤206中,高速缓冲存储器12中的地址范围比较电路120将高速缓存缺失地址与所选择的地址范围如上述那样进行比较。在步骤208中,确定高速缓存缺失地址是否符合特定的地址范围比较标准。如果高速缓存缺失地址不符合地址范围比较标准,处理器在步骤210中等待高速缓存列填充操作完成,并返回步骤200中任务A的执行。如果高速缓存缺失地址符合地址范围比较标准,则在步骤212中通知处理器改变任务。参照图3,高速缓存控制器110向DSP 10发送高速缓存缺失信号。然后在步骤214中,在高速缓存列填充操作期间,处理器执行任务B。应该理解与地址范围比较相关的步骤206、208、和210在图4的处理中是可选择的。
以上阐述了本发明的至少一个实施方式的许多方面,对于本领域技术人员而言,可以容易做各种变更、修改、和改进。这种变更、修改、和改进是指本发明的一部分,在本发明的主旨和范围之内。因此,前述说明和图只是示例。
Claims (22)
1.一种方法,用于操作包括处理器和高速缓冲存储器的嵌入式处理器系统,包括:
用与第一任务相关的数据填充高速缓冲存储器的一条或多条列;
执行第一任务,该任务包括访问高速缓冲存储器中的数据;
响应于第一任务执行期间的高速缓存缺失,执行高速缓存列填充操作;
将与高速缓存列填充操作相关的地址与特定的地址范围比较;
仅在地址范围比较的结果符合基于所述特定的地址范围的预定的标准时,向处理器通知高速缓存列操作;以及
响应于通知处理器,在高速缓存列填充操作期间执行第二任务。
2.如权利要求1所述的方法,其中数据包括与第一任务相关的一个或多个操作数。
3.如权利要求1所述的方法,其中数据包括与第一任务相关的一个或多个指令。
4.如权利要求1所述的方法,其中向处理器通知高速缓存列填充操作的步骤包括通知运行在处理器中的任务调度程序。
5.如权利要求1所述的方法,其中执行第二任务的步骤包括执行比第一任务更高优先级别的任务。
6.如权利要求1所述的方法,其中在单个处理器上执行第一和第二任务。
7.如权利要求1所述的方法,其中地址范围比较中使用的地址范围是可编程的。
8.如权利要求1所述的方法,还包括访问高速缓冲存储器中与第二任务相关的数据。
9.如权利要求1所述的方法,其中执行第二任务的步骤包括读取用于第二任务的指令和操作数。
10.如权利要求1所述的方法,还包括当高速缓存列填充操作完成时恢复第一任务。
11.一种嵌入式处理器系统,包括:
高速缓冲存储器,用于存储与第一任务相关的数据,所述高速缓冲存储器包括高速缓存控制器,用于检测高速缓存缺失,响应于高速缓存缺失而执行高速缓存列填充操作,用于将与高速缓存列填充操作相关的地址与特定的地址范围比较,并且用于仅在地址范围比较结果符合基于所述特定的地址范围的预定标准时产生高速缓存缺失通知;和
处理器,用于执行第一任务,并响应于执行第一任务期间的高速缓存缺失通知,在高速缓存列填充操作期间执行第二任务。
12.如权利要求11所述的嵌入式处理器系统,其中数据包括与第一任务相关的一个或多个操作数。
13.如权利要求11所述的嵌入式处理器系统,其中数据包括与第一任务相关的一个或多个指令。
14.如权利要求11所述的嵌入式处理器系统,其中高速缓存缺失通知包括通知运行在所述处理器中的任务调度程序。
15.如权利要求11所述的嵌入式处理器系统,其中第二任务具有比第一任务更高的优先级别。
16.如权利要求11所述的嵌入式处理器系统,其中第一和第二任务在单个处理器上执行。
17.如权利要求11所述的嵌入式处理器系统,其中特定的地址范围是可编程的。
18.如权利要求11所述的嵌入式处理器系统,其中配置所述高速缓冲存储器用于存储与第二任务相关的数据。
19.如权利要求11所述的嵌入式处理器系统,其中所述处理器包括用来读取用于执行第二任务的指令和操作数的装置。
20.如权利要求11所述的嵌入式处理器系统,其中所述处理器还包括用于当高速缓存列填充操作已经结束时恢复执行第一任务的装置。
21.如权利要求11所述的嵌入式处理器系统,其中所述高速缓冲存储器包括两个或多个列填充缓冲器。
22.如权利要求11所述的嵌入式处理器系统,其中所述高速缓冲存储器包括两个或多个列拷回缓冲器。
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