CN1301473C

CN1301473C - Multiprocessor system and method for sharing bootstrap module thereof

Info

Publication number: CN1301473C
Application number: CNB031468810A
Authority: CN
Inventors: 赵凯; 陈诗军; 苏绣江; 黄钟琪
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2003-09-17
Filing date: 2003-09-17
Publication date: 2007-02-21
Anticipated expiration: 2023-09-17
Also published as: CN1525353A

Abstract

The present invention relates to a multiprocessor system and a method for the system to share a boot module, particularly to a multi-CPU system with a PCI controller, which belongs to the field of communication. The multiprocessor system comprises a plurality of processors, wherein each processor is provided with a control state register, a dynamic RAM, a static RAM, a serial port, etc. which are matched with the processor, and the processors are connected with each other by a PCI bus so as to share one PCI arbiter; a processor with the boot module serves as a main processor, and other processors serve as the auxiliary processors. When the power of the system is switched on, the main processor reads instructions from the boot module of the main processor, and the auxiliary processors obtain instructions from the RAMs; the main processor restores the auxiliary processors after initializing the auxiliary processors, and the system can normally operate at this time. The present invention has the advantages of simple method, capability of saving boot modules and Ethernet controllers, etc.

Description

Multicomputer system is shared the method for bootstrap module

Technical field

The present invention relates to a kind of multiprocessor (CPU) system and multi-CPU system and share the method for BOOT FLASH (bootstrap module), relate in particular to many CPU in the multi-CPU system of the relevant band of communication field PCI (Peripheral Component Interconnect, peripheral element extension interface) controller and this system and share the method for bootstrap module.

Background technology

At present in embedded system for the processing power that increases veneer, increase integrated level, usually cpu systems are overlapped in design more on same veneer, every cover system carries a BOOT FLASH, place at the band pci controller utilizes CPLD (Complex Programble Logic Device toward contact, complex programmable logic equipment) PCI moderator of oneself design, and from network interface or FLASH download version file.As shown in figures 1 and 3.Fig. 1 be before by the hardware principle block diagram of the multi-CPU system of art methods design, two covers or overlap cpu system self more and respectively be with a BOOT FLASH, a PCI moderator, at least one Ethernet interface in the system.Fig. 3 is the software flow pattern that powers on by each cpu system of art methods, each cpu system is separate in the system, behind the electrification reset, all CPU are instruction fetch from the BOOT FLASH of self, finish the initialization of hardware, also pass through Ethernet or FLASH load application version file, finish the startup of system.

But CPU (hereinafter to be referred as CPU) for some band pci controller, if method for designing according to this prior art, obviously increase cost, also taken valuable printing board PCB space, can seek the startup that some new bootstrap techniques are finished system for this reason.The one piece of application number that retrieves from U.S. trademark patent office is that 20020138156 patented claim document " System ofconnecting multiple processors in cascade " (serial multiprocessor connected system) has related to the startup of relevant multisystem, it utilizes bootStrap (steering tape) bus of serial to finish the transmission of start-up code of each cpu subsystem of multi-CPU system, but this method needs to design a cover bootStrap bus on hardware, and to the processing of the RAM equipment of each cpu system also more complicated.

Summary of the invention

Purpose of the present invention provides a kind of multi-CPU system scheme just in order to overcome above-mentioned shortcoming, and provides many CPU to share the method for BOOT FLASH channeling conduct.

A kind of multicomputer system among the present invention, comprise a plurality of processors, each processor all has supporting state of a control register, DRAM, SRAM, serial ports etc., a plurality of processors are associated in together by pci bus, a shared PCI moderator, a processor band bootstrap module is as primary processor, and other processors conducts are from processor; Wherein the PCI moderator is realized by complex programmable logic equipment.

Multiprocessor among the present invention is shared the method for bootstrap module, comprises the following steps: (1) initialization primary processor critical registers; (2) primary processor DRAM and SRAM, memory test; (3) in primary processor, copy to code segment and data segment in the internal memory and jump to this place's operation; (4) primary processor interrupts and the abnormality processing initialization; (5) main processor cores initialization; (6) primary processor memory management initialization; (7) main processor system clock and auxiliary clock initialization; (8) pci controller and PCI device initialize; (9) primary processor IO and file system initialization: (10) load the primary processor serial port drive and Ethernet drives; (11) load the primary processor version file: (12) operation primary processor version file: it is characterized in that: in described step (8) afterwards, step (9) before, and is further comprising the steps of;

1.1 from processor critical registers and DRAM thereof, SRAM initialization;

1.2 test is from processor memory;

1.3 code segment and data segment are copied to internal memory from processor system, and a jump instruction are set at the first address of internal memory;

1.4 reset from processor.

Resetting in the said method from processor, carry out following steps from processor:

2.1 the code segment value in the internal memory;

2.2 interrupt and the abnormality processing initialization;

2.3 kernel initialization;

2.4 memory management initialization;

2.5 system clock and auxiliary clock initialization;

2.6 pci controller and PCI device initialize;

2.7 IO and file system initialization;

2.8 loading serial port drive and/or Ethernet drives;

2.9 load application version file;

2.10 operation version file.

The present invention compared with prior art, method is simple, need on hardware, not add optional equipment, and can save BOOT FLASH, CPLD once handles on software, can not pass through Ethernet load application version file from CPU, and by pci bus from host CPU load application version file, can also save ethernet controller from cpu system.If produce in batches, the present invention will bring considerable economic.

Description of drawings

Fig. 1 is a multi-CPU system theory diagram of the prior art;

Fig. 2 is the theory diagram of an embodiment of multi-CPU system of the present invention;

Fig. 3 is by art methods designed system boot flow figure;

Fig. 4 is the method flow diagram among the present invention;

Fig. 5 is the boot flow figure from CPU of the present invention;

Fig. 6 is the cpu address among the present invention and the mapping relations figure of PCI address.

Embodiment

Host CPU has BOOT FLASH in system of the present invention, and is not with BOOT FLASH from CPU.All CPU are associated in together by pci bus, and a shared PCI moderator.When system powered on, host CPU was from the BOOT FLASH instruction fetch of self, and obtained instruction from CPU from RAM, but what at this moment obtain is illegal instruction, can't move, but host CPU was to allowing it reset once more after the CPU initialization after a while, and at this moment it can normally move.

Core of the present invention is to utilize a kind of warm reset, makes the instruction fetch and do not carry out other operation from RAM from CPU.Utilize this specific character, power on or after host CPU resets in system, host CPU is configured the PCI space from CPU, will be from the various state of a control register CSR (Controll Status Registers) of the inside of cpu system, DRAM, SRAM etc., shine upon to host CPU by pci controller, make CSR from CPU, DRAM (DRAM), SRAM (SRAM) becomes the open source of host CPU, host CPU just can carry out initialization to the CSR from CPU, particularly the DRAM control register is carried out initialization, code segment and data segment with instruction copies to from the DRAM of cpu system then, and by host CPU to after the CPU initialization, allowing it reset once more, make instruction fetch the DRAM from self, finish startup from CPU from CPU.

The present invention is described in detail below in conjunction with accompanying drawing.

1, the system architecture among the present invention

Multicomputer system functional-block diagram among the present invention is (in the present embodiment, system comprises a primary processor and one from processor, and two CPU have only drawn among the figure) as shown in Figure 2.All CPU link to each other by pci bus.Main CPU system is done by the CPU1 system, starts by the BOOT FLASH that carries.The CPU2 system is done from system, and its some resource (dram controller, SRAM controller) is come initialization by the CPU1 system.PCI moderator among the figure is realized by CPLD, finishes the control of pci bus.

2, the method among the present invention

Method among the present invention is exactly in fact the software of the main CPU system flow process that powers on, as shown in Figure 4.This method flow process is similar generally to flow process of the prior art (shown in Figure 3).After system powered on or resets, all CPU are instruction fetch from BOOT FLASH.The same with most processors, article one instruction after CPU powers on is a jump instruction, point to the start address of BOOT FLASH instruction, program at first is to close cache (buffer memory), carries out the initialization of DRAM and SRAM controller, opens cache then, and DRAM carried out full test, if mistake is found in the DRAM test, then the initialization of dram controller is incorrect, needs to adjust initialized parameter.If test successfully, just copy to the code segment among the BOOT FLASH and data segment among the DRAM and begin instruction fetch from DRAM.After the DRAM instruction fetch, successively finish the initialization of pci controller, the address assignment of PCI equipment and initialization, the initialization of operating system nucleus, and load serial port drive, Ethernet driving, by network, FLASH or disk load application version file, finish the startup of system.

The present invention and the software of the prior art flow process that powers on is compared, behind pci controller and PCI device initialize, host CPU will be given from the CSR of CPU and DRAM and distribute the address, and their configuration space carried out initialization, by pci bus, just all become the addressable resource of host CPU from CSR, the DRAM of CPU, SRAM; Afterwards, host CPU just carries out initialization to the CSR (clock controller) from CPU, and they are carried out full test, if test is not passed through, will alarm and withdraw from, require the deviser that initialized parameter is adjusted, if test is by just copying code segment among the main CPU system BOOT FLASH and data segment from the ad-hoc location of cpu system DRAM to; Putting a jump instruction from the start address of DRAM after copy is finished, this instruction will make and jump to foregoing special address from CPU and reach instruction, and this jump instruction is article one instruction that obtains behind cpu reset; After finishing above-mentioned work, host CPU just to write foregoing special reset instruction from the reseting register of CPU, just can normally move from DRAM from CPU in instruction fetch.

3, among the present invention from the software of the cpu system flow process that powers on

Among the present invention from the software flow of CPU after host CPU resets as shown in Figure 5.Receive the reset command of host CPU from the reseting register of CPU after, just from the first address instruction fetch of DRAM and jump to foregoing specific position instruction fetch.Owing to by the host CPU initialization, behind cpu reset, can not carry out initialization to them again from the dram controller of CPU, cache.In addition because the host CPU PCI address that has been each PCI devices allocation, can be from CPU again to each PCI equipment deallocation yet, but from the configuration register of each PCI equipment, read these addresses.Other operation is identical with process flow diagram shown in Figure 3, mainly finishes the initialization of kernel, the loading that serial port drive, Ethernet drive.Last load application version file is finished the startup of system.

Can finish by Ethernet, FLASH or disk from cpu system load application version file, also can obtain from main CPU system by pci bus.When main CPU system obtains version file, only need in the code of master and slave cpu system, add a PCI communication module, master-slave cpu passes through this PCI communication module interactive information, finish version file from main CPU system to transmission from cpu system.Make the ethernet controller that just can save the download version file in this way from cpu system.

4, master-slave cpu map addresses of the present invention

Fig. 6 is master and slave cpu address and PCI address mapping relation figure among the present invention (among the figure be example explanation with two CPU).

In the present invention (not marking PCI IO space the figure) carried out distributing unitedly in host CPU, PCI MEM (PCI internal memory) space and the PCI IO space of CSR, DRAM, SRAM and Ethernet from CPU in pci bus.The DRAM_BASE of host CPU (DRAM base address), SRAM_BASE (SRAM base address), CSR_BASE (CSR base address) reflect respectively body to pci bus PCI_DRAM_BASE1, PCI_SRAM_BASE1, PCI_CSR_BASE1, will be from DRAM_BASE, the SRAM_BASE of CPU, PCI_DRAM_BASE2, PCI_SRAM_BASE2, the PCI_CSR_BASE2 that CSR_BASE is mapped to pci bus respectively, they are determined with DRAM, the SRAM of reality and space size DRAM_SIZE, SRAM_SIZE, the CSR_SIZE of CSR in the size in PCI space.This mapping is to finish when host CPU carries out initialization to the PCI configuration register of each PCI equipment.On pci bus, be exactly that DRAM to main CPU system conducts interviews like this to the visit in PCI_DRAM_BASE1～PCI_DRAM_BASE2 space, PCI_CSR_BASE2～PCI_CSR_BASE2+CSR_SIZE space is conducted interviews, exactly the CSR space from CPU is conducted interviews.

In CPU, a certain section physical address space (we are called cpu address, and the address of pci bus output is called the PCI address) is used as the visit to the PCI space, to the operation of this sector address, will produce the PCI operation.Host CPU when initialization with the PCI map addresses to certain section space more than the PCI_MEM_BASE of cpu address of oneself, host CPU is operated a certain section space above the PCI_MEM_BASE of oneself like this, the PCI time sequential routine be will change into automatically, DRAM, SRAM, CSR just can be operated from cpu system.

Claims

1, a kind of multicomputer system is shared the method for bootstrap module, comprises the following steps: (1) initialization primary processor critical registers; (2) carry out the initialization of dynamic ram and static RAM (SRAM) controller, primary processor dynamic ram and static RAM (SRAM) test; (3) in primary processor, code segment and data segment copied in the internal memory and jump in the internal memory and move; (4) primary processor interrupts and the abnormality processing initialization; (5) main processor cores initialization; (6) primary processor memory management initialization; (7) main processor system clock and auxiliary clock initialization; (8) pci controller and PCI device initialize; (9) primary processor I/O and file system initialization; (10) loading primary processor serial port drive and Ethernet drives; (11) load the primary processor version file; (12) operation primary processor version file; It is characterized in that: in described step (8) afterwards, step (9) is before, and is further comprising the steps of:

1.1 from processor critical registers and dynamic ram thereof, static RAM (SRAM) initialization;

1.2 test is from processor memory;

1.3 code segment and data segment copied to from the internal memory of processor system and at the first address from the internal memory of processor system from the internal memory of primary processor a jump instruction is set, this instruction will make from the address that CPU jumps under the duplicating position and reach instruction;

1.4 reset from processor.

2, the described multicomputer system of claim 1 is shared the method for bootstrap module, and it is characterized in that: described step 1.4 may further comprise the steps:

1.4.1 the code segment value in the internal memory;

1.4.2 interrupt and the abnormality processing initialization;

1.4.3 kernel initialization;

1.4.4 memory management initialization;

1.4.5 system clock and auxiliary clock initialization;

1.4.6 pci controller and PCI device initialize;

1.4.7 I/O and file system initialization;

1.4.8 loading serial port drive and/or Ethernet drives;

1.4.9 load application version file;

1.4.10 operation version file.