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Numéro de publicationCN1302403 C
Type de publicationOctroi
Numéro de demandeCN 200410002889
Date de publication28 févr. 2007
Date de dépôt20 janv. 2004
Date de priorité20 janv. 2004
Autre référence de publicationCN1558335A
Numéro de publication200410002889.3, CN 1302403 C, CN 1302403C, CN 200410002889, CN-C-1302403, CN1302403 C, CN1302403C, CN200410002889, CN200410002889.3
Inventeurs徐明椲, 彭盛昌
Déposant威盛电子股份有限公司
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes:  SIPO, Espacenet
Optimization verification method for processor bus
CN 1302403 C
Résumé  Langue du texte original : Chinois
一种处理器总线最佳化验证方法。 A processor bus optimization authentication method. 首先,设定处理器与北桥芯片组之间总线的总线启始频宽与总线启始频率以及总线操作频宽与总线操作频率,接下来,发出读取南桥芯片组的指令,接下来,南桥芯片组输出总线中断信号以中断处理器与北桥芯片组之间的总线的联机,并启始计数器的计数值以及输出具有第一电平的最佳化验证信号。 First, set the bus between the processor and the Northbridge chipset bus starting starting frequency bandwidth and bus and bus operations and bus operating frequency bandwidth, then, issued a directive to read the Southbridge chipset, then, Southbridge chipset output bus interrupt signal to interrupt the connection between the bus of the processor and Northbridge chipset, and starts the count value of the counter and an output having a first level optimization verification signal. 当计数器的计数值累积达一既定值,则南桥芯片组输出总线连接信号,并将上述最佳化验证信号的电平转换为第二电平。 When the count value of the counter accumulated to a certain level, the Southbridge chipset output bus connection signal and convert the above optimal level verification signal is the second level. 最后,总线根据总线连接信号以及第二电平的最佳化验证信号而重新连接处理器与北桥芯片组,并工作于另一总线操作频宽与总线操作频率。 Finally, the processor bus and to reconnect with the Northbridge chipset bus connection according to the second level signal and verification signal optimization, and work on the other bus operations and the bus operating frequency bandwidth.
Revendications(7)  Langue du texte original : Chinois
1.一种处理器总线最佳化验证方法,适用于一处理器、一北桥芯片组、耦接于该处理器与北桥芯片组之间的总线以及耦接于该北桥芯片组的南桥芯片组,包括下列步骤:设定该处理器与北桥芯片组之间总线的总线启始频宽与总线启始频率以及总线操作频宽与总线操作频率;设定该总线的最佳化操作频宽与最佳化操作频率;发出读取该南桥芯片组的指令;该南桥芯片组接收到该指令后,输出一总线中断信号以中断该处理器与北桥芯片组之间的总线的连线,并启始一计数器的计数值,以及输出具有一第一电平的一最佳化验证信号;当该计数器的计数值累积达一既定值,则该南桥芯片组输出一总线连接信号,并将该最佳化验证信号的电平转换为一第二电平;以及该总线根据该总线连接信号以及具有第二电平的最佳化验证信号而重新连接该处理器与北桥芯片组,并工作于最佳化总线操作频宽与最佳化总线操作频率。 A processor bus optimized authentication method for a processor, a Northbridge chipset, coupled to the bus between the processor and the Northbridge chipset and coupled to the Northbridge chipset Southbridge group, comprising the steps of: setting between the processor and the Northbridge chipset bus bus bus bandwidth starting starting frequency bandwidth and bus operations and bus operating frequency; setting to optimize the operation of the bus bandwidth and optimizing the operating frequency; issuing a read command to the Southbridge chipset; the Southbridge chipset after receiving the instruction, the output of a bus interrupt signal to interrupt the bus between the processor and the Northbridge chipset connection and Kai begin a count value of the counter, and a verification signal output optimized with a first level; when the cumulative count of the counter reaches a predetermined value, the Southbridge chipset output signal of a bus connection, and level shifting the optimized authentication signal is a second level; and the bus signals and based on the optimized bus connection verification signal having the second level of re-connecting the processor and Northbridge chipset, and work in the best of bus operations and optimizing bandwidth bus operating frequency.
2.如权利要求1所述的处理器总线最佳化验证方法,其中该总线中断信号以及总线连接信号用于设定以及解除由该南桥芯片组的一输出端所输出的信号。 Processor bus optimization 2. The authentication method according to claim, wherein the interrupt signal and the bus connection bus signals for setting and releasing an output signal from the Southbridge chipset outputted.
3.如权利要求1所述的处理器总线最佳化验证方法,其中该总线中断信号以及总线连接信号是由同一输出端所输出。 Processor bus optimization authentication method according to claim, wherein said bus interrupt signal and a bus connection signal is outputted from the same output.
4.如权利要求1所述的处理器总线最佳化验证方法,其中该最佳化验证信号是由一电平检测电路所输出。 Processor bus optimization 4. The authentication method according to claim 1, wherein the verification signal is optimized by a level detection circuit output.
5.如权利要求4所述的处理器总线最佳化验证方法,其中该电平检测电路包括一触发器以及耦接于该触发器的一或逻辑门,当该南桥芯片组输出该总线中断信号时,则该触发器输出具有第一电平的最佳化验证信号,当该南桥芯片组输出该总线连接信号时,则该触发器输出具有第二电平的最佳化验证信号。 5. The processor bus optimized authentication method according to claim 4, wherein the level detection circuit comprises a flip-flop and coupled to the trigger of an OR logic gate, when the output of the bus Southbridge chipset interrupt signal, the flip-flop output having a first level optimization verification signal, when the output of the Southbridge chipset bus connection signal, the flip-flop output having the second level verification signal optimization .
6.如权利要求4所述的处理器总线最佳化验证方法,其中该电平检测电路设置于该南桥芯片组的输出端。 Processor bus optimization authentication method as claimed in claim 4, wherein the level detecting circuit provided in the Southbridge chipset output.
7.如权利要求4所述的处理器总线最佳化验证方法,其中该电平检测电路设置于该北桥芯片组或处理器的输入端。 7. The processor bus optimized authentication method according to claim 4, wherein the level detecting circuit is provided to the Northbridge chipset and the processor input.
Description  Langue du texte original : Chinois
处理器总线最佳化验证方法 Processor bus optimized authentication method

技术领域 FIELD

本发明涉及一种处理器总线最佳化验证方法,特别是涉及一种应用于AMD K8操作平台(plat form)的处理器总线最佳化验证方法。 The present invention relates to a processor bus optimization authentication method, and more particularly to an AMD K8 platform (plat form) of the processor bus optimized authentication method is applied.

背景技术 BACKGROUND

Legacy I/O总线结构因其低成本以及利用已建立的标准软件以及硬件标准而容易实施等特性,因此广泛使用于嵌入式系统(embedded system)中。 Legacy I / O bus architecture standard software and hardware standards for its low cost and the use of established and easily implemented and other characteristics, it is widely used in embedded systems (embedded system) in. 然其最高操作频率仅为66MHz左右,因此,现今操作频率达500MHz以上的处理器,必须使用具有更高频宽以及操作频率的总线。 However, its highest operating frequency is only about 66MHz, therefore, now operating at frequencies up to 500MHz or faster processor, you must use a higher bus bandwidth and operating frequency.

闪电数据传输I/O总线(Lightning Data Transport,LDT,I/O Bus),亦称高传输I/O总线(Hyper Transport,HT,I/O Bus),满足了目前计算机网络、通讯系统以及其它嵌入式系统所需的高频宽需求,为一种具有灵活性、扩充性以及容易使用的总线架构。 Lightning data I / O bus (Lightning Data Transport, LDT, I / O Bus), also known as high transmission I / O bus (Hyper Transport, HT, I / O Bus), meet the current computer networks, communications systems, and other embedded systems demand high bandwidth required for a flexible, scalable and easy to use bus architecture. LDT I/O总线能够提供下一代处理器以及通讯系统所需的频宽(width),再者,LDT I/O总线还具有可调整的总线频宽以及操作速度等功能,以符合电源、空间以及成本的需求。 LDT I / O bus to provide the next generation of processors and communications systems required bandwidth (width), Furthermore, LDT I / O bus also has adjustable bus bandwidth and speed of operation, and other functions, to meet the power and space and cost requirements.

传统LDT I/O总线的频宽与操作频率的最佳化必须通过执行LDT总线中断(disconnection)以及重新连接(reconnection)程序以使得LDT总线操作于预期的频宽与操作频率。 Traditional LDT I / O bus bandwidth and operating frequency so that the LDT must be optimized by performing a bus operation LDT bus interrupt (disconnection) and re-connect (reconnection) with the program in the intended operating frequency bandwidth.

图1示出了传统的具有LDT总线的计算机系统架构图。 Figure 1 shows a conventional computer system architecture diagram with LDT bus. 如图所示,处理器10与北桥14之间具有一LDT总线12。 As shown, having a LDT bus between the processor 10 and the north bridge 12 14. 在此,处理器以AMD所制造的K8CPU为例。 In this case, AMD processor manufactured K8CPU example. 而北桥14与南桥18之间具有另一总线16。 The north bridge 18 and the south bridge 14 between the bus 16 with another. 当要执行处理器电源管理程序以及总线最佳化程序时,位于处理器10与北桥14之间的LDT总线12必须执行中断以及重新联机的操作,上述操作需受到由南桥18所输出的信号LDTSTOP#的电平变化所控制。 When processor power management program to be executed and the bus optimized program, located in the processor and Northbridge 10 14 12 between the LDT bus must execute the interrupt and re-line operation, the above operation required by the signal output by the Southbridge 18 LDTSTOP # level change control. 信号LDTSTOP#的电平在正常情形为第一电平(以高电平为例),当南桥将信号LDTSTOP#的电平拉低为第二电平时(以低电平为例),此称为设定(assert)信号LDTSTOP#,而当处理器10以及北桥14皆接收到设定(assert)的信号LDTSTOP#时,则LDT总线12中断联机。 LDTSTOP # signal level in normal circumstances for the first level (high level, for example), when the signal LDTSTOP # Southbridge level down to the second level (at a low level, for example), this called set (assert) signal LDTSTOP #, and when the processor 10 and 14 are received Northbridge set (assert) LDTSTOP # signal, then the LDT bus line 12 interrupts. 此时,南桥18内部的计数器19开始计数,待达到一既定值后,则南桥将信号LDTSTOP#的电平再恢复为原本的第一电平(高电平),此称为解除(deassert)信号LDTSTOP#。 At this point, the south bridge 18 internal counter 19 starts counting, after a predetermined value to be reached, the Southbridge LDTSTOP # signal and then restored to the level of the original first level (high level), this is called the release ( deassert) signal LDTSTOP #. 当处理器10以及北桥14皆接收到解除(deassert)的信号LDTSTOP#时,则LDT总线12重新联机,以套用新的LDT总线操作频率以及频宽,或者是处理器的操作电压与频率。 When the processor 10 and 14 are received Northbridge lift (deassert) LDTSTOP # signal, then the LDT bus 12 back online, to apply the new LDT bus operating frequency and bandwidth, or the operating voltage and frequency of the processor.

图2示出了传统LDT I/O总线的频宽与操作频率最佳化的操作流程图。 Figure 2 shows a conventional LDT I / bandwidth and operating frequency optimized operation flowchart O bus. 首先,在系统电源启动后,由基本输入/输出系统(Basic Input/OutputSystem,BIOS)初始(initialize)LDT总线的启始设定,包括设定处理器与北桥之间的LDT总线的总线启始频宽与总线启始频率以及最佳化时的总线操作频宽与操作频率(S1)。 First, after the system power-up, the basic input / output system (Basic Input / OutputSystem, BIOS) initial (initialize) starting LDT bus setting, including settings between the processor and Northbridge LDT bus bus initiation initiating bus bandwidth and bus bandwidth and operating frequency operating frequency and optimized when (S1). 举例来说,在计算机系统启动后,总线启始频宽可为8位,但最佳化时可调整为16位。 For example, after the computer system starts, starting bus bandwidth for eight, but the best of the time can be adjusted to 16. 再者,总线启始频率可为200MHz,但可最佳化为400MHz、600MHz或800MHz等频率。 Furthermore, the bus starting frequency for 200MHz, but the best into 400MHz, 600MHz or 800MHz and other frequencies. 上述最佳化时的总线操作频宽与操作频率设定于BIOS中。 Bus operation frequency of said bandwidth and optimizing operation when set to the BIOS. 接下来,BIOS依序初始处理器以及包含北桥以及南桥的芯片组的电源管理缓存器,并设定最佳化时的总线操作频宽与操作频率(S2)。 Next, BIOS sequentially initial processor and chipset power management register contains the Northbridge and Southbridge, and set the bus operation frequency bandwidth and optimizing operation when (S2). 接下来,BIOS于南桥启动一自动恢复(Auto Resume)的计数器(S3),接下来,BIOS并发出读取指令至南桥的输入输出端口(PowerMana gement I/O,PMIO)偏移15th以设定(asserting)信号LDTSTOP#(S4)。 Next, BIOS in Southbridge start an automatic recovery (Auto Resume) of the counter (S3), the next, BIOS and issuing a read command to the Southbridge 15th input and output ports (PowerMana gement I / O, PMIO) offset to setting (asserting) signal LDTSTOP # (S4). 在此,对信号LDTSTOP#执行设定的操作是将原本为高电平的信号LDTSTOP#转换为低电平信号。 In this case, the implementation of the set of operations on the signal LDTSTOP # is the original high signal LDTSTOP # converted to low-level signals. 当南桥将信号LDTSTOP#设定为低电平时,则位于处理器以及北桥之间的LDT总线即中断连接(S5)。 When the signal LDTSTOP # Southbridge is set to low, then located between the processor and Northbridge LDT bus that is disconnected (S5).

接下来,当于步骤S3所启动的计数器的计数值达到一既定值时,则南桥将信号LDTSTOP#解除(deassert)为高电平(S6),亦即将先前设定为低电平的信号LDTSTOP#恢复为高电平。 Next, when the count value of the counter is initiated in step S3 reaches a predetermined value, the Southbridge will signal LDTSTOP # lift (deassert) is high (S6), that is, the previously set to a low level signal LDTSTOP # restore high. 当信号LDTSTOP#重新恢复为高电平后,则位于处理器以及北桥之间的LDT总线即恢复连接(S7),并根据于先前BIOS所设定的最佳化的总线操作频宽与操作频率作为重新联机后的LDT总线的操作频宽与频率,完成了LDT I/O总线的频宽与操作频率的最佳化。 When the signal is restored LDTSTOP # is high, are located in the processor bus and the LDT is restored connection between the Northbridge (S7), and according to the best operation of the bus bandwidth and operating frequency to the previously set BIOS As the operating frequency bandwidth and back online after the LDT bus, complete LDT I / O bus bandwidth optimization and operating frequency.

上述总线最佳化程序,必须藉由执行LDT总线的中断以及重新联机的操作才能完成调整总线的频宽与操作频率的操作。 Best of the bus line, you must complete the bandwidth to adjust the operating frequency of the bus by LDT bus and interrupt the execution of operations to back online. 然而,若LDT总线的中断以及重新联机的操作未完全执行,则总线的状态并不会改变,无法达到将总线最佳化的效果,因此导致系统效能无法有效提升。 However, if the LDT bus and interrupt operations back online is not fully executed, the state of the bus does not change, can not reach the bus optimal results, thus resulting in system performance can not be effectively improved.

然而,传统技术在判断总线是否已完成最佳化程序上,遭遇了许多困难。 However, conventional techniques to determine whether the bus is on the optimization procedure has been completed, encountered many difficulties. 以软件而言,软件工程师几乎无法确定总线是否已完成最佳化程序。 In software, the software engineer is almost impossible to determine whether the bus has completed the optimization process. 以硬件而言,系统工程师必须利用示波器的探针直接检测输出信号LDTSTOP#的接脚的电平变化来判断总线是否已完成最佳化程序,此检测操作相当的麻烦。 In terms of hardware, the system engineer must use the level change of the oscilloscope probe directly detected output signal LDTSTOP # pins to determine whether the bus optimization procedure has been completed, the detection operation considerable trouble. 再者,纵使已检测到输出信号LDTSTOP#的接脚的电平被设定(assert)以及解除(deassert),若南桥18与处理器10或北桥14其中任何一者的电路联机发生断路的情形,则处理器10与北桥14无法同时接收到被设定(assert)以及解除(deassert)的信号LDTSTOP#,因此总线的频宽与操作频率仍然不会最佳化。 Furthermore, even if the output signal has been detected LDTSTOP # of pin level is set (assert) and release (deassert), if the processor 10 or 18 Southbridge Northbridge 14 any one circuit breaker happen online case, the processor 10 and 14 can not be received simultaneously Northbridge is set (assert) and release (deassert) signal LDTSTOP #, so the operating frequency of the bus bandwidth is still not optimal.

发明内容 SUMMARY

有鉴于此,为了解决上述问题,本发明主要目的是提供一种总线最佳化验证方法,以确认信号LDTSTOP#被设定(assert)以及解除(deassert)的程序完全被执行完毕,以避免计算机系统因为总线未被最佳化而导致整体系统效能不佳的情形。 In view of this, in order to solve the above problems, the main object of the present invention to provide a bus optimization authentication method, to confirm that the signal LDTSTOP # is set (assert) and releasing (deassert) the program is completely finished, in order to avoid computer system because the bus is not the best situation and lead to poor overall system performance.

为实现上述的目的,本发明提出一种处理器总线最佳化验证方法。 To achieve the above object, the present invention proposes a processor bus optimization authentication method. 首先,设定处理器与北桥之间总线的总线启始频宽与总线启始频率以及总线操作频宽与总线操作频率,设定该总线的最佳化操作频宽与最佳化操作频率;接下来,发出读取南桥的指令,接下来,南桥输出总线中断处理器与北桥芯片组之间的总线的连线,并启始计数器的计数值以及输出具有第一电平的最佳化验证信号。 First, set the bus between the processor and Northbridge bus starting starting frequency bandwidth and bus bandwidth and bus operations and bus operating frequency is set to optimize the operating bandwidth and optimize the operating frequency of the bus; Next best, issuing a read command Southbridge, then, Southbridge output bus Disconnected bus between the processor and the Northbridge chipset, and starts the count value of the counter and the output has a first level Validation signal. 当计数器的计数值累积达一既定值,则南桥输出总线连接信号,并将上述最佳化验证信号的电平转换为第二电平。 When the count value of the counter accumulated to a certain level, the Southbridge output bus connection signal and convert the above optimal level verification signal is the second level. 最后,总线根据总线连接信号以及第二电平的最佳化验证信号而重新连接处理器与北桥,并工作于最佳化总线操作频宽与最佳化总线操作频率。 Finally, the bus and the processor and Northbridge reconnect signal and a bus connection according to the second level verification signal optimization, and to work in the best operating bandwidth of the bus and the bus operation frequency optimization.

为使本发明的上述目的、特征和优点能更明显易懂,下文特举一较佳实施例,并结合附图详细说明如下。 For the above object, features and advantages of the present invention can be more fully understood, the following special lifting a preferred embodiment, the following detailed description in conjunction with the accompanying drawings.

附图说明 Brief Description

图1示出了传统具有LDT总线的计算机系统架构图。 Figure 1 shows a diagram of a conventional computer system architecture has the LDT bus.

图2示出了传统LDT I/O总线的频宽与操作频率最佳化的操作流程图。 Figure 2 shows a conventional LDT I / bandwidth and operating frequency optimized operation flowchart O bus.

图3示出了根据本发明实施例所述的具有LDT总线的计算机系统架构图。 Figure 3 illustrates a computer system architecture diagram with LDT bus according to the present embodiment of the invention herein.

图4示出了根据本发明实施例所述的电平检测电路的电路图。 Figure 4 shows a circuit diagram according to an embodiment of the present invention, the level detection circuit.

图5示出了根据本发明实施例所述的处理器总线最佳化验证方法的操作流程图。 Figure 5 shows a flowchart of the operation of the processor bus authentication method according to the preferred embodiment of the invention claimed.

符号说明10~处理器12~LDT总线14~北桥16~总线18~南桥21~电平检测电路LDTSTOP#~信号具体实施方式参阅图3,图3示出了根据本发明实施例所述的具有LDT总线的计算机系统架构图。 Description of Reference Numerals 10 ~ 12 ~ LDT processor bus 16 to the bus 14 to the north bridge 18 to the south bridge 21 to the level detection circuit LDTSTOP # ~ signal DETAILED DESCRIPTION Referring to Figure 3, Figure 3 shows the embodiment according to the present invention, LDT bus with a computer system architecture diagram. 如图所示,处理器20与北桥24之间具有一LDT总线22,或称HT总线。 As shown, having a LDT bus 22 between processor 20 and the north bridge 24, also known as HT bus. 在此,处理器20是以AMD所制造的K8CPU为例。 In this case, the processor 20 is manufactured by AMD K8CPU example. 而北桥24与南桥28之间具有另一总线26。 Southbridge and Northbridge have between 24 and 28 other bus 26. 当要执行总线最佳化程序时,位于处理器20与北桥24之间的LDT总线22必须执行中断以及重新联机的操作,上述操作受到南桥28所输出的信号LDTSTOP#的电平变化所控制。 When you want the best of the bus program, located between the processor and Northbridge 24 20 22 LDT bus must execute the interrupt and re-line operation, the above operation by LDTSTOP # signal output level change control Southbridge 28 . 信号LDTSTOP#的电平在正常情形为第一电平(以高电平为例),当南桥29将信号LDTSTOP#的电平拉低为第二电平时(以低电平为例),此称为设定(assert)信号LDTSTOP#,则LDT总线22中断联机。 LDTSTOP # signal level in normal circumstances for the first level (high level, for example), when Southbridge LDTSTOP # 29 will signal the level down to the second level (at a low level, for example), This is called signal LDTSTOP # set (assert), the LDT bus line 22 interrupts. 此时,南桥28内部的计数器29开始计数,待达到一既定值后,则南桥将信号LDTSTOP#的电平再恢复为原本的第一电平(高电平),此称为解除(deassert)信号LDTSTOP#,则LDT总线22重新联机,以套用新的LDT总线操作频率以及频宽。 At this time, the internal counter 29 Southbridge 28 starts counting, after a predetermined value to be reached, the Southbridge LDTSTOP # signal and then restored to the level of the original first level (high level), this is called the release ( deassert) signal LDTSTOP #, the LDT bus 22 back online, to apply the new LDT bus operating frequency, and bandwidth.

再者,根据本发明实施例所述的总线最佳化验证方法,增设一信号电平检测电路21来判断信号LDTSTOP#是否已执行设定(assert)以及解除(deassert)的程序。 Furthermore, optimization of the bus authentication method according to an embodiment of the present invention, the addition of a signal level detecting circuit 21 determines whether the signal LDTSTOP # set (assert) and releasing (deassert) procedures have been performed.

图4示出了根据本发明实施例所述的电平检测电路21的电路图。 Figure 4 shows a circuit diagram of the level detection circuit according to the present invention is described in Example 21. 根据本发明实施例所述的电平检测电路21包括一触发器40,以及耦接于触发器40的D端子的或逻辑门42。 Level detecting circuit according to an embodiment of the present invention 21 comprises a flip-flop 40, and an OR logic gate coupled to the D terminal of flip-flop 40. 42. 在此电平检测电路21中,系统在或逻辑门42的输入端42A输入逻辑电平“1”的信号,此时于触发器40的Q端子输出逻辑电平“1”的信号LSTSTOP_STATUS。 In this level detection circuit 21, the system logic gate 42 in the input or end 42A input logic level "1" signal, this time in the flip-flop Q output terminal 40 is a logic level "1" signal LSTSTOP_STATUS. 当触发器40的RST端子所接收的信号LDTSTOP#由低电平上升到高电平时,则触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平清除为“0”。 When the RST terminal of the flip-flop 40 of the received signal LDTSTOP # rises from low level to high level, the signal output terminal Q LSTSTOP_STATUS trigger 40 is cleared to logic level "0." 由于信号LDTSTOP#的电平于正常情况下系保持于高电平,当信号LDTSTOP#被设定(assert)为低电平,再被解除(deassert)为高电平时,触发器40的Q端子所输出的信号LSTSTOP_STATUS的逻辑电平才会为“0”。 Since the signal level at LDTSTOP # normally lines were maintained in a high level, when the signal LDTSTOP # is set (assert) is low, and then is released (deassert) is high, Q terminal of the flip-flop 40 The output signal of the logic level will LSTSTOP_STATUS "0." 因此,藉由检测触发器40的Q端子所输出的,即可判断信号LDTSTOP#完成执行设定(assert)以及解除(deassert)的程序。 Therefore, by detecting terminal 40 of the flip-flop Q output, you can determine the signal LDTSTOP # completes execution set (assert) and release (deassert) program.

再者,关于电平检测电路21所设置的位置可置于南桥20的输出端,以及处理器20和北桥24接收信号LDTSTOP#的输入端,如图3所示。 Furthermore, with regard to the position set by the level detection circuit 21 may be placed Southbridge output terminal 20, and a processor 20 and a north bridge 24 receives an input signal LDTSTOP #, as shown in FIG. 另外,根据本发明实施例图4中所示的电平检测电路的电路结构仅为一较佳实施例,然而,检测信号LSTSTOP_STATUS逻辑电平的操作同样也可利用其它电路来实现,并不限定于图4中所示的电平检测电路结构。 Further, according to embodiments of the present invention showing a circuit configuration of the level detection circuit shown in Figure 4 is only a preferred embodiment, however, the logic level of the detection signal LSTSTOP_STATUS operation can also be implemented using other circuitry, not limited level detection circuit structure shown in Fig.

图5示出了根据本发明实施例所述的处理器总线最佳化验证方法的操作流程图。 Figure 5 shows a flowchart of the operation of the processor bus authentication method according to the preferred embodiment of the invention claimed. 根据本发明实施例,首先,在系统电源启动后,由基本输入/输出系统(Basic Input/Output System,BIOS)初始(initialize)LDT总线的启始设定,包括设定处理器与北桥之间的LDT总线的总线启始频宽与总线启始频率以及最佳化时的总线操作频宽与操作频率(S21)。 According to the present embodiment of the invention, first of all, after the system power-up, the basic input / output system (Basic Input / Output System, BIOS) initial (initialize) Kai LDT bus start setting, including settings between processors and Northbridge The LDT bus bandwidth of the bus starting the bus and the bus operation starting frequency and the operating frequency bandwidth optimization when (S21). 举例来说,总线启始频宽可为8位,但最佳化时可调整为16位。 For example, the bus bandwidth can initiate 8, but can be adjusted to optimize the time 16-bit. 再者,总线启始频率可为200MHz,但可最佳化为400MHz、600MHz或800MHz等频率。 Furthermore, the bus starting frequency for 200MHz, but the best into 400MHz, 600MHz or 800MHz and other frequencies. 上述最佳化时的总线操作频宽与操作频率系设定于BIOS中。 Bus bandwidth and operating frequency system operating above optimal when setting in the BIOS. 接下来,由BIOS依序初始处理器以及包含北桥以及南桥的芯片组的电源管理缓存器,以处理相关的电源设定(S22)。 Next, an initial sequence by the BIOS and chipset processor power management register contains the Northbridge and Southbridge, to handle the associated power settings (S22). 接下来,BIOS将处理器与北桥之间的LDT总线的总线最佳化的操作频宽与操作频率设定于缓存器中(S23),例如,将总线最佳化操作频宽设定为16位、将总线最佳化操作频率设定为800MHz。 Next, BIOS will optimize the operation of the bus and the operating frequency bandwidth between the processor and Northbridge LDT bus is set to buffer (S23), for example, will optimize the operation of the bus bandwidth is set to 16 bit bus optimal operating frequency is set to 800MHz. 接下来,BIOS于南桥启动一自动恢复(Auto Resume)的计数器(S24)。 Next, BIOS in the South Bridge start an automatic recovery (Auto Resume) of the counter (S24). 当自动恢复(Auto Resume)的计数器的计数值累计到一既定值时,则解除(deassert)信号LDTSTOP#。 When the count value is automatically restored (Auto Resume) counter accumulated to a predetermined value, then lift (deassert) signal LDTSTOP #.

接下来,在如图4所示的电平检测电路21的逻辑门42的输入端42A输入逻辑电平“1”的信号,使得触发器40的Q端子输出逻辑电平“1”的信号LSTSTOP_STATUS(S25)。 Next, as shown in Figure 4 the logic gate level detection circuit 21 input 42 input 42A of the logic level "1" signal terminal, so that the Q terminal of the flip-flop 40 outputs a logic level "1" signal LSTSTOP_STATUS (S25). 接下来,BIOS发出读取指令至南桥的输入输出端口(Power Management I/O,PMIO)偏移15th以设定(asserting)信号LDTSTOP#(S26)。 Next, BIOS issues a read command to the Southbridge input and output ports (Power Management I / O, PMIO) offset 15th to set (asserting) signal LDTSTOP # (S26). 在此,对信号LDTSTOP#执行设定的操作是将原本为高电平的信号LDTSTOP#转换为低电平信号。 In this case, the implementation of the set of operations on the signal LDTSTOP # is the original high signal LDTSTOP # converted to low-level signals. 当南桥将信号LDTSTOP#设定为低电平时,则位于处理器以及北桥之间的LDT总线即中断连接(S27)。 When the signal LDTSTOP # Southbridge is set to low, then located between the processor and Northbridge LDT bus that is disconnected (S27).

接下来,当在步骤S24所启动的计数器的计数值达到一既定值时,则南桥将信号LDTSTOP#解除(deassert)为高电平(S28),亦即将先前设定为低电平的信号LDTSTOP#恢复为高电平。 Next, when the count value reaches a predetermined value of the counter in step S24 starts, the South Bridge would signal LDTSTOP # lift (deassert) is high (S28), i.e., the previously set to a low level signal LDTSTOP # restore high. 当信号LDTSTOP#解除(deassert)为高电平后,由于信号LDTSTOP#耦接于电平检测电路21的的RST端子,因此触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平清除为“0”(S29)。 When the signal LDTSTOP # lift (deassert) after a high level, since the signal LDTSTOP # is coupled to the RST terminal of the level detection circuit 21, and therefore the flip-flop 40 Q output terminal of the logic level of the signal LSTSTOP_STATUS cleared to "0 "(S29). 接下来,检测触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平(S30),以判断信号LDTSTOP#是否已完成设定(assert)以及解除(deassert)的完整程序。 Next, the detection of the trigger signal LSTSTOP_STATUS Q output terminal 40 of the logic level (S30), to determine whether the signal LDTSTOP # has completed setting (assert) and release (deassert) the complete program. 接下来,处理器判断触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平是否为“0”(S31),若不为“0”,则回到步骤S30,继续检测触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平。 Next, the processor determines the logic level of the signal LSTSTOP_STATUS output terminal Q of the flip-flop 40 whether the "0" (S31), if it is "0", the flow returns to step S30, continues to detect the Q terminal of the flip-flop 40 LSTSTOP_STATUS signal output logic levels. 若于步骤S31的判断出LSTSTOP_STATUS的逻辑电平为“0”,则位于处理器以及北桥之间的LDT总线即恢复连接,并根据于先前BIOS所设定的最佳化的总线操作频宽与操作频率作为重新联机后的LDT总线的操作频宽与频率(S32),完成了LDT I/O总线的频宽与操作频率的最佳化。 If the determination in step S31 in the LSTSTOP_STATUS logic level "0", are located between the processor and Northbridge LDT bus, i.e. the connection is restored and BIOS according to the previously set optimum operation of the bus bandwidth and As the operating frequency back online after LDT bus bandwidth and operation frequency (S32), to complete the LDT I / O bus and the optimization of operating frequency bandwidth.

根据本发明实施例所述的处理器总线最佳化验证方法,藉由检测设置于南桥的电平检测电路21所输出的LSTSTOP_STATUS的逻辑电平即可判断信号LDTSTOP#是否已完成设定(assert)以及解除(deassert)的完整程序。 According to the processor bus optimized verification method described embodiments of the invention, by detecting the level set in Southbridge detection circuit 21 LSTSTOP_STATUS output logic level signal LDTSTOP # to determine whether the setting has been completed ( assert) and release (deassert) the complete program. 再者,若在北桥或者处理器于接收信号LDTSTOP#的输入端处设置电平检测电路,还可确保完成设定(assert)以及解除(deassert)完整程序的信号LDTSTOP#正常连接至北桥或者处理器,确认位于北桥以及处理器之间的总线能够遵循信号LDTSTOP#电平的变化确实完成中断联机以及恢复联机的操作。 Furthermore, if the set level detection circuit in Northbridge or processor LDTSTOP # received signal at the input, but also to ensure the complete set (assert) and release (deassert) complete program signal LDTSTOP # properly connected to the Northbridge or processing is confirmed and a processor bus between the North Bridge to follow the signal level changes LDTSTOP # indeed complete interrupt line and back online operation.

本发明虽以较佳实施例披露如上,然其并非用以限定本发明的范围,本领域的技术人员在不脱离本发明的精神和范围的前提下,可做若干的更动与润饰,因此本发明的保护范围以本发明的权利要求为准。 Although the present invention is to disclose the preferred embodiments described above, however it is not intended to limit the scope of the invention, those skilled in the art without departing from the spirit and scope of the present invention is the premise to do a number of modifications and variations, therefore The scope of the invention to the claimed invention shall prevail.

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Classifications
Classification internationaleG06F13/38
Événements juridiques
DateCodeÉvénementDescription
29 déc. 2004C06Publication
2 mars 2005C10Request of examination as to substance
28 févr. 2007C14Granted