CN1319149C

CN1319149C - Double metal/polycrystalline oxide nitride oxide silicon memory unit for wide programing

Info

Publication number: CN1319149C
Application number: CNB02126452XA
Authority: CN
Inventors: 大仓世纪; 大仓智子
Original assignee: Harlow Co
Current assignee: Harlow Co
Priority date: 2002-07-19
Filing date: 2002-07-19
Publication date: 2007-05-30
Anticipated expiration: 2022-07-19
Also published as: CN1469455A

Abstract

The present invention relates to a method for selecting storage cells, and operation for obtaining wide programming bandwidth and EEPROM erasing performance. In a reading period, two storage areas in one storage cell can be simultaneously selected; furthermore, in a programming period, an energy source generating current flow can be dynamically obtained from stored electric charges on bit lines which are selected; if the capacitance of the bit lines fail to provide enough required electric charges, the capacitance of additional bit lines is borrowed form the bit lines which are not selected, or an output transistor in a source electrode can be used.

Description

Bimetallic/the polycrystalline oxide nitride oxide silicon memory unit that is used for wide programing

Technical field

The present invention relates to non-volatile memory storage, and be particularly related to the MONOS memory.

Background technology

Two MONOS memory cells are exposed in United States Patent (USP) the 6th recently, 255,1662B1 number (Ogura etc.) (being method) at a kind of Nonvolatile memery unit and memory array and a kind of its programming, United States Patent (USP) the 6th, 248,633B1 number (Ogura etc.) (are at a kind of manufacturing, programming and the process of operating a dibit multilayer trajectory MONOS memory), U.S. patent application case the 09/595th, No. 059 (filing an application March 19 calendar year 2001) (is at Nonvolatile memery unit and memory array, and method of operation), and in the 10/005th, No. 932 (file an application December 5 calendar year 2001) (being array organization and method of operation) of U.S. patent application case at nonvolatile memory.Figure 1A and Figure 1B are the schematic diagrames that shows two kinds of MONOS type memories, Figure 1A show the diffusion bit architecture, and Figure 1B show a metal bit architecture, in the memory array of arbitrary form, bit line vertically is connected with the diffusion region, position of memory cell, and is separated by the transistor of three series connection: a control grid memory transistor, a word grid are chosen transistor, are reached another control grid memory transistor.The word grid is as a memory cell selector, and used jointly by neighbor memory cell, be connected to the word gate level with word line, control gate has bottom nitrogen oxide (ONO) film, its may trapped electrons with storage data, but control grid trapped electrons in two respective areas and is represented it by two each other transistors, but its grid physical property ground or link together electrically is to share identical control gate pole tension.

Fig. 2 is the drawing in side sectional elevation that shows a word line, in an independent memory cell (unit 1), have a control grid CG1, reach a diffusion region BL1, reach two half-word grids, under control grid CG1, have two memory nitride storage area (NSS) M2 and M3, electronics is injected in the storage area, contains the limit voltage of M2 and M3 element with raising, and carries out the storage area programming thus.Because the nitride storage area and the channel region of bottom are very short, so the injection device of two MONOS unit is referred to as trajectory channel hot electron (CHE), electronics injects and has very high efficient, progression about 1E-4, it is because short channel provides the energy attenuation of less duplet electron scattering, and the conventional flat floating grid elements of more use CHE have the injection efficiency of 1E-6 to 1E-10 progression.During programming, be to need high-tensionly, these high voltages are by charge pump circuit provided.The high program current that the conventional feature of using the element of CHE is a 100uA/ unit progression, and 10 programming times to hundreds of microseconds.The element number of disposable programmable is limited; Therefore, element number is limited by the charge pump maximum current.

In order to remove (threshold value that it reduces memory cell (CELL1)), between control grid CG1 and position diffusion region BL1, apply a high electric field, so that induction Fu Le-Nuo Dehan tunnelling (FN) or hot hole inject or its combination, and be passed in the oxide between nitride and diffusion region.In this step, the negative voltage of a pact-2V puts on the control grid CG1, and the positive voltage of an about 4V puts on the diffusion region BL1, in being shown in the memory array tissue of Fig. 1, there are two nitride storage area M2 and M3 (it shares identical control grid CG1 and identical bits diffusion region BL1) in an operation, to be eliminated together usually.

Yet, in programming operation, sharing two nitride storage areas of identical control grid and identical bits diffusion region, can individually be programmed mutually.The programming state embodiment of two MONOS memory array profiles is provided in Fig. 3, that has chosen memory cell (CELL1) in order to programme chooses right nitride storage area M3, then will control grid CG1 brings up to+5V, the voltage of position diffusion region BL1 is determined by programming data, usually, bit line is connected to a programming data latch, if when wanting programming unit to a logic " 0 ", then diffusion region BL1 is brought up to+5V, otherwise, if when programming data was a logic " 1 ", then the voltage of BL1 was 0V, with adjacent right position line BL2 ground connection.When word line voltage is brought up to the voltage of about 1.2V, will open at the raceway groove under the word grid, and inject electronics to the nitride of choosing storage area M3 from raceway groove.In order to be suppressed at the programming of the same memory unit (CELL1) Nei Zuo district storage area M2, when the threshold value of M1 storage area greater than 0 the time, with left adjacent bit lines BL0 and adjacent left side control grid CG0 ground connection, between BL0 and BL1, flow to prevent electric current.

Yet, even the small amount of current between BL0 and BL1 can cause a serious programming disturbance state, for this reason, if have any the M1 storage area may be become a unit of finishing removing with a negative limit voltage time, for the BL0 that closes the word grid element to the BL1 electric current, preferably the voltage of BL0 is brought up to word grid voltage (about 1.2V).

During programming, when being programmed in nitride storage area in the memory cell, with two control grid CG[N] and CG[N+1] bring up to 3V and 5V respectively, in order only to isolate the programming of having chosen the nitride storage area to one, must be with adjacent control grid CG[N-1] and CG[N+2] ground connection.As described pair of MONOS memory array of routine; minimum control gate decoder must be four unit; the minimum bitline decoding unit also is four unit; and the adjacent bit lines of having chosen the unit the next-door neighbour need be brought up near word line voltage, so that prevent an excessive clearing cell electric current in order to protect during programming.

Fig. 4 is provided at the voltage status embodiment of memory cell (CELL1) during the removing, and the negative voltage of a pact-2V puts on the control grid CG1, and the positive voltage of an about 5V puts on the bit line BL1, electronics is stored from nitride layer be ejected on the bit line.U.S. patent application case the 10/005th, No. 932 (filing an application) December 5 calendar year 2001, it is the device that to remove at other, as removing in conjunction with the auxiliary hot hole of word line voltage, become a negative voltage and another word line bias voltage is become a positive voltage by choosing the word line bias voltage, can quicken to have chosen the removing action of word line and suppressed not alternative line, therefore, this becomes might selective clearing and a byte or even the same little data recruitment in a single memory unit.

The feature of short channel nitride storage area (being implemented in two MONOS unit) is to have high programming efficiency and elimination efficiency.

Summary of the invention

One of the present invention main purpose is to choose two nitride storage areas that are contained in the MONOS memory cell simultaneously, to be used to read, programme, reach clear operation.

Another object of the present invention is that programming is contained in the nitride storage area in the MONOS memory cell.

The present invention's another purpose is to programme simultaneously to be contained in a plurality of nitride storage area in the MONOS unit.

The present invention's another purpose is to use bit line capacitance, so that the electric charge of a programming operation to be provided.

The present invention's another purpose is to use bit line selector grid to export as one source pole, with the control storage cell drain, and reduces the required bit line capacitance that needs supply memory areas programming cell current.

The present invention's another purpose is to use bit line selector grid, selecting time bit line, and reduces bit line capacitance.

The present invention's another purpose is to use a high voltage that reduces bit line capacitance, with the nitride storage area of programming MONOS memory cell.

The present invention's another purpose is to use the electric charge on the bit line capacitance, by the required a part of program current of feeding unit, augmenting a high voltage source or charge pump, and therefore reduces the required electric current of charge pump or high voltage source.

The present invention's another purpose is never to choose to use electric capacity in the bit line, producing enough electric capacity, and provides the total electrical charge of a programming operation.

The present invention's another purpose is to cut off the bit line source of bit line of will programming, and uses bit line charge then, with programming a pair of MONOS memory cell district.

The present invention introduces the novel method of a kind of memory unit and usage, wherein can be in an operation two nitride storage areas in the program memory cells respectively, pass through the method, programming step compared to prior art, because the minimum unit of decoding changes to two unit from four unit, multiplicable programming width.

The method of an improvement program bandwidth comes from the use of array organization.This improved process of realization is provided.Can in independent operation, programme severally two nitride storage areas in the single memory unit, it is to be calibrated to a high voltage by the bit-line voltage that will choose the unit, and determine the voltage status of the left and right adjacent bit lines on the programming data then, therefore, can be programmed in two neighbor memory element under the identical control grid severally, double program bandwidth at once compared to the prior art programmed method.

Determine program bandwidth divided by the quotient of program speed by data width, in order to improve program bandwidth, this need increase programmed cells quantity at once, and time of reducing programming, the invention provides the method for improving program bandwidth.

The charge pump current restriction can cause the general restriction of program bandwidth, because of the relation of the high injection efficiency of two MONOS elements can prevent, moreover, the programming data latch need not output HIGH voltage, it can reduce circuit complexity, the use that source electrode output or drain current are written into element during programming also is control and the method that reduces required program current, and the charge pump of distortion is diminished in order to the agretope line current.

Apply a voltage to adjacent not the choosing on the unit of unit chosen, a current source is provided, one chosen the unit to programme, when the bit line of adjacent cells is about 0V, an electric current will reach between the bit line of not choosing the unit at the bit line of choosing the unit and flow, therefore, the nitride storage area in the unit has been chosen in programming, and it is higher than Current Zone.When the adjacent bit line of not choosing the unit is about or is higher than word line voltage, the nitride storage area that will not have electric current and can not programme and choose the unit then.

The electric capacity of bit line is used to provide the source of a high-energy electron, storage area with programming MONOS memory cell, do not choose being capacitively coupled to of bit line and one chosen bit line, so that the energy of enough programmings one storage area to be provided, this finishes by using the bit line grid, this bit line grid is selected a plurality of parts of bit line, and provides to share and do not choose bit line and chosen the electric capacity of bit line, not can be used for providing the programming that is connected to the memory cell of choosing bit line energy so that choose the electric capacity of bit line.

The bit line of electric current with program memory cells is provided, at first charging becomes a high voltage, a switch gate that connects electric charge source electrode and bit line can be opened, and the electric charge on bit line is used for the nitride storage area of program memory cells, if bit line charge is not to use conduct with the total source electrode of the high-energy electron of program memory cells, bit line charge can be used for reducing the electric current that needs the high voltage source electrode, moreover, switch gate can be used for exporting as one source pole, voltage with the control bit line, it provides the bigger tolerance limit of the voltage fluctuation of high voltage source electrode, and still keep excellent controlled, these controlled and dynamic electric voltage charging notions further extend to clear operation and multilayer programming.

Description of drawings

The feature of method of the present invention and advantage will more clearly be understood by the explanation of following conjunction with figs., include:

Figure 1A is the structural representation that shows the prior art structure of a part of memory or MONOS memory cell, is arranged as a bit line structure.

Figure 1B is the structural representation that shows the prior art structure of a part of memory or MONOS memory cell, is arranged as a metal wire structure.

Fig. 2 is the drawing in side sectional elevation that shows the row of prior art memory cell.

Fig. 3 is the drawing in side sectional elevation that shows the row of prior art memory cell, the voltage status that reaches programming operation.

Fig. 4 is the drawing in side sectional elevation that shows the row of prior art memory cell, the voltage status that reaches clear operation.

Fig. 5 A is the drawing in side sectional elevation that shows the row of the voltage status of programming operation of the present invention and memory cell.

Fig. 5 B shows the structural representation of implementing dynamic programming notion of the present invention.

Fig. 6 is the structural representation that shows the present invention, and bit line is subdivided into bit line selection transistor.

Fig. 7 is drawing in side sectional elevation, and the voltage status of clear operation of the row of display-memory unit, is used to protect programming of the present invention to disturb.

Fig. 8 be the hardware result that shows word grid voltage efficient, and the final programming of the present invention face the program current of limit.

Fig. 9 shows that a constant-current supply is connected to a bit line of the present invention, with need the programme electric current of a unit of assist control.

Figure 10 A is the drawing in side sectional elevation of demonstration one around the zone of storage area of the present invention.

Figure 10 B is to show electron distributions and at the structural representation of the CHE temperature of a control grid bias 5V to 10D.

Figure 11 A figure and 11B are the positions of the CHE temperature of display capture electron distributions and control grid bias 6.5V.

Embodiment

During removing, programme and reading, two nitride storage areas in a single memory unit, can select simultaneously as a unit, one single memory unit can be as being eliminated as the description of the Prior Art, in addition, because storing, short channel nitrogenize district has very high elimination efficiency, so checkout time is very fast, and can allow them float then by just reaching negative voltage and dynamically carry out it choosing to apply respectively on bit line and the control gate line.

In a single operation, read two districts severally, it is to adjust to a low-voltage by the bit-line voltage that will choose the unit, and apply one on the grid and select voltage choosing control, with the control grid that crushes adjacent, and improve the word grid voltage then with the unit.Choosing two bit-line voltages or the electric current of bit line both sides, can monitor out by two other sense amplifiers, to determine the memory state of two storage areas.

Two storage areas in a single memory unit also can be in a single operation and be programmed individually, and it is to adjust to a high voltage by the bit-line voltage that will choose the unit, determines the voltage status on a left side and right adjacent bit lines on the programming data then.Fig. 5 A figure is the voltage status that is presented at two the nitride storage areas of programming simultaneously in a pair of MONOS memory cell, corresponding Fig. 5 B that is shown in that the diffusion bit array carries out, wherein M0, M1, M2, M3, M4, M5, M6, and M7 be the nitride storage area of unit, be connected to a word line WM0 and have bit line BL0, BL2 and BL3, and control grid CG0, CG1, CG2, and CG3.Memory cell (unit 1) is for choosing the unit, and it includes nitride storage area M1 and M3.For M2 and the M3 of will programming, a high voltage (5V) puts on the CG1, and a pressure is striden voltage (3V) and is put on CG0 and the CG2, bit line BL1 is brought up to a high voltage (5V), and decoder control other programming latch, according to the M2 of programming value and M3 and decide, to connect voltage respectively to BL0 and BL2.If when wanting data programmed to be a logic " 0 ", then the voltage of BL0 or BL2 is 0V, and in the time can using word line, then program current flows between 0V bit line and high voltage (5V).If data are when being a logic " 0 ", the bit-line voltage of BL0 and BL2 is set at a pact or greater than the voltage of selectivity word gate line WL0 voltage, it is in order to suppress program current.The bit-line voltage state of one logic " 1 " is considered " programming suppresses ".Bit line decoder can be controlled the bit-line voltage of BL0 and BL2 respectively, and the data of can programme in identical programming operation severally two nitride storage area M2 and M3.

It should be noted,, and not should be any form that is restricted in the voltage of this patent unless known relation clear and definite between voltage status is the approximation that is used for simplicity of explanation.

This threshold value that hangs down threshold value " 1 " unit can be reduced to one extremely low or even for negative value, be in order to increase the cell current of high-speed applications.In this excessive clearing cell, inferior facing limits electric leakage will become an important problem.Consult Fig. 7, when if storage area M6 may become the excessive removing with a negative threshold value, during adjacent cells (unit 1) programming, a small channel electric current or inferior threshold current even can increase threshold value or cause serious programming to disturb, because this reason, preferably bit line BL3 is brought up to and be higher than the word grid voltage ^-1.2V it can cause the negative-grid-source electrode bias voltage between word line and bit line BL3, and cuts off bit line BL2 to the BL3 current path.

Because the high injection efficiency of two MONOS unit, the required total electrical charge of programming operation is the progression of hundreds of electronics, this is one and discharges total amount of electric charge and memory finally face direct relation between spacing the moving during programming, at a small amount of micromicroampere program current and less than the program speed of microsecond, may be high injection rate, therefore, this may become the use bit line capacitance as the Charge Source that a required electronics injects, and makes the charge pump current restriction reduce to minimum.For example, if average program current is during 2uA and the programming during for 1usec, the electric capacity that then needs a 2pf, to guarantee that high bit-line voltage rests on the 5V 0.5V (C=1/dt/dV that adds deduct, wherein 1-5mA, dV=0.5V, and dt=1usec), calculate by this, bit line capacitance is enough to be provided at the required electric charge that injects during the programming, this notion is useful for standby flash memory system, and wherein data reliability is extremely important.If when the plant capacity accident was cut off suddenly, the store charge on chip can be enough to finish programming operation.

It is as follows to carry out the dynamic programming conceptual description, based on Fig. 5 B, Fig. 5 B shows a schematic diagram that carries out " dynamic programming " notion, wherein supply suitable voltage to bit line SBL0, SBL1 and SBL2, and control gate line CG0, CG1 and CG2 go up to be used for programming unit 1, it includes nitride storage area M2 and M3, derailing switch MSG0 and MSG2 connect 0V or 1.5V (shown in 5A figure) to bit line SBL0 and SBL2, and the bit line SBL1 of itself and unit 1 is adjacent.After applying voltage, can cut off one connect high bit-line voltage (+5V) to the derailing switch SGX of bit line SBL1, can produce programming and need not anyly further supply 5V to memory bit line SBL1, be because bit line capacitance Csb1 provides the electric charge of necessity.

The bit line capacitance that the present invention is absorbed in " dynamic programming " notion and " dynamically aided programming " notion uses.In " dynamically aided programming " notion, be stored in electric charge on the bit line and have a rule of replenishing, a high voltage source or a charge pump can be used for being provided at required high 5V during the programming, still, because bit line capacitance replenishes the electric current of charge pump, so need little electric current.

In second embodiment of the present invention, a smaller capacitive can be used with a high voltage and one source pole output, to control a transmission transistor, with in order to reduce required bit line capacitance, and increase the voltage fluctuation tolerance limit, Fig. 6 shows a schematic diagram, its neutrality line is subdivided into bit line selection transistor MSG0 again, MSG1 and MSG3, when high selection signal SGBL is arranged, bit line selection transistor MSG0, MSG1 and MSG3 respectively with inferior bit line SBL0, SBL1, connect between SBL2 and SBL3, and respectively with main bit line MBL0, MBL1, MBL2 and MBL3, except the function that inferior bit line is selected, select transistor MSG0, MSG1 and MSG3 can be used as source electrode output voltage limiting element.For example, apply 7V to the grid of bit line selection transistor with limit voltage 2V, the voltage that can limit time bit line is 5V or littler (Vgs-Vt), if main bit line (for example overcharges, to 7V) time, needing to stop time position only is 0.8pF (I=CdV/dt from total main bit line capacitor C mb that 4.5V descends, I=2uA, dv/dt=1usec/ (7-4.5)=2.5), 0.8pF main bit line electric capacity be significantly less than 2pF electric capacity, it does not need when using main bit line to overcharge the source electrode output intent, moreover, main bit line voltage fluctuation tolerance limit be 2.5V (=7-4.5) relative with the inferior bit-line voltage fluctuation tolerance limit of 5.0V.

In the 3rd embodiment of the present invention, another method that increases program bandwidth is to come to make the programming unit quantity of programming simultaneously increase to maximum, and it is limited by the current energy of program current and charge pump usually.Programmable features as element, it has the width of 0.4um, be shown in Fig. 8, when approaching the word grid, word voltage faces limit, program current can be lower than 1uA, program speed is slower when this low current, but can increase program current apace and be about a little micromicroampere, yet, if electric current increases when surpassing 30uA, then program speed begins to reduce, and according to these optimization hardware results not, the program current of a 2-3uA (about 5uA/um) can be the program current of the best, for a restriction electric current charge pump, so that want the quantity of programming unit to be increased to greatest extent, except being limited the electric current by foregoing low word line voltage, program current also can be controlled by a bit line current source.

Fig. 9 shows a step, the constant current supply of one of them is arranged on the end of two MONOS source bit line BL0, reference voltage Vref is supplied by a current source, it has been calibrated to optimal low program current, in the 4th embodiment of the present invention, when bit line capacitance does not enough meet the programming time, electric current, when reaching voltage, for fear of losing the zone because of extra capacitor, may adopt an electric capacity of not choosing bit line, though do not lose the zone because of extra capacitor, but bit line decoder need can: 1) connect together and chosen and do not chosen bit line, and 2) be close to the two-phase ortho position line of not choosing bit line and should bring up to one near the voltage of having chosen word grid voltage (about 1.2V), it is to suppress to connect the unit of non-selected bit line in order to programme, and its electric capacity is used.Be positioned at the number of unit of choosing and not choosing between bit line, need be at least four, by using the bit line capacitance borrowing method, minimum bitline decoder unit is eight unit.

In the 5th embodiment of the present invention, improve program speed and integral member reliability by controlling injection device electricity and electron distributions zone, at Figure 10 A is the drawing in side sectional elevation that shows the electron storage zone, with 5V bias voltage control grid and diffusion region, position, at Vds=5V, Vcg=5V, and on the Vword=1.0, the distribution of the electron temperature before electronics injects under the control grid is shown in the solid line of Figure 10 B, in this curve, highest energy slightly peaks in the n-knot, therefore, on the initial point that electronics injects, the trapped electrons in the nitride storage area distributes will be identical with Temperature Distribution, and the dotted line that shows along Figure 10 B, along with catching more electronics, the spike of electric field can improve, and further moves to right, shown in the solid line of Figure 10 C.Figure 10 D is presented at CHE Temperature Distribution and the electron distributions that the electron capture process is kept a period of time current source afterwards, appreciablely be, most of most electronics is hunted down in zone that n-ties, because the concerning that it does not effectively provide and face limit and move of high n concentration, moreover, when the close knot of decanting point edge, need consider the problem of wearing out bottom oxide.Yet, when an about Vcg＞ ^-6.5V high voltage (drain bias+Vt and include substrate sensitiveness) when putting on the control grid, the spike electric field moves to left, and is more close in the gap of word and control gate interpolar, shown in Figure 11 A.Higher control gate pole tension produces an electronics inverse thermal stratification near the gap, and it is trapped electrons in a better position, and it just in time is positioned on the control grid groove.The advantage of the control gate pole tension that another is higher is, spread all over channel region by filling trapping region, and avoid pin mark to pass, it provides preferable durability and reliability, therefore, the Vcg that use is higher than (Vd+Vt) provides preferable electron distributions, itself so that can cause preferable by feature and program speed and preferable durability faster.

Though the present invention is represented especially with reference to its preferred embodiment and is illustrated, it will be understood by a person skilled in the art that and can carry out the various changes that reach in form on the details in spirit that does not deviate from the present invention and category.

Claims

One kind in a MONOS memory cell programming a plurality of storage areas method, comprising:

A) choose a first memory unit of a memory array, it includes first and second storage area under the control grid, can physically or electrically link together, to form a single control grid;

B) applying one first high voltage has chosen on the bit line to one of this first memory unit;

C) apply one second high voltage to this control grid of this first memory unit;

D) apply one first electric current decision voltage to one first and do not choose on first bit line of memory cell, first not choose memory cell adjacent with this first memory unit for this;

E) apply one second electric current decision voltage to second bit line of a second memory unit, this second memory unit is adjacent with this first memory unit;

F) use this first electric current, this first storage area of programming; And

G) use this second electric current, this second storage area of programming, and this first storage area of programming simultaneously.
2. method according to claim 1, wherein this memory array is configured to a metal bit architecture or a diffusion bit architecture.
3. method according to claim 1, wherein second high voltage is higher than first high voltage, differs a threshold value.
4. method according to claim 1 is wherein cut off this high voltage that this has chosen bit line, uses at this and has chosen a store charge on the bit line this first and second storage area of programming.
5. method according to claim 1, wherein this first electric current decision voltage first is not chosen this first bit line of memory cell and this and has been chosen and produce an electric current between bit line at this, and this first electric current decision voltage is one and is lower than the value that the word line that is connected to this first memory array is chosen voltage, and this first electric current flows through this first storage area under the injection electronics to this first storage area thus.
6. method according to claim 1, wherein this first electric current decision voltage first is not chosen this first bit line of memory cell and this and has been chosen and do not produce an electric current between bit line at this, and this first electric current decision voltage is one and is higher than the value that the word line that is connected to this first memory array is chosen voltage, and this first electric current does not flow through under this first storage area thus.
7. method according to claim 1, wherein this second electric current decision voltage has been chosen at this second bit line of this second memory unit and this and has been produced an electric current between bit line, and this second electric current decision voltage is one and is lower than the value that the word line that is connected to this first memory array is chosen voltage, and this second electric current flows through this first storage area under the injection electronics to this second storage area thus.
8. method according to claim 1, wherein this second electric current decision voltage has been chosen at this second bit line of this second memory unit and this and has not been produced an electric current between bit line, and this second electric current decision voltage is one and is higher than the value that the word line that is connected to this first memory array is chosen voltage, and this first electric current does not flow through under this first storage area thus.
9. method according to claim 1, wherein this first and second storage area is the nitride storage area, is positioned under first and second control grid of this first memory unit.
10. method according to claim 1, wherein this this first and second storage area of programming has simultaneously doubled the width of maximum programming data.
11. method according to claim 1 also includes a bit line selection transistor as source electrode output, is used for the bit-line voltage of control storage unit during programming and the bit line capacitance of reduction memory cell:

A) the memory cell bit line is coupled to time bit line;

B) utilize bit line selection transistor that inferior bit line is coupled to main bit line so that time bit line and main bit line are isolated;

C) applying one the 3rd high voltage puts in place on the transistorized grid of line options device to select time bit line; And

D) apply one the 4th high voltage to main bit line, to produce to the first required high voltage of first memory unit programming by the selection transistors couple that is connected with the inferior bit line of first memory unit.
12. method according to claim 11, wherein the main bit line voltage fluctuation is allowed in this source electrode output, and keeps bit-line voltage one stable time.
13. method according to claim 11, wherein the 3rd high voltage is a limit voltage higher than this first high voltage.
14. method according to claim 11, wherein the 4th high voltage is bigger than this first high voltage.
15. use bit line capacitance so that the method for enough high voltage store charges with the MONOS storage area of programming to be provided, comprising for one kind:

A) choose a MONOS memory cell, it includes a plurality of storage areas, and connects and one chosen word line, use a bit line selection transistor and connect and one chosen bit line, and connect one and chosen control line;

B) choose bit line for one first that does not choose memory cell, use one first electric capacity, be used in second electric capacity that this has chosen bit line, to provide electric charge with the MONOS storage area of programming from it;

C) first do not choose bit line and chosen bit line to this and use electric capacity by connecting this, to produce the electric capacity of an associating; And

D) apply one first voltage and first do not choose bit line and this has been chosen on the bit line, should unite the electric capacity charging to this.
16. method according to claim 15 wherein applies one second voltage to first not choosing adjacent second and third of bit line and do not choose bit line and suppress this with programming and do not choose memory cell with this.
17. method according to claim 15 wherein will connect this and first not choose bit line and this has chosen bit line together, produce enough associating electric capacity, so as with a predeterminated voltage electric charge to this storage area programming.
18. method according to claim 16, wherein this second voltage first is not chosen this bit line and this and has been chosen bit line and cut off, and the channel hot electron of the mobile generation of electric current of this electric charge on comfortable this associating electric capacity since this storage area and programming.
19. method according to claim 16, wherein this electric charge on this associating electric capacity is augmented this second voltage, to reduce the current requirements of a voltage source that produces this second voltage.
20. method according to claim 16 wherein applies this second voltage and first does not choose bit line and this has chosen bit line to this, produces enough electric charges on this associating electric capacity, with these a plurality of storage areas of programming.
21. method according to claim 16, wherein this second voltage is a high voltage that generation one electric current flows under this storage area, and this electric current flows is enough to inject electronics to this storage area.
22. method according to claim 16, wherein this second voltage equal one this chosen the voltage of choosing on the word line.
23. method according to claim 15, wherein this bit line is chosen transistor and is used for bit line is subdivided into and is inferior bit line, thereby reduces the bit line capacitance of having chosen the unit.
24. the device of a plurality of storage areas of the MONOS unit of programming simultaneously comprises:

A) a kind of being used for is connected to the control grid of two MONOS memory cells to high voltage to choose the device of described memory cell;

B) a kind of device that is used for a high voltage is connected to a bit line of described memory cell;

C) a kind ofly be used under one first storage area of this memory cell producing the device that one first electric current flows;

D) a kind ofly be used under one second storage area of this memory cell producing the device that one second electric current flows; And

E) a kind of being used for reaches electronics from the mobile device that is injected into this second storage area of this second electric current from mobile this first storage area that is injected into of this first electric current simultaneously.
25. device according to claim 24 also includes a kind of device that this first and second electric current flows that is used to limit, and when cutting off being connected of this high voltage and this bit line, is used for providing store charge on this bit line, with this first and second storage area of programming.
26. device according to claim 24, also include a kind of source electrode output device that a main bit line is connected with this bit line of this MONOS memory cell of being used for, wherein this high voltage fluctuation is allowed in this source electrode output, controls the bit-line voltage of MONOS memory simultaneously.
27. device according to claim 24 wherein is used to produce the device that this first electric current flows, and is controlled by putting on a voltage of not choosing bit line adjacent with this first storage area.
28. device according to claim 27, wherein this of voltage device generation is lower than the value that this has chosen a word line voltage of memory cell, to cause this first electric current to flow and this first storage area of programming.
29. device according to claim 28, wherein the programming of this first storage area is injected by channel hot electron and is carried out.
30. device according to claim 27, wherein this of voltage device generation is higher than the value that this has chosen a word line voltage of memory cell, can not cause this first electric current to flow and this first storage area of can not programming.
31. device according to claim 24 wherein produces this device that this second electric current flows, and puts on adjacent with this second storage area one by a voltage device and does not choose bit line and controlled.
32. device according to claim 31, wherein this of voltage device generation is lower than the value that this has chosen a word line voltage of memory cell, to cause this second electric current to flow and this second storage area of programming.
33. device according to claim 31, wherein the programming of this second storage area is injected by channel hot electron and is carried out.
34. device according to claim 31, wherein this of voltage device generation is higher than the value that this has chosen a word line voltage of memory cell, can not cause this second electric current to flow and this second storage area of can not programming.
35. device according to claim 24, wherein this first and second storage area is the nitride storage area.
36. device according to claim 24, wherein flowing from this first electric current simultaneously is injected into electronics this first storage area, and flows from this second electric current and electronics to be injected into this device of this second storage area, and program bandwidth will be doubled.
37. one kind provides electric charge to use device with the position electric capacity of the MONOS storage area of programming, comprising:

A) a kind ofly be used for that first high voltage is connected to one and contain the control grid of a MONOS memory cell of a plurality of memory blocks to choose the device of a described MONOS memory cell;

B) a kind ofly be used to connect second high voltage with device to first bit line charging of being coupled to a described MONOS memory cell;

C) a kind of being used for charges to second bit line that is associated with the 2nd MONOS memory cell of not choosing, and sharing charging with described first bit line, thereby produces the device of the electric current of the described memory block that is enough to programme.
38., also include the mobile device of electric current that a kind of shared charging that limits described first and second bit lines causes, with the amount of control programming electric current according to the described device of using of claim 37.
39. according to the described device of using of claim 37, wherein the device that second bit line that is associated with the 2nd MONOS memory cell of not choosing is charged produces an associating charging capacitor when being coupled to described first bit line, and it is mobile that this associating charging capacitor produces the electric current of storage area of the MONOS memory cell that is enough to programme.
40. according to the described device of using of claim 37, wherein the minimum bitline decoding unit with eight unit chooses described first bit line and described second bit line, comprises that the programming of described the 2nd MONOS memory cell suppresses
41. according to the described device of using of claim 40, wherein the programming of the 2nd MONOS memory cell suppress need with the voltage bias of the either side adjacent bit lines of described second bit line, described voltage bias is approximately equal to this voltage of choosing of having chosen word line.