CN1320467C

CN1320467C - Noise resisting clock signal circuit

Info

Publication number: CN1320467C
Application number: CNB031580785A
Authority: CN
Inventors: 刘召锦
Original assignee: Wistron Corp
Current assignee: Wistron Corp
Priority date: 2003-09-04
Filing date: 2003-09-04
Publication date: 2007-06-06
Anticipated expiration: 2023-09-04
Also published as: CN1591366A

Abstract

The present invention provides a noise resisting clock signal circuit for eliminating noise in an initial clock signal transmitted on a bus. The noise resisting clock signal circuit comprises a connecting conducting wire assembly and a voltage detecting circuit, wherein the connecting conducting wire assembly comprise a bus and a conducting wire which is arranged along the bus; an initial clock signal is input to the first end of the bus; the first end of the conducting wire is connected with reference voltage. The voltage detecting circuit is electrically connected with the bus in the connecting conducting wire assembly and the second end of the conducting wire for outputting a correct clock signal according to the electric potential difference between the voltage of the bus and the second end of the conducting wire; the correct clock signal is equivalent to the initial clock signal after the noise is eliminated.

Description

The antinoise clock signal circuit

Technical field

The present invention is relevant to a kind of bus circuit, refers in particular to a kind of antinoise clock signal circuit that a clock signal and this clock signal can not be subjected to noise that is used to transmit.

Background technology

In any electronic circuit, the pickup electrode that is transmitted on the lead is vulnerable to interference of noise.Generally speaking, if this signal is one to be transmitted in the data-signal of a data bus (data bus), make a mistake when disturbing noise on this data-signal still to be unlikely to this data-signal of interpretation, if but this signal is one to be transmitted in the clock signal of a clock bus (clock bus), be present in the undesired running that any little surging (glitch) on this clock signal also very likely causes this electronic circuit.

See also Fig. 1, Fig. 1 is a conventional original clock signal CLK _OrgAnd original clock signal CLK _OrgFormed noise clock signal clk after in the process that is transmitted, having born noise _NoOscillogram.Shown in 1 part among Fig. 1, in this electronic circuit, original clock signal CLK _OrgOriginally predetermined to betide time t ₁Rising edge (rising edge) trigger an electronic component, yet, original clock signal CLK _OrgIn the process that transmits via this clock bus, bear noise and formed noise clock signal clk shown in 2 parts among Fig. 1 _No, this electronic component is because of the noise clock signal clk _NoTriggering, not only can move in time t ₁The rising edge at place also can be in time t ₂And t ₃The rising edge at place begins action.

Summary of the invention

Therefore fundamental purpose of the present invention is to provide a kind of antinoise clock signal circuit that a clock signal and this clock signal can not be subjected to noise that is used to transmit.

According to the present invention, the present invention discloses a kind of antinoise clock signal circuit, be used for eliminating the noise of the original clock signal that is transmitted on the bus, it comprises: one connects the lead group, it comprises this bus and at least one lead that is provided with along this bus, this original clock signal is input to first end of this bus, and first end of each this lead is connected to a reference voltage; One voltage arithmetic mean device, the input end of this voltage arithmetic mean device is electrically connected to second end of each this lead, is used to calculate the arithmetic mean voltage of voltage on second end of all these leads; An and voltage detecting circuit, be electrically connected to second end of this bus in this connection lead group and the output terminal of this voltage arithmetic mean device, be used for revising clock signal according to the output of the potential difference (PD) on the output terminal of second end of this bus and this voltage arithmetic mean device one.

According to the present invention, the present invention discloses a kind of method that is used for eliminating the noise of the original clock signal that is transmitted on the bus, and this method comprises: the output terminal that this original clock signal is inputed to this bus; Along this bus at least one lead is set, wherein the input end of each this lead is connected to a reference voltage; Calculate the arithmetic mean voltage of voltage on the output terminal of all these leads; And the voltage on the output terminal of this bus is when being higher than this arithmetic mean voltage, and clock signal is revised in output one.

According to the present invention, the present invention discloses a kind of antinoise clock signal circuit, be used for eliminating the noise of the original clock signal that is transmitted on the bus, it comprises that one connects a lead group and a voltage detecting circuit, this connection lead group comprises this bus and a lead along this bus setting, this original clock signal is input to first end of this bus, and first end of this lead is connected to a reference voltage.This voltage detecting circuit is electrically connected to second end of this bus and this lead in this connection lead group, be used for revising clock signal according to the output of the potential difference (PD) between the voltage on second end of this bus and this lead one, this correction clock signal is equivalent to the original clock signal behind this noise of removal.

In one embodiment of this invention, this lead is parallel to this bus.

Because this connection lead group is except comprising this bus in the antinoise clock signal circuit of the present invention, comprise that also one is parallel to the lead of this bus, because the difference between the noise that the two ends of two leads parallel to each other are accumulated is equal to zero, can not be subjected to interference of noise so be equivalent to the original clock signal that is transmitted on this bus.

Description of drawings

Fig. 1 is a conventional original clock signal CLK _OrgAnd original clock signal CLK _OrgFormed noise clock signal clk after in the process that is transmitted, having born noise _NoOscillogram.

Fig. 2 is one group of synoptic diagram that includes the connection lead group of two parallel wires of the present invention.

Fig. 3 is the functional block diagram of an antinoise clock signal circuit in one embodiment of the invention.

Fig. 4 is the oscillogram of each signal in the shown antinoise clock signal circuit of Fig. 3.

Fig. 5 is the functional block diagram of an antinoise clock signal circuit in the another embodiment of the present invention.

The reference numeral explanation

10,50 antinoise clock signal circuits, 12 primary controllers

14 from control device 16,56 connection lead groups

18 voltage detecting circuits, 20 buses

22,54 leads, 24 reference circuits

52 voltage arithmetic mean devices, 58 totalizers

60 dividers

Embodiment

See also Fig. 2, Fig. 2 is one group of synoptic diagram that includes the connection lead group 80 of two parallel wires 82,84 in one embodiment of the invention.As shown in Figure 2, since the interference of noise NOISE, first end of lead 82,84 (or title is input end) L ₁₁, L ₂₁On original signal V _1org, V _2orgAt second end that is transferred into lead 82,84 (or title is output terminal) L ₁₂, L ₂₂After can be transformed into original signal V respectively _1org+ noise NOISE ₁, V _2org+ noise NOISE ₂Yet included lead 82,84 is parallel to each other in the lead group 80 because connect, so original signal V _1org, V _2orgThe noise NOISE that in the process that is transmitted by lead 82,84 respectively, is accumulated to respectively ₁, NOISE ₂Almost equal, in detail, the first end L of lead 82 ₁₁On original signal V _1orgThe first end L with lead 84 ₂₁On original signal V _2orgBetween the difference second end L of lead 82 no better than ₁₂On original signal V _1org+ noise NOISE ₁The second end L with lead 84 ₂₂On original signal V _2org+ noise NOISE ₂Between poor.The present invention promptly utilize between signal on first end that is present in two parallel wires difference no better than the character of the difference between the signal on second end to eliminate the noise in the clock signal that is transmitted on the bus.

See also Fig. 3, Fig. 3 is the functional block diagram of an antinoise clock signal circuit 10 in one embodiment of the invention, the original clock signal CLK that antinoise clock signal circuit 10 can be sent a primary controller 12 _OrgBe sent to one from control device (bus slave) 14 via a bus 20.Be sent to from the process of control device 14 original clock signal CLK via bus 20 by primary controller 12 _OrgUnavoidable ground can be subjected to the interference of noise NOISE (in the second end BUS of bus 20 ₂Last formation one noise clock signal clk _No), and antinoise clock signal circuit 10 of the present invention can be eliminated the noise clock signal clk effectively _NoIn noise NOISE, and and then make from control device 14 received clock signals to be one not have the correction clock signal clk of any noise NOISE _Amd

Antinoise clock signal circuit 10 comprises that a connection lead group 16, a voltage detecting circuit 18 and are used to produce a reference voltage V _RefReference circuit 24.Connect lead group 16 and comprise bus 20 and a lead 22 that is provided with along bus 20, the original clock signal CLK that primary controller 12 is sent _OrgBe input to the first end BUS of bus 20 ₁, the first end LINE of lead 22 ₁Be connected to reference circuit 24, reference voltage V _RefBe input to the first end LINE of lead 22 ₁The second end BUS of bus 20 and lead 22 in the connection lead group 16 ₂, LINE ₂All be electrically connected to voltage detecting circuit 18.Voltage detecting circuit 18 is arranged at the second end BUS of bus 20 (and lead 22) ₂The place, voltage detecting circuit 18 is according to the second end BUS of bus 20 and lead 22 ₂, LINE ₂On the noise clock signal clk _NoAnd noise reference voltage V _RefnoBetween potential difference (PD) output revise clock signal clk _Amd

In one embodiment of this invention, bus 20 is a SMBUS (smart bus: intelligent bus), primary controller 12 can be a south bridge circuit or a keyboard controller (keyboard controller, KBC), can be a memory module, a clock generator or a peripherals from control device 14, lead 22 is parallel to bus 20, and voltage detecting circuit 18 is one to be used in the noise clock signal clk _NoGreater than noise reference signal V _RefnoClock signal clk is revised in time output _AmdComparer, and reference circuit 24 comprises one first resistance R ₁Reach one and be concatenated into first resistance R ₁Second resistance R ₂, first resistance R wherein ₁First end be connected to one first voltage V _Cc, second resistance R ₂First end be connected to one second voltage GND, and the first end LINE of lead 22 ₁Be connected to first resistance R ₁Second end and second resistance R ₂Second end.

In the present invention, though the first end BUS of bus 20 ₁On original clock signal CLK _OrgBe transferred into the second end BUS of bus 20 via bus 20 ₂Process in, maybe can be subjected to the interference of noise NOISE and be out of shape (for example being deformed into the noise clock signal clk shown in Fig. 1 _No), but because of the first end LINE of lead 22 ₁On reference signal V _RefBe transferred into the second end LINE of lead 22 via lead 22 ₂Process in, the noise NOISE that is born almost is equal to original clock signal CLK _OrgThe noise NOISE that is born (precedingly addressed, the difference between the signal on first end of two parallel wires is poor between the signal on second end no better than), so, the second end BUS of bus 20 ₂On noise clock CLK _NoThe second end LINE with lead 22 ₂On noise reference voltage V _RefnoBetween variation close the first end BUS be tantamount to bus 20 ₁On original clock signal CLK _OrgThe first end LINE with lead 22 ₁On reference voltage V _RefBetween variation relation.Be equivalent to, be arranged at the second end BUS of bus 20 (and lead 22) ₂The place is used for according to the noise clock signal clk _NoAnd noise reference signal V _RefnoRevise clock signal clk to produce _AmdVoltage detecting circuit 18 be arranged at the first end BUS of bus 20 (and lead 22) seemingly ₁The place is used for according to original clock signal CLK _OrgAnd reference signal V _RefWith same generation correction clock signal clk _AmdVoltage detecting circuit, original clock signal CLK _OrgIn the process that transmits via bus 20, be not subjected to the interference of any noise NOISE seemingly.

See also Fig. 4, Fig. 4 is original clock signal clk among the present invention _Org, reference voltage V _Ref, the noise clock signal clk _No, noise reference voltage V _RefnoAnd correction clock signal clk _AmdOscillogram.Shown in 3 and 4 parts among Fig. 4, primary controller 12 and reference circuit 24 are respectively at the first end BUS of bus 20 ₁And the first end LINE of lead 22 ₁Output is not with the original clock signal CLK of any noise NOISE respectively _OrgAnd reference voltage V _RefAfter through the transmission that connects lead group 16, the second end BUS of bus 20 ₂And the second end LINE of lead 22 ₂On the noise clock signal clk _NoAnd noise reference voltage V _RefnoMeeting has noise NOISE respectively as the waveform as shown in 5 and 6 parts among Fig. 4, and the noise clock signal clk _NoAnd noise reference voltage V _RefnoTime of origin and the size of middle noise NOISE but can be identical.Therefore, 18 of the voltage detecting circuits of device are concerned about the noise clock signal clk as a comparison _NoAnd noise reference voltage V _RefnoBetween relativeness (the noise clock signal clk of a certain time point _NoThe noise reference voltage V that whether is higher than this time point _Refno), and do not remove to comprehend the noise clock signal clk _NoAnd noise reference voltage V _RefnoAbsolute figure actually why.

In antinoise clock signal circuit 10 of the present invention, be used to produce reference voltage V _RefReference circuit 24 also can change and constituted by operational amplifier, and voltage detecting circuit 18 also can be made of operational amplifier or subtracter except comparer, because these are routine techniques, so repeat no more in this.

In one embodiment of this invention, though the connection lead group 16 of antinoise clock signal circuit 10 comprises the only SMBUS of single bus of tool, yet connect lead group 16 and also can comprise other pattern bus with multiple bus, but the connection lead group 16 of this moment must comprise one or one or more lead corresponding to the multiple bus lead of this other pattern bus, and also must comprise one or more comparer accordingly in the voltage detecting circuit 18.

Connection lead group 16 shown in Fig. 3 only comprises a lead 22 that is positioned at bus 20 1 sides, and the noise from bus 20 sides and lead 22 sides that hypothesis connection lead group 16 is born is all identical.Yet, in some cases, come from the noise that connects lead group 16 both sides and understand some difference, cause the second end BUS of bus 20 ₂Go up the second end LINE that reaches lead 22 ₂On the noise accumulated not the same, for this kind problem, the inventor can utilize another embodiment as shown in Figure 5 to solve.See also Fig. 5, Fig. 5 is the functional block diagram of an antinoise clock signal circuit 50 in the another embodiment of the present invention.Compare with antinoise clock signal circuit 10 shown among Fig. 3, antinoise clock signal circuit 50 also comprises a voltage arithmetic mean device 52, and connection lead group 56 included in the antinoise clock signal circuit 50 is except comprising bus 20 and lead 22, also comprise a lead 54 that also is provided with along bus 20, lead 22,54 is divided into the both sides of bus 20.Voltage arithmetic mean device 52 comprises a totalizer 58 and a divider 60, and totalizer 58 is used to add up the noise reference voltage V on second end of lead 22,54 _No1, V _No2, and divider 60 is used for noise reference voltage V that totalizer 58 is exported _No1, V _No2The result of addition is divided by 2.In other words, voltage arithmetic mean device 52 is used for calculating noise reference voltage V _No1, V _No2Arithmetic mean voltage.Then, voltage detecting circuit 18 is just according to this arithmetic mean voltage and noise clock signal clk _NoProduce and revise clock signal clk _Amd

Certainly, though only list two leads 22 among the embodiment of Fig. 5, yet the present invention can also be provided with the many leads that are electrically connected with reference voltage along this bus, and calculate the arithmetic mean voltage of all wire output ends by voltage arithmetic mean device, then according to this arithmetic mean voltage and noise clock signal clk _NoProduce the correction clock signal clk _Amd

Compare with routine techniques, no matter utilization the present invention is original clock signal CLK _OrgThe path that is transmitted has and how far reaches the noise that is afforded and have muchly, and this voltage detecting circuit all can dynamically be equivalent to according to original clock signal CLK _OrgAnd reference voltage V _RefBetween relation produce the correction clock signal clk do not contain any surging _AmdTherefore the present invention is equivalent to and can eliminates original clock signal CLK _OrgAccumulation noise thereon in the process that transmits.

The above only is the preferred embodiments of the present invention, and all equivalences of making according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.

Claims

1. antinoise clock signal circuit is used for eliminating the noise of the original clock signal that is transmitted on the bus, and it comprises:

One connects the lead group, and it comprises this bus and at least one lead that is provided with along this bus, and this original clock signal is input to first end of this bus, and first end of each this lead is connected to a reference voltage;

One voltage arithmetic mean device, the input end of this voltage arithmetic mean device is electrically connected to second end of each this lead, is used to calculate the arithmetic mean voltage of voltage on second end of all these leads; And

One voltage detecting circuit is electrically connected to second end of this bus in this connection lead group and the output terminal of this voltage arithmetic mean device, is used for revising clock signal according to the output of the potential difference (PD) on the output terminal of second end of this bus and this voltage arithmetic mean device one.

2. antinoise clock signal circuit as claimed in claim 1, wherein each this lead is parallel to this bus.

3. antinoise clock signal circuit as claimed in claim 1, wherein can be arranged at the both sides of this bus along the lead of this bus setting, and the lead number that is arranged at this bus one side is compared with the lead number that is arranged at this bus opposite side, is equal or many one.

4. method that is used for eliminating the noise of the original clock signal that is transmitted on the bus, this method comprises:

This original clock signal is input to first end of this bus;

Along this bus one lead is set, first end of this lead is connected to a reference voltage; And

When the voltage on second end of this bus was higher than voltage on second end of this lead, clock signal was revised in output one.

5. method as claimed in claim 4, wherein this lead is parallel to this bus.

6. method as claimed in claim 4, wherein this bus is an intelligent bus.

7. method as claimed in claim 4, wherein this original clock signal produces from a primary controller, and this correction clock signal exports one to from the control device.

8. method that is used for eliminating the noise of the original clock signal that is transmitted on the bus, this method comprises:

This original clock signal is inputed to the output terminal of this bus;

Along this bus at least one lead is set, wherein the input end of each this lead is connected to a reference voltage;

Calculate the arithmetic mean voltage of voltage on the output terminal of all these leads; And

When the voltage on the output terminal of this bus was higher than this arithmetic mean voltage, clock signal was revised in output one.

9. method as claimed in claim 8, wherein each this lead is parallel to this bus.

10. method as claimed in claim 8 wherein can be arranged at the both sides of this bus along the lead of this bus setting, and the lead number that is arranged at this bus one side compares with the lead number that is arranged at this bus opposite side, is to equate or many one.