CN1322577C - Method for avoiding up electrode layer to generae stress-leaded seam in 1T-SRAM working - Google Patents
Method for avoiding up electrode layer to generae stress-leaded seam in 1T-SRAM working Download PDFInfo
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- CN1322577C CN1322577C CNB031548563A CN03154856A CN1322577C CN 1322577 C CN1322577 C CN 1322577C CN B031548563 A CNB031548563 A CN B031548563A CN 03154856 A CN03154856 A CN 03154856A CN 1322577 C CN1322577 C CN 1322577C
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Abstract
The present invention discloses a method for avoiding void generation caused by stress induction on a top electrode layer during processing a capacitor of a single transistor static read only access memory (1T SRAM). The method mainly adds an inner dielectric layer between the top electrode layer and an anti-reflecting layer of the capacitor for balancing stress; in addition, the method improves isolation effects between gate electrodes and between the gate electrodes and the top electrode layer at the same time so as to reduce the formation of voids.
Description
Technical field
The invention relates to a kind of in the processing of the static read-only access memory of one-transistor (1T SRAM), avoid the method that produces because of the stress induced slit (void) of upper electrode layer, particularly about between the upper electrode layer of electric capacity and its anti-reflecting layer, adding the method that an inner-dielectric-ayer avoids this slit to produce.
Background technology
The basic module configuration of traditional static RAM (SRAM) is made up of six transistors, and normally the metal oxide semiconductor field effect of four N passages (N-channel) answers transistor (MOSFET) to add the MOSFET of two P passages.In order to cut down finished cost, the semiconductor product industry tries to make littler chip, and the density with original chip is identical at least, even bigger.As long as can on a certain size base material, cut out more chip, just the cost of each one chip can reduce.Yet, in the SRAM manufacturing technology, six transistors are positioned on the less semiconductor chip, be some difficult thing.Therefore, the manufacturing technology of SRAM just is absorbed at a transistor, and promptly on the structure cell of 1T SRAM (one-transistor static read-only access memory), it comprises that a metal oxide semiconductor field effect answers a transistor (MOSFET) and a capacitance structure.The one-transistor like this and the feature of capacitance structure but provide and six effects that transistorized SRAM is identical, the road of the littler semiconductor chip of design of also marching toward gradually.
Because process integration is improving always, semiconductor is already made the trend of integrated circuit at present, be and on an one chip, integrate memory array and high speed logic circuit, form an embedded access memory (for example embedded dynamic random access memory, embedded 1T SRAM).Embedded memory array and the logical circuit of having comprised simultaneously can reduce circuit area widely and increase processing speed.For 1T SRAM processing, electric capacity processing must be finished before logic processing beginning, and therebetween in order to dwindle born of the same parents' size, gate will inevitably cover whole capacitor.So less than the processing of 0.13 μ m (micrometre) be have challenging.Because electric capacity processing just need be finished before logic processing beginning, so electric capacity will have a series of high temperature process, for example ion of the growth of gate pole oxidation layer, source/drain implantation.Because these continuous high temperature process, the unequal power distribution between upper electrode layer and the anti-reflecting layer can cause forming slit (void) between upper electrode layer and anti-reflecting layer.Also owing to the generation in these slits, gate can contact with upper electrode layer by the slit when growing up, and causes the short circuit between gate and the upper electrode layer.
Summary of the invention
Because in above-mentioned background technology, the imbalance of the upper electrode layer of electric capacity and its anti-reflecting layer intermediate stress can produce the slit; Simultaneously, this slit also can cause the short circuit between gate and the upper electrode layer.
Therefore, the object of the present invention is to provide the manufacture method of the static read-only access memory capacitor of a kind of one-transistor, can avoid unbalanced stress between upper electrode layer and the anti-reflecting layer.
Another object of the present invention is to provide the manufacture method of the static read-only access memory capacitor of a kind of one-transistor, can avoid in follow-up high temperature process, producing the slit.
A further object of the present invention is to provide the manufacture method of the static read-only access memory capacitor of a kind of one-transistor, can avoid gate to contact with upper electrode layer by the slit when growing up and cause short circuit between gate and the upper electrode layer.
According to the above object, implementation method step of the present invention is as follows: form shallow slot isolation structure on semiconductor substrate, form a pad oxide and one first cover curtain layer thereon in regular turn.On active region and shallow slot isolation structure, form a patterning photoresist layer, expose predetermined electric capacity and make the zone.Etching downwards removes the part shallow slot isolation structure to mold several openings, then, removes photoresist layer, conformally deposits one first conductor layer.Remove first conductor layer on first cover curtain layer in regular turn, remove first cover curtain layer on the pad oxide, the conductor layer of winning can be covered within this shallow slot isolation structure.
Then on this active region and shallow slot isolation structure, form one first dielectric layer, one second conductor layer, one second dielectric layer and an anti-reflecting layer in regular turn.Non-then grade is to etching part anti-reflecting layer, second dielectric layer, second conductor layer and first dielectric layer, and molds a capacitance structure with pad oxide for stopping layer.Then on this pad oxide, form a clearance wall, on active region, form a gate pole oxidation layer then, form gate structure at last and be across on this capacitance structure, this active region and the shallow slot isolation structure.
The invention has the advantages that, by in electric capacity, adding one second dielectric layer, balance the stress between second conductor layer and the anti-reflecting layer, thereby avoided the generation in slit in follow-up high temperature process.In addition, because the balance of stress has been avoided the generation in slit in the follow-up high temperature process, cause short circuit between gate and the upper electrode layer thereby effectively avoid gate when growing up, to contact with upper electrode layer by the slit.
Brief Description Of Drawings
For cooperating the elaboration of preferred embodiment of the present invention, in the literary composition conjunction with figs. is elaborated, wherein: Fig. 1 to Fig. 6 is the generalized section during according to each step of processing of preferred embodiment of the present invention.
Embodiment
For the present invention and above-mentioned purpose, feature and advantage more can be become apparent, only with a better embodiment and after the results are shown in, and the conjunction with figs. label is described in detail:
Please refer to Fig. 1, on semiconductor base material 100, form a shallow slot isolation structure 102 (STI), and form an active region 104 (Active Area).Then, this active region 104 is carried out implanting ions, to form the doped well zone (not shown).
Please refer to Fig. 2, on base material, deposit the pad oxide 18 (Pad Oxide) and first cover curtain layer 20 in regular turn.Wherein, the material of this first cover curtain layer 20 can be a silicon nitride, and it utilizes electricity slurry reinforced-chemical vapour deposition (CVD) (PE-CVD) method or low pressure-chemical vapour deposition (CVD) (LP-CVD) method to form.Then be coated with a photoresist layer (not shown) and cover active region and shallow slot isolation structure top, patterning photoresist layer (not shown) exposes part shallow slot isolation structure 102 and active region 104, with first cover curtain layer 20 on the active region is the cover curtain, form several openings with an etching and processing in shallow slot isolation structure 102, these openings are the structures as capacitor openings.
Please refer to Fig. 3, remove the photoresist layer (not shown).Then on those openings and first cover curtain layer 20, conformally deposit one first conductor layer 22.The material of this first conductor layer can be polysilicon (Poly-silicon) or other conductive metal layer.
Please refer to Fig. 4, utilize cmp or the method for eat-backing to remove first conductive layer 22 partly, and first cover curtain layer 20 is as stopping layer (a stop layer).Then utilize hot phosphoric acid (hot H
3PO
4) remove first cover curtain layer 20.
Please refer to Fig. 5, conformally deposit first dielectric layer 24, second conductor layer 26, second dielectric layer 28 and anti-reflecting layer 30 in regular turn.Wherein, the material of first dielectric layer 24 is double-deckers of a silicon nitride and silica.The material of second conductor layer 26 can be polysilicon or other conductive metal layer.Second dielectric layer 28 can be oxide or nitride.The material of anti-reflecting layer 30 can be the silicon oxynitride (SiON) of tool extension power, and it is to utilize the mode of low pressure-chemical vapour deposition (CVD) (LP-CVD) to form.
Please refer to Fig. 6, non-grade is to etching part first dielectric layer 24, second conductor layer 26, second dielectric layer 28 and anti-reflecting layer 30, and with pad oxide 18 for stopping layer so that on STI, mold a capacitance structure 44.Then deposited silicon nitride layer conformally on this electric capacity, silicon oxide layer deposited on this silicon nitride layer more afterwards.Etching removes this silicon nitride layer then, forms silica clearance wall 40 next-door neighbour's silicon nitride layers.Etching removes silicon nitride layer then, and on pad oxide 18, the both sides of electric capacity form silicon nitride gap wall 42, it is the L type substantially.Therefore formed the compound clearance wall of a kind of silicon nitride and silica.Then on active region 104, form gate pole oxidation layer 46, form gate online 56 at last and get final product.
Be noted that wherein in the preferred embodiment of the present invention that first conductor layer 22 is the lower electrode layer of capacitance structure 44, and this lower electrode layer is arranged in sti structure.And second conductor layer 26 is the upper electrode layer of capacitance structure 44.
Be noted that preferred embodiment of the present invention especially, it is characterized in that it adds second dielectric layer 28 in electric capacity, but balance second conductor layer 26, stress between the upper electrode layer just, and anti-reflecting layer 30 is to avoid the generation of slit in the follow-up high temperature process (void).In addition, because the balance of stress has been avoided the generation in slit in the follow-up high temperature process, cause short circuit between gate and the upper electrode layer thereby effectively avoided gate when growing up, to contact with upper electrode layer by the slit.
Just as one of ordinary skill in understanding, the present invention discloses as above by preferred embodiment, but above-mentioned preferred embodiment and non-limiting protection scope of the present invention; Allly do not break away from design modifications or improvements of the present invention, all should be included within the protection range that claim of the present invention limits.
Claims (18)
1, a kind of method of avoiding electric capacity interior slit generation in the static read-only access memory processing of one-transistor, it comprises following steps at least:
In a substrate, form a shallow slot isolation structure;
Carry out a forming step, so that in this shallow slot isolation structure, form several openings;
Conformally deposit one first conductor layer;
Remove part first conductor layer;
Deposit one first conformal dielectric layer;
On this first dielectric layer, form one second conformal conductor layer;
On this second conductor layer, form one second dielectric layer;
On this second dielectric layer, form an anti-reflecting layer; And
Carry out a final step, to form complete capacitance structure.
2, the method for claim 1 is characterized in that, this forming step comprises the following steps: at least
On this substrate, form a pad oxide;
Deposition forms one first cover curtain layer on this pad oxide; And
Carry out a lithography step.
3, method as claimed in claim 2 is characterized in that: this first cover curtain layer is a silicon nitride layer that forms by electricity slurry enhancement mode-chemical vapour deposition (CVD) or low pressure-chemical vapour deposition (CVD).
4, the method for claim 1 is characterized in that: this first conductor layer material comprises a polysilicon.
5, the method for claim 1 is characterized in that: this first conductor layer utilizes chemical mechanical milling method or the method for eat-backing to remove.
6, the method for claim 1 is characterized in that: this first dielectric layer material comprises the double-decker of a silicon nitride and silica.
7, the method for claim 1 is characterized in that: this second conductor layer material comprises a polysilicon.
8, the method for claim 1 is characterized in that: this second dielectric layer comprises oxide or nitride.
9, the method for claim 1 is characterized in that: this final step comprises the following step at least:
Carry out a forming step so that remove part anti-reflecting layer, this second dielectric layer, this second conductor layer and first dielectric layer, so that on this shallow slot isolation structure, form an electric capacity; And
On the two side of this electric capacity and this pad oxide, form a clearance wall.
10, method as claimed in claim 9 is characterized in that: this anti-reflecting layer is a silicon oxynitride that forms by low pressure-chemical vapour deposition (CVD).
11, method as claimed in claim 9 is characterized in that: this clearance wall is combined by silicon nitride and silica.
12, a kind of capacitance structure, this structure comprises at least:
One bottom electrode;
One is positioned at first dielectric layer on this bottom electrode;
One is positioned at the top electrode on this first dielectric layer;
One is positioned at second dielectric layer on this top electrode; And
One is positioned at the anti-reflecting layer on this second dielectric layer,
Wherein, this second dielectric layer difference of being used for relaxing stress between this top electrode and this anti-reflecting layer is to avoid producing hole when the follow-up hot working between this top electrode and this anti-reflecting layer.
13, capacitance structure as claimed in claim 12 is characterized in that: this bottom electrode material is arranged in a shallow slot isolation structure.
14, capacitance structure as claimed in claim 12 is characterized in that: this bottom electrode material comprises a polysilicon.
15, capacitance structure as claimed in claim 12 is characterized in that: this first dielectric layer material comprises the double-decker of a silicon nitride and silica.
16, capacitance structure as claimed in claim 12 is characterized in that: this top electrode material comprises a polysilicon.
17, capacitance structure as claimed in claim 12 is characterized in that: this second dielectric layer material comprises oxide or nitride.
18, capacitance structure as claimed in claim 12 is characterized in that: this anti-reflecting layer material comprises a silicon oxynitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031548563A CN1322577C (en) | 2003-08-15 | 2003-08-15 | Method for avoiding up electrode layer to generae stress-leaded seam in 1T-SRAM working |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031548563A CN1322577C (en) | 2003-08-15 | 2003-08-15 | Method for avoiding up electrode layer to generae stress-leaded seam in 1T-SRAM working |
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| Publication Number | Publication Date |
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| CN1581469A CN1581469A (en) | 2005-02-16 |
| CN1322577C true CN1322577C (en) | 2007-06-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031548563A Expired - Lifetime CN1322577C (en) | 2003-08-15 | 2003-08-15 | Method for avoiding up electrode layer to generae stress-leaded seam in 1T-SRAM working |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8742540B2 (en) | 2005-08-31 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Insulation layer to improve capacitor breakdown voltage |
| US9620582B2 (en) * | 2015-01-27 | 2017-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal-insulator-metal (MIM) capacitors and forming methods |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583077A (en) * | 1995-04-04 | 1996-12-10 | Taiwan Semiconductor Manufacturing Company Ltd | Integrated dual layer passivation process to suppress stress-induced metal voids |
| US6136688A (en) * | 1999-10-20 | 2000-10-24 | Vanguard International Semiconductor Corporation | High stress oxide to eliminate BPSG/SiN cracking |
| US6174820B1 (en) * | 1999-02-16 | 2001-01-16 | Sandia Corporation | Use of silicon oxynitride as a sacrificial material for microelectromechanical devices |
| US6221794B1 (en) * | 1998-12-08 | 2001-04-24 | Advanced Micro Devices, Inc. | Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines |
| US6287962B1 (en) * | 2000-11-30 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Method for making a novel graded silicon nitride/silicon oxide (SNO) hard mask for improved deep sub-micrometer semiconductor processing |
| US6414376B1 (en) * | 1997-07-31 | 2002-07-02 | Micron Technology, Inc. | Method and apparatus for reducing isolation stress in integrated circuits |
| TW506081B (en) * | 2001-09-21 | 2002-10-11 | Taiwan Semiconductor Mfg | Manufacturing method for embedded memory |
| US6468855B2 (en) * | 1998-08-14 | 2002-10-22 | Monolithic System Technology, Inc. | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same |
-
2003
- 2003-08-15 CN CNB031548563A patent/CN1322577C/en not_active Expired - Lifetime
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583077A (en) * | 1995-04-04 | 1996-12-10 | Taiwan Semiconductor Manufacturing Company Ltd | Integrated dual layer passivation process to suppress stress-induced metal voids |
| US6414376B1 (en) * | 1997-07-31 | 2002-07-02 | Micron Technology, Inc. | Method and apparatus for reducing isolation stress in integrated circuits |
| US6468855B2 (en) * | 1998-08-14 | 2002-10-22 | Monolithic System Technology, Inc. | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same |
| US6221794B1 (en) * | 1998-12-08 | 2001-04-24 | Advanced Micro Devices, Inc. | Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines |
| US6174820B1 (en) * | 1999-02-16 | 2001-01-16 | Sandia Corporation | Use of silicon oxynitride as a sacrificial material for microelectromechanical devices |
| US6136688A (en) * | 1999-10-20 | 2000-10-24 | Vanguard International Semiconductor Corporation | High stress oxide to eliminate BPSG/SiN cracking |
| US6287962B1 (en) * | 2000-11-30 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Method for making a novel graded silicon nitride/silicon oxide (SNO) hard mask for improved deep sub-micrometer semiconductor processing |
| TW506081B (en) * | 2001-09-21 | 2002-10-11 | Taiwan Semiconductor Mfg | Manufacturing method for embedded memory |
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