CN1329989C - 半导体集成电路器件 - Google Patents
半导体集成电路器件 Download PDFInfo
- Publication number
- CN1329989C CN1329989C CNB988126710A CN98812671A CN1329989C CN 1329989 C CN1329989 C CN 1329989C CN B988126710 A CNB988126710 A CN B988126710A CN 98812671 A CN98812671 A CN 98812671A CN 1329989 C CN1329989 C CN 1329989C
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- Prior art keywords
- mosfet
- threshold voltage
- gate
- path
- channel mosfet
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000000034 method Methods 0.000 title claims description 74
- 239000000758 substrate Substances 0.000 claims description 47
- 230000008569 process Effects 0.000 claims description 28
- 230000000644 propagated effect Effects 0.000 abstract 2
- 230000004907 flux Effects 0.000 description 22
- 230000008859 change Effects 0.000 description 18
- 230000003647 oxidation Effects 0.000 description 18
- 238000007254 oxidation reaction Methods 0.000 description 18
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 17
- 230000000295 complement effect Effects 0.000 description 16
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 15
- 238000003860 storage Methods 0.000 description 15
- 230000006870 function Effects 0.000 description 13
- 239000012535 impurity Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 12
- 238000009826 distribution Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000004364 calculation method Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 101100243558 Caenorhabditis elegans pfd-3 gene Proteins 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 238000012938 design process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
Abstract
Description
Claims (2)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35927797A JP3777768B2 (ja) | 1997-12-26 | 1997-12-26 | 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法 |
JP359277/1997 | 1997-12-26 | ||
JP359277/97 | 1997-12-26 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101121200A Division CN101060325B (zh) | 1997-12-26 | 1998-12-16 | 半导体集成电路器件和半导体集成电路的设计方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1294783A CN1294783A (zh) | 2001-05-09 |
CN1329989C true CN1329989C (zh) | 2007-08-01 |
Family
ID=18463680
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101121200A Expired - Lifetime CN101060325B (zh) | 1997-12-26 | 1998-12-16 | 半导体集成电路器件和半导体集成电路的设计方法 |
CNB988126710A Expired - Lifetime CN1329989C (zh) | 1997-12-26 | 1998-12-16 | 半导体集成电路器件 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101121200A Expired - Lifetime CN101060325B (zh) | 1997-12-26 | 1998-12-16 | 半导体集成电路器件和半导体集成电路的设计方法 |
Country Status (9)
Country | Link |
---|---|
US (3) | US6380764B1 (zh) |
EP (1) | EP1058386A4 (zh) |
JP (1) | JP3777768B2 (zh) |
KR (2) | KR20040023618A (zh) |
CN (2) | CN101060325B (zh) |
HK (1) | HK1109248A1 (zh) |
MY (1) | MY133109A (zh) |
TW (5) | TW536808B (zh) |
WO (1) | WO1999034512A1 (zh) |
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JP3853576B2 (ja) * | 2000-06-29 | 2006-12-06 | 株式会社東芝 | 回路自動生成装置、回路自動生成方法及び回路自動生成プログラムを記載した記録媒体 |
SE518797C2 (sv) * | 2000-07-19 | 2002-11-19 | Ericsson Telefon Ab L M | Effekt-LDMOS-transistor innefattande ett flertal parallellkopplade transistorsegment med olika tröskelspänningar |
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1997
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1998
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- 1998-12-10 MY MYPI98005591A patent/MY133109A/en unknown
- 1998-12-10 TW TW087120480A patent/TW437054B/zh not_active IP Right Cessation
- 1998-12-10 TW TW091124090A patent/TW536809B/zh not_active IP Right Cessation
- 1998-12-10 TW TW089114774A patent/TW457695B/zh not_active IP Right Cessation
- 1998-12-10 TW TW090114045A patent/TW529156B/zh not_active IP Right Cessation
- 1998-12-16 CN CN2007101121200A patent/CN101060325B/zh not_active Expired - Lifetime
- 1998-12-16 WO PCT/JP1998/005688 patent/WO1999034512A1/ja active IP Right Grant
- 1998-12-16 KR KR10-2003-7016302A patent/KR20040023618A/ko not_active Application Discontinuation
- 1998-12-16 EP EP98961366A patent/EP1058386A4/en not_active Withdrawn
- 1998-12-16 CN CNB988126710A patent/CN1329989C/zh not_active Expired - Lifetime
- 1998-12-16 KR KR1020007007129A patent/KR100592864B1/ko not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
US6380764B1 (en) | 2002-04-30 |
KR100592864B1 (ko) | 2006-06-23 |
TW536808B (en) | 2003-06-11 |
CN101060325A (zh) | 2007-10-24 |
JP3777768B2 (ja) | 2006-05-24 |
TW457695B (en) | 2001-10-01 |
TW536809B (en) | 2003-06-11 |
WO1999034512A1 (en) | 1999-07-08 |
CN101060325B (zh) | 2010-08-18 |
US6769110B2 (en) | 2004-07-27 |
MY133109A (en) | 2007-10-31 |
KR20040023618A (ko) | 2004-03-18 |
US7129741B2 (en) | 2006-10-31 |
TW437054B (en) | 2001-05-28 |
TW529156B (en) | 2003-04-21 |
HK1109248A1 (en) | 2008-05-30 |
EP1058386A4 (en) | 2006-05-31 |
KR20010033616A (ko) | 2001-04-25 |
EP1058386A1 (en) | 2000-12-06 |
CN1294783A (zh) | 2001-05-09 |
JPH11195976A (ja) | 1999-07-21 |
US20020079927A1 (en) | 2002-06-27 |
US20040196684A1 (en) | 2004-10-07 |
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