CN1358059A - Structure of reducing mutual inductance between adjacent wires on substrate - Google Patents
Structure of reducing mutual inductance between adjacent wires on substrate Download PDFInfo
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- CN1358059A CN1358059A CN 01115309 CN01115309A CN1358059A CN 1358059 A CN1358059 A CN 1358059A CN 01115309 CN01115309 CN 01115309 CN 01115309 A CN01115309 A CN 01115309A CN 1358059 A CN1358059 A CN 1358059A
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- mutual inductance
- transmission line
- adjacent wires
- substrate
- hollow
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The present invention is a structure to lower the mutual inductance between the adjacent conducting wires on the base plate, it lays a hollow transmitting wire in between the complex numbers of transmitting wires disposed in parallel. Two top points of the hollow transmitting wire are coupled with bondwire and the via of printed circuit board or ball grid array board separately to be used as signal input and output points at the same time the complex numbers of top points of the hollow transmitting wire coupled with the printed circuit board or ball grid array board are bevelled jointed, and setting the length of complex short-edges as half of transmitting signal wave length so that the signal phase on two long-edges are completely reversed in phase to nearly eliminate all the mutual inductance and to effectively lower the cross-linking effects.
Description
The present invention relates to the structure between a kind of printed circuit board (PCB) or ball grid array board, and be particularly related to a kind of structure that can effectively reduce mutual inductance between adjacent wires on substrate.
After IBM Corporation developed PC/XT and later PC/AT personal computer, many manufacturers also and then made the personal computer with IBM PC compatibility, make the whole world generally use this type of computer.
Begin development up to now from IBM PC, though hardware and software engineering have greatly improved during this, the motherboard of the personal computer that these are commonly used disposes the form of still following originally, and industry generally is referred to as the AT motherboard.Because the progress of hardware is dwindled the area of motherboard, the volume of whole computer also reduces, and the personal computer after industry generally will reduce is called BABY AT, and its motherboard then is called BABY AT motherboard.But because now the AT that uses is all the form of BABY AT, therefore generally all directly be called AT, below also follow this address.Because produce the division of labor that the industry characteristic of personal computer has height, so it is up to specification that the specifications of motherboard all needs, could cooperate multi-form computer cabinet, or different interface card is installed, the area of motherboard for example, the configuration of interface slot, or the position of screw hole all have regulation.
Though the specification of AT is followed by industry, but because the progress of hardware and software, the specification of AT is for the inapplicable a bit part of present personal computer, for example now because mouse (Mouse) has become the standard configuration of personal computer, but on the personal computer of AT specification, must install the RS232 serial port that connects mouse additional and could connect mouse, rather inconvenience in the use.Based on this reason, industry is developed another kind of ATX specification, and some interfaces commonly used can directly be provided on motherboard, cooperates the designed motherboard of this specification promptly to be called as the ATX motherboard.
Assembly on the pc board has a central processing unit (CentralProcessing Unit is hereinafter to be referred as CPU) at least at present, if provide the motherboard of multi-processor function that the CPU that surpasses more than then can be installed.Except that CPU, Accelerated Graphics Port (the Accelerated Graphics Port that connects video card on the motherboard in addition, hereinafter to be referred as AGP), install memory modules memory bank and can be for the peripheral assembly linkage interface (Peripheral Component Interconnect is hereinafter to be referred as PCI) that various interface card are installed.Except above assembly, other control circuit, major part all is that design is within a chipset (Chip Set).And chipset and above-mentioned CPU, internal memory, AGP slot, and the PCI slot all must is connected, so the pin position of chipset planning must the consideration chipset and the relevant position of other assembly.The processing data of especially present personal computer all is 32 (Bit) or more than 32, thus chipset respectively and CPU, internal memory, AGP slot, and the PCI slot between connecting line all far above hundreds of.On the other hand, at present the clock frequency used of CPU is more up to more than hundreds of MHz, thus when doing the wiring of motherboard, must be very careful, just can make the stable work of computer main frame panel of making.
Shown in Figure 1 is that (Ball Grid Array, chipset pin BGA) or the layout method between printed circuit board (PCB) adopt the chipset of this known pin layout to a kind of known ball grid array board, as the chipset of the numbering 440BX of Intel manufacturing.Chipset generally all is to adopt square flat pack, and thickness has only several centimetres, mainly contains two square planars, and wherein one side has the pin that is connected with other assembly for internal wiring, and one side is printed words identification in addition.Please refer to Fig. 1, when known printed circuit board layout, transmission line 11, transmission line 12 and transmission line 13 are arranged in parallel, and mutual inductance effect (Mutual Inductance) and transmission line are apart from becoming logarithmic relationship, even therefore strengthen the distance between two transmission lines on the printed circuit board (PCB), this kind wire laying mode also can't effectively reduce the mutual inductance effect between transmission line.The clock frequency of using at present CPU is up to hundreds of MHz when above, the wiring like this of the circuit of motherboard will make 12 pairs of transmission lines 11 of transmission line and transmission line 13 mutual inductance effect that produces more serious, and this mutual inductance effect also can cause producing between transmission line commissure (Cross-talk) effect, and this phenomenon will make the data on the transmission line make a mistake.
It shown in Figure 1A the vertical view of a plurality of transmission lines of known wiring.Wherein the self-induction that produced of transmission line 11 is L1, and the self-induction that transmission line 13 is produced is L2, and the self-induction that transmission line 12 is produced is Ls, and 12 pairs of transmission lines 11 of transmission line and the mutual inductance that transmission line 13 produced then are Lm.Wherein the width of transmission line is all 80um (micron), is spaced apart 70um between transmission line, and the length of transmission line is all 10000um.
It shown in Figure 1B the sectional view of Figure 1A.Please refer to Figure 1B, wherein h is the distance of printed circuit board (PCB) or ball grid array board upper strata cabling and ground plane, and its distance h is 100um in BGA, and the thickness d 1 of transmission line is 27um, and the thickness d 2 of ground plane is 35um.
Be various parameters shown in the table 1, use the Ansoft-Spicelink simulation software self-induction that object computer emulation is calculated under the situation of f=100MHz, mutual inductance value according to a plurality of transmission lines shown in Figure 1.
Table 1: self-induction, the mutual inductance value that emulation calculated uses a computer
| ?Ls | ?Lm | ?L1 | |
| The parallel wiring method | ?0.598 | ?0.321 | ?0.605 |
Unit: nH/mm (nanohenry profit/millimeter)
As shown in table 1 is known method self-induction, the mutual inductance value that emulation calculated that use a computer, as can be seen from Table 1, with the transmission line parallel wiring and can't reduce between transmission line mutual inductance and because of commissure phenomenon that mutual inductance produced.
Comprehensive above-mentioned discussion, the wiring method between known as can be known ball grid array board or printed circuit board (PCB) has following shortcoming:
Transmission line is adopted the parallel wiring method, and can't effectively reduce the mutual inductance effect between transmission line.Especially more than clock frequency that present CPU uses is up to hundreds of MHz, the wiring like this of the circuit of motherboard will make the mutual inductance effect between transmission line more serious.
Therefore, purpose of the present invention is exactly to be to provide a kind of structure that reduces mutual inductance between adjacent wires on substrate, when making it be applied in clock frequency, can effectively reduce mutual inductance effect and caused commissure phenomenon thereof between transmission line up to the motherboard circuit more than hundreds of MHz.Under the identical situation of the distance between centers of tracks (pitch) of transmission line, the mutual inductance between transmission line can be reduced near original about 1/4～1/6.This effect is especially unobvious when the ball grid array board of two-ply has ground plane.
The present invention is a kind of structure that reduces mutual inductance between adjacent wires on substrate, can be used on the wiring of computer main frame panel.Comprise the following steps: that (1) places the hollow transmission line of shape hollow between a plurality of transmission lines, one of a plurality of summits of this hollow transmission line are couple to milgraining (bondwire), in order to as the signal input point, another summit on a plurality of summits of hollow transmission line is couple to the perforation (via) on the plate, in order to as the signal output point; (2) will be couple to a plurality of summits mitered of the outer hollow transmission line of printed circuit board (PCB) or BGA Package with the prevention aerial radiation; (3) make the length of a plurality of minor faces of hollow transmission line equal half of signal wavelength.By above-mentioned steps, can effectively reduce the mutual inductance and the commissure phenomenon of signal.The following stated, except that specifying, transmission line all refers to solid transmission line, no longer lay special stress on.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, elaborate:
The drawing explanation:
Fig. 1 be a kind of known ball grid array board (Ball Grid Array, BGA) or the wiring method between printed circuit board (PCB);
Figure 1A is the vertical view of Fig. 1;
Figure 1B is the sectional view that contains 4 laminate BGA of ground plane;
Fig. 2 is the pattern figure of the hollow transmission line of a kind of structure that reduces mutual inductance between adjacent wires on substrate of the present invention;
Fig. 2 A is a vertical view of the present invention;
Fig. 2 B is a sectional view of the present invention;
Fig. 3 is the another kind of pattern figure of the hollow transmission line of a kind of structure that reduces mutual inductance between adjacent wires on substrate of the present invention.
Description of reference numerals:
11 to 13: transmission line
21,23: transmission line
22: the hollow transmission line
Embodiment one:
Please refer to Fig. 2, is the pattern of the hollow transmission line of a kind of structure that reduces mutual inductance between adjacent wires on substrate of the present invention.The configuration of transmission line 21,23 is as the transmission line 11,13 of Fig. 1, the transmission line 12 of Fig. 1 then replaces with the rectangle hollow transmission line 22 of a shape hollow, the one summit a or the b of hollow transmission line 22 are couple to printed circuit board (PCB) or BGA Package, in order to as the signal input point; Another summit b or a of hollow transmission line 22 are couple to printed circuit board (PCB) or BGA Package, in order to as the signal output point.The aerial radiation effect that is produced when preventing high frequency simultaneously will be couple to a plurality of summit c and the d mitered of the outer hollow transmission line 22 of printed circuit board (PCB) or BGA Package.In addition with the length setting of a plurality of minor face ad of hollow transmission line 22 and bc for transmitting half of signal wavelength.So configuration is application, especially clock frequency for a high frequency clock particular significant effect during greater than 1GHz, and frequency then is in order to shorten 1/2 wavelength greater than 1GHz, promptly for the consideration of practicality.Through after like this configuration, the phase place that two long limit ac and bd go up signal will be anti-phase fully.Therefore, almost be eliminated by magnetic field that electric current produced on two long limit ac and the bd and the mutual inductance that causes because of magnetic field.Because commissure effect and mutual inductance have very strong connection, so mutual inductance is eliminated nature commissure effect (Cross-talk) and also can be reduced effectively.
Please refer to Fig. 2 A, is vertical view of the present invention.The self-induction that transmission line 21 is produced is L1, and the self-induction that transmission line 23 is produced is L2, and the self-induction that hollow transmission line 22 is produced is Ls, and 22 pairs of transmission lines 21 of hollow transmission line and the mutual inductance that transmission line 23 produced then are Lm.Wherein the width of transmission line is all 80um (micron), and the spacing between transmission line is 70um, and the length of transmission line is all 10000um.
Please refer to Fig. 2 B, is sectional view of the present invention.Wherein h is the distance of upper strata cabling (top trace) and ground plane, and its distance h is 100um in BGA, and the thickness d 1 of transmission line is 27um, and the thickness d 2 of the ground plane of printed circuit board (PCB) is 35um.
The following stated is that simple formula is calculated in the easy mutual inductance of two-dimentional parallel cabling:
Lm/l＝(u/4Pi)ln(1+(2h/s)^2)??uH/m
L=length of transmission line wherein
The u=magnetic conductivity
Pi＝3.14159
The distance of h=transmission line and ground connection flat bed
The distance between centers of tracks (pitch=width+space) of s=two contiguous transmission lines approximately becomes logarithmic relationship with interval (space) by above-mentioned simple formula mutual inductance as can be known (Lm), so increase the interval and can't effectively reduce mutual inductance (Lm).
Shown in the table 2 various parameters according to a plurality of transmission lines and the hollow transmission line 22 of Figure 1 and Figure 2.Self-induction, the mutual inductance value of using the Ansoft-Spicelink simulation software to calculate when printed circuit board (PCB) or BGA plate have ground plane do one relatively with self-induction, mutual inductance value that the Computer Simulation mutual inductance computing formula of known parallel wiring method obtains simultaneously.By table 2 can it is evident that use known parallel wiring method at the transmission line width when 70um becomes 145um, the mutual inductance value is reduced to 0.279nH/mm from 0.321nH/mm between its transmission line, effect is not very remarkable.And the mutual inductance value that method of the present invention produced is about 0.076nH/mm, be 0.272 times in the mutual inductance value of using known method when being spaced apart 145um, to be produced, just use the mutual inductance value that method of the present invention produced to reduce-11.3dB under at interval at identical printed circuit board (PCB) with 145um.
Table 2: self-induction, mutual inductance value that the emulation formula that uses a computer is calculated
| ?Ls | ?Lm | ?L1＝L2 | |
| Parallel wiring method (space=70um) | ?0.598 | ?0.321 | ?0.605 |
| Parallel wiring method (spac=145um) | ?0.621 | ?0.279 | ?0.633 |
| Structure of the present invention (space=70um) | ?0.545 | 0.076 | ?0.559 |
Unit: nH/mm (nanohenry profit/millimeter)
Embodiment two:
Please refer to Fig. 3, is the another kind of pattern figure of the hollow transmission line of a kind of structure that reduces mutual inductance between adjacent wires on substrate of the present invention.Hollow transmission line 22 among Fig. 2 is the rectangle of hollow form, Fig. 3 then provides the another kind of pattern of hollow transmission line 22, it also is the rectangle of a hollow form, just its a plurality of long limit ac and bd slightly protrude in a plurality of minor face ad and bc one segment length, wherein a summit a or the b of hollow transmission line 22 are couple to printed circuit board (PCB) or BGA Package, in order to as the signal input point, another summit b or a of hollow transmission line 22 are couple to printed circuit board (PCB) or BGA Package, in order to as the signal output point.The aerial radiation effect that is produced when preventing high frequency simultaneously will be couple to a plurality of summit c and the d mitered of the outer hollow transmission line 22 of printed circuit board (PCB) or BGA Package.In addition with the length setting of a plurality of minor face ad of hollow transmission line 22 and bc for transmitting half of signal wavelength.Through after like this configuration, the phase place that two long limit ac and bd go up signal will be anti-phase fully.Therefore, almost be eliminated by magnetic field that electric current produced on two long limit ac and the bd and the mutual inductance that causes because of magnetic field.Because commissure effect and mutual inductance have very strong connection, so mutual inductance is eliminated nature commissure effect (Cross-talk) and also can be reduced effectively.
In addition, structure of the present invention is also applicable among printed circuit board (PCB) that ground plane is not provided or the BGA.Be shown in the table 3 in the printed circuit board (PCB) that ground plane is not provided, various parameters according to a plurality of transmission lines and the hollow transmission line 22 of Figure 1 and Figure 2, self-induction, the mutual inductance value of using aforementioned Computer Simulation mutual inductance computing formula to obtain simultaneously do one relatively with self-induction, mutual inductance value that the Computer Simulation of known parallel wiring method obtains.
Table 3: the emulation that uses a computer in the printed circuit board (PCB) of ground plane is not provided
The self-induction that the mutual inductance computing formula obtains, mutual inductance value
| ?Ls | ?Lm | L1＝L2 | |
| Parallel wiring method (space=70um) | ?1.08 | ?0.786 | 1.09 |
| Parallel wiring method (spac=145um) | ?1.1 | ?0.715 | 1.11 |
| Structure of the present invention (space=70um) | ?0.597 | ?0.125 | 1.1 |
Unit: nH/mm (nanohenry profit/millimeter)
By table 3 can it is evident that use known parallel wiring method at transmission line at interval when 70um becomes 145um, the mutual inductance value is reduced to 0.715nH/mm from 0.786nH/mm between its transmission line, effect is not very remarkable.And the mutual inductance value that structure of the present invention produced is about 0.125nH/mm, 0.175 times of the mutual inductance value that is produced when being to use known method and being spaced apart 145um, just be spaced apart the identical printed circuit board space of 145um under use the mutual inductance value that structure of the present invention produced can reduce-15.1dB.
From above discussion, the structure of the reduction mutual inductance between adjacent wires on substrate of the embodiment of the invention and known method relatively have following advantage as can be known:
Use the structure of reduction mutual inductance between adjacent wires on substrate provided by the present invention, when it is applied to clock frequency up to the motherboard circuit more than hundreds of MHz, can effectively reduce mutual inductance effect and caused commissure phenomenon thereof between transmission line.
Though the present invention with preferred embodiment explanation as above; but this embodiment is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when the change that can do a little and modification; for example the shaped slightly of the hollow transmission line 22 of hollow form can be done change, as for forms such as ellipse or tear drop shape can reach similar effect person, all in protection scope of the present invention.Therefore protection scope of the present invention should be with being as the criterion that claims were defined.
Claims (9)
1. structure that reduces mutual inductance between adjacent wires on substrate is characterized in that: comprising:
At least each transmission lines is positioned at the both sides of a hollow ring transmission line, and an end points of this hollow ring transmission line is connected to an assembly, and a diagonal end points of this hollow ring transmission line is connected on the substrate to import a signal;
The bond length of this hollow ring transmission line is 1/2nd of this signal wavelength.
2. the structure of reduction mutual inductance between adjacent wires on substrate according to claim 1 is characterized in that: described substrate is a printed circuit board (PCB).
3. the structure of reduction mutual inductance between adjacent wires on substrate according to claim 1 is characterized in that: described substrate is BGA Package (BGA).
4. the structure of reduction mutual inductance between adjacent wires on substrate according to claim 1 is characterized in that: described annular is the rectangle of sealing.
5. the structure of reduction mutual inductance between adjacent wires on substrate according to claim 1 is characterized in that: described annular is the rectangle of non-sealing.
6. the structure of reduction mutual inductance between adjacent wires on substrate according to claim 1 is characterized in that: the summit of described annular be mitered to reduce antenna effect.
7. the structure of reduction mutual inductance between adjacent wires on substrate according to claim 1 is characterized in that: described signal is the clock (clock) of high frequency.
8. the structure of reduction mutual inductance between adjacent wires on substrate according to claim 1 is characterized in that: the frequency of described signal is greater than 1GHz.
9. the structure of reduction mutual inductance between adjacent wires on substrate according to claim 1 is characterized in that: described substrate has ground plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01115309 CN1213640C (en) | 2001-04-18 | 2001-04-18 | Structure of reducing mutual inductance between adjacent wires on substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01115309 CN1213640C (en) | 2001-04-18 | 2001-04-18 | Structure of reducing mutual inductance between adjacent wires on substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1358059A true CN1358059A (en) | 2002-07-10 |
| CN1213640C CN1213640C (en) | 2005-08-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01115309 Expired - Lifetime CN1213640C (en) | 2001-04-18 | 2001-04-18 | Structure of reducing mutual inductance between adjacent wires on substrate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100484367C (en) * | 2005-10-26 | 2009-04-29 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board with high speed holding-wire wiring structure |
| US8099783B2 (en) | 2005-05-06 | 2012-01-17 | Atmel Corporation | Security method for data protection |
-
2001
- 2001-04-18 CN CN 01115309 patent/CN1213640C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8099783B2 (en) | 2005-05-06 | 2012-01-17 | Atmel Corporation | Security method for data protection |
| CN100484367C (en) * | 2005-10-26 | 2009-04-29 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board with high speed holding-wire wiring structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1213640C (en) | 2005-08-03 |
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