CN1425232A

CN1425232A - Power saving for MAC ethernet control logic

Info

Publication number: CN1425232A
Application number: CN00818508A
Authority: CN
Inventors: 詹姆斯·正寿·伊克; 林萧·王
Original assignee: Mitel Semiconductor VN Inc
Current assignee: Zarlink Semiconductor VN Inc
Priority date: 1999-12-20
Filing date: 2000-12-18
Publication date: 2003-06-18
Also published as: EP1243098A2; KR20020077366A; DE1243098T1; WO2001047188A3; WO2001047188A2; AU2275001A; TW488136B

Abstract

A media access controller (100) having a power-saving feature. The controller (100) comprises a receive logic circuit for receiving incoming data from a physical interface device (104) and processing the incoming data for transmission to a frame processor (102), and a transmit logic circuit for receiving outgoing data of the frame processor (102) and processing the outgoing data for transmission to the physical interface device (104). A power management control logic (114) operatively connects to each of the receive logic circuit and the transmit logic circuit to control the receive logic circuit and the transmit logic circuit in a first mode or a second mode. The power management control logic (114) controls the media access controller (100) in the first mode to conserve power by stopping operation of substantial portions of both the receive and transmit logic circuits, and in the second mode, which is a full power mode, by running both the receive and transmit logic circuits.

Description

The energy-saving scheme that is used for MAC Ethernet logic control circuit

Technical field

The present invention relates to a kind of media access controller, more specifically, the present invention relates to a kind of method that realizes energy conservation characteristic in media access controller, this method is by placing idle pulley to realize on one or more clocks of controller when the data packet traffic amount is very low.

Background technology

Internet development has been for to have brought huge commercial interest at line service, thereby developed a potential huge client source.For further opening up the market of these potentiality of being in the black, tens dollars capital investment is on hardware, software and bottom facilities.The hardware of bottom facilities comprises router and adapter, thereby they are used for packet sent elsewhere in the fan of data network footpath and make the manufacturer can contact the consumer or make the consumer can contact the manufacturer conversely.When because no matter hardware fault or multiple other is any former thereby when causing these data networks to break down is consumer or manufacturer, all very big loss can be arranged.

The main cause that hardware fault occurs is heating.Along with the raising of data transmission bauds, handling these data desired power also will increase.All have cooling fan on present most of high speed microprocessor, in case locking apparatus is owing to will bear ever-increasing data processing amount and heating burnout.But other device then must be in position, thereby sends data or receive data from network to the Internet or local area network (LAN).

For the Gigabit Ethernet that is about to occur, because the increase of data flow, the burden of Network Interface Unit will be more heavy, also be debatable and adopt mechanical cooling means.Need a kind of energy-saving system by improving the working life that energy efficiency prolongs these equipment.

Summary of the invention

This paper openly and claimed invention provide a kind of media access controller in an aspect therein with energy conservation characteristic.This controller comprises a receive logic circuit, and it is used for receiving the input data from a physical interface equipment, and the input data are handled, so that data are transmitted to a Frame Handler; Controller comprises that also sends a logical circuit, and it is used for outer data of received frame processor, and these outer data of sending out are handled, so that data are transmitted to said physical interface device.A power management control logic circuit is all remained valid with the transmission logical circuit with the receive logic circuit and is connected, so that receive logic circuit or transmission logical circuit are controlled under one first pattern or one second pattern.This power management control logic circuit quits work by the main part that makes reception, transmission logical circuit and media access controller is controlled under first pattern, thereby saving energy, and in second pattern following time as full lotus pattern, then make the receive logic circuit and send logical circuit to be in running status.

Description of drawings

For the present invention and advantage thereof are had comprehensive understanding, hereinafter will be described in conjunction with the accompanying drawings, in the accompanying drawings:

The block diagram of Fig. 1 has been represented execution mode disclosed herein;

Fig. 2 is a flow chart, expression be total process of the incident-activation handling process of a disclosed embodiment according to the present invention;

Fig. 3 is a more detailed flow chart, has represented the energy conservation characteristic when receiving incident for;

Fig. 4 is a more detailed flow chart, has represented the energy conservation characteristic when sending incident for;

Fig. 5 is a block diagram, has represented when adopting the independently clock source during interface of various and media;

Fig. 6 is a gate circuit diagrammatic sketch, expression be situation when being used for RMII type interface according to novel embodiment disclosed herein; And

Fig. 7 is the block diagram of a system, expression be that this system has a plurality of energy-conservation mac controllers.

Embodiment

Fig. 1 is a The general frame, has represented a mac controller 100 and has connected overall interface annexation to 102 and physics of a Frame Handler (FP) (PHY) interface 104 from this controller.Mac controller is handled the elementary stream between FP102 and the phy interface 104.Generally speaking, although mac controller 100 is in energy saver mode (or idle pulley) when initial, it can transfer full lotus operating state (or being operational mode) in response to detected one or more " incidents ".The receive logic circuit of mac controller 100 and transmission logical circuit all can be activated in response to the generation of a detected reception incident or the incident of transmission.Similarly, when both not detecting the reception incident and do not detect the transmission incident yet, receive logic circuit and send logical circuit and just all be placed in energy saver mode.Thereby, when initial, be in energy saver mode, when detecting from input packet that FP102 or phy interface 104 send, just make mac controller 100 change full lotus mode of operation into from energy saver mode as the MAC100 controller.

In an illustrated embodiment, this angle of data that will receive from physical interface 104, also process mac controller 100 passes to FP102 to be discussed in the reception aspect of mac controller 100, and this discussion simultaneously is idle condition when initial from mac controller 100.In order to handle to the input data of FP102 passing from phy interface 104, mac controller 100 must change operational mode into from energy saver mode.This work transfer process is in response to the event signal that phy interface 104 transmits and carries out.Mac controller 100 starts one corresponding " affairs " this event signal is responded, and judge whether need to rotate back into idle pulley before these affairs of end.This event signal is the carrier detect signal that phy interface 104 adopts according to common protocol, and those common protocols wherein for example are CSMA/CA (having the carrier sense multiaccess protocol that avoids conflict) and CSMA/CD (the carrier sense multiaccess protocol that has collision detection).(it should be noted that, although do not adopt LAN protocol herein, system among the disclosure embodiment also can with other protocol-compliant, if these agreements can indicate that communications transaction on LAN or communication medium has been activated and packet be about to come promptly can).Carrier detect signal is published on the network media by a network transfer equipment, it is as the omen that sends packet, it is detected by phy interface 104, and making has a corresponding signal to send to mac controller 100 through one or more receiving interface circuit 106 from phy interface 104.Receive data and control signal that phy interface circuit 106 has been admitted between mac controller 100 and the phy interface 104.

Receive logic circuit part at mac controller 100 " is revived " before in response to carrier detect signal, and data may be received in the buffer 108.This buffer 108 always is (this is because it receives the cause of clock pulses from a system clock that moves continuously 109) that work, its function is interim the preservation from the packet of phy interface 104 inputs, up to the receive logic circuit of mac controller 100 changes full lotus mode of operation into from energy saver mode till (for example being to finish in the time period in one or two clock signal).Buffer 108 comprises some flip and flop generator (not shown)s with the series connection of flowing water form, these flip and flop generators can provide enough caching functions, after the receive logic circuit becomes complete operating state, the inside that just data is sent to mac controller 100 receives in the logical circuit, to handle.Buffer 108 is connected with system clock 109 by one or more clock line 112, this system clock 109 is self-contained clocks of mac controller 100, and the operation of this clock is a continuous uninterrupted, thereby guarantee that buffer 108 is in active state at any time, so that can receive the input packet of phy interface 104.System clock is also driving each logical circuit of FP102, and this clock is connected to FP102 by FP system clock line 113.

A power management logic module 114 of implanting in the mac controller 100 is used to realize energy-conservation effect, and this logic module connects a certain or a few in receiving phy interface line 106, with the incident carrier detect signal of monitoring phy interface 104.Power management logic module 114 is intercepted signal and is responded and carry out such function to this: trigger the logic function (for example from idle pulley turning operation pattern) that needs mac controller 100 to carry out.More specifically, power management logic module 114 is that work at any time, and, specifically be the type which type of signal source of clock receive clock signal to depend on used phy interface 104 from from one or more signal source of clock receive clock pulse signals.Connect a selector logical circuit 116 (for example being a multiplexer), the corresponding suitable clock source of particular type of interface that is used to select Yu is adopted.For example, when adopting a RMII type interface (brief media stand-alone interface), the reference clock 110 of phy interface 104 is used to drive inner tranmitting data register TX CLX118 and internal reception clock RX CLX130.If adopted MII or GPSI type interface (USB (universal serial bus), this is a kind of 7 interface), then just can adopt original clock signal source 111, from this original clock signal of phy interface 104 output be original TX clock signal also be original RX clock signal.This original TX clock signal is driving TX CLX118, and original RX clock signal is then driving RX CLX130.TX CLX118 is used as the source clock in MII or GPSI type Application of Interface, and this is because it is more closely following the variation of original TX clock signal.Also can adopt system clock 109, but this will need more synchronizer logic circuit, and have the potential possibility make become longer time of delay between the moment of the incident of detecting and moment that MAC logical circuit 100 is started working.If what adopt is SMII type (serial MII), GMII (gigabit MII) or XGMII (extended pattern GMII) type interface, the original RX clock part of then utilizing reference clock 110 and original clock signal source 111 is as the clock source.Reference clock is used to produce the TX clock output signal, and this signal turns back to phy interface 104 again, and is same, and reference clock also is utilized for MAC control logic circuit 100 and produces TX CLX.If adopt other clock signal (signal in reference clock 110 and original clock signal source 111), then in order to realize that between signal source of clock (110 and 111) that control logic circuit must be done is more more complicated synchronously.Selector 116 connects to the PHY of outside reference clock 110 by one or more clock line 122; Connect to original clock signal source 111 by one or more clock line 120; And pass through 124 connections of one or more clock line to a self-contained tranmitting data register (TXCLX) 118.The output of selector 116 connects to power management logic circuit 114 by one or more clock line 128.The selector 116 corresponding signal source of clock of the particular type phy interface selecting and adopted 104 that can be configured to work independently, perhaps also can be configured to carry out work according to power management logic circuit 114 (not shown interconnection line), if make power management logic circuit 114 detect the type of phy interface 104, just control selector 116 and select the suitable clock signal source.

The arousal function of receiving unit is by realizing 130 and tranmitting data register 118 gatings of a gate receive clock (RX CLX) in the power management logic circuit 114, gating to RX CLX is undertaken by one or more receive clock control line 132, and the gating of TX CLX is undertaken by one or more tranmitting data register line 134.RX CLX130 receives FIFO control module (RX FIFO control module) 136 and receptions control logic module (RX control module) 138 to one clock signal is provided.RX control logic circuit 138 receives data by buffer interface line 140 from buffer 108, and the data form put in order, so that data are inserted among the asynchronous reception FIFO (asynchronous RX FIFO) 142, also check the integrality of data mode and data simultaneously.RX control logic circuit 138 also is connected with RX fifo control logic circuit 136 interfaces, to provide control signal to it.RX fifo control logic circuit 136 is in response to receiving the control signal of coming from RX control logic circuit 136, and the data that are input to asynchronous RX FIFO142 through RX control logic circuit 138 are carried out synchronously.

The control that data are sent to FP102 from asynchronous RX FIFO142 is to be coordinated by the RX fifo control logic circuit 136 of mac controller 100 and the control interface line 144 between the FP102.Data are that the asynchronous RX FIFO142 along one or more reception data-interface line 146 from mac controller 100 passes to the FP102.No matter be RX CLX130 or TXCLX118, when power management logic circuit 114 was judged all affairs relevant with transmit operation with the reception operation of MAC control logic circuit 100 and all finished, they were all closed down.But,,, read the postamble of data and this asynchronous RX FIFO142 up to FP102 and send signal and indicate and just stop when it has become emptying state so it can work on FP102 because asynchronous RX FIFO142 is asynchronous.

When as signal source of clock, reference clock 110 also provides commutator pulse by the sub-fraction of one or more clock line 148 in RX fifo control logic circuit 136; And provide commutator pulse to a sub-fraction that sends fifo control logic circuit (TX fifo control circuit) 150 by clock line 152; And a few register in asynchronous RX FIFO142 and asynchronous transmission FIFO (asynchronous TX FIFO) 154 sends commutator pulse (clock line for this two covers logical circuit is not expressed in the drawings).

The work that sends logical circuit in the mac controller 100 is the data that receive from FP102 " exhalation ", and these data are handled, to send it to phy interface 104.When FP102 is about to begin when setting about sending the Frame bag to PHY104, FP102 sends a letter signal to the transmission logical circuit of mac controller 100.This letter signal is interpreted as the second class incident by power management logic circuit 114.The transmission logical circuit that the TXCLX118 of power management logic circuit 114 by the gating gate wakes up in the mac controller 100 responds to this second event signal.In addition, started general process that one second affairs-begun are sent to the preparation of phy interface 104 and enforcement from FP102 with packet as to this part respond.These second affairs comprise and output to data among the asynchronous TX FIFO154 of mac controller 100 by one or more transmission interface line 156, and what the process that these data transmit was carried out side by side is intercommunication control signal between mac controller 100 and FP102, and the communication of control signal is to send on the control interface line 158 at the FP that leads to TXFIFO control logic circuit 150 to carry out.Determine that the time of transfer data packets realizes by TX CLX118 is carried out gating, TX CLX118 receives commencing signal and stop signals by one or more tranmitting data register line 134 from power management module 114.TX CLX118 provides timing signal to a TX fifo control logic circuit 150 and a transmission control logic module (TX control module) 160.TX control logic circuit 160 provides from asynchronous TX FIFO154 and has sent the data path that line 162 leads to phy interface 104 through physical interface, and provide control signal to TX fifo control logic circuit 150, so that the data that assign into from FP102 the asynchronous TX FIFO154 are carried out synchronously.The control signal of TX control logic circuit 160 outputs is also given power management logic circuit 114 with the communication of data transmit status.RX FIFO130 and TX FIFO118 are designed to mate the receiving velocity and the transmission rate of Ethernet respectively.When the Frame of sending out from FP102 finished, second kind of affairs (transmission affairs) stopped.It is if surpass the blanking time between Frame among a predetermined limits and the asynchronous TX FIFO154 for empty that the judgment data frame transmits the foundation that finishes.

As mentioned above, in order to make the energy-conservation interests maximization that brings, mac controller 100 has independently clock zone.Because RX/TX FIFO (being respectively 142 and 154) is asynchronous; and the control to RX/TX logical circuit of clock (being respectively 130 and 118) is the gate gating, so the main part in mac controller 100 logical circuits can be placed in idle pulley (being shutdown mode).When detecting when an effective connection having occurred between MAC100 and phy interface 104, said power-economizing method also can be saved power supply by shutting down in the free time during continuous data packet transmission.Determine when the startup power-saving technology and depend on a link pulse in some prior art, design system disclosed by the invention has more sane application: no matter be to receive packet or transmission packet, when continuing not see packet, just trigger power saving function, thereby the energy consumption of MAC circuit is significantly lowered.For example, gigabit Ethernet mac controller is operated on system's speed up to 125MHz, and high like this speed has very big influence to the life-span of chip, and the chip life-span is subjected to internal power consumption running time and the influence of the coolant mechanism that adopted.When the data packet traffic amount was low, the partial circuit that if can optionally close this mac controller 100 then can prolong the life-span of MAC circuit, also can not influence the throughput of packet simultaneously.Design system of the present invention also is applicable to the Ethernet of 10G.

Disclosed embodiment of this invention provides a kind of power-economizing method, thus, power management logic circuit 114 in the mac controller 100 can start RX FIFO130 and TX FIFO118 simultaneously in response to a detected incident, and when not having service needed to handle again, two clocks (being RX CLX130 and TX CLX118) unification is closed.Be understood that in an alternative, power management logic circuit 114 can be configured to RX CLX130 and TXCLX118 are controlled independently of each other, thereby to when the packet of phy interface 104 inputs is handled, TX CLX118 and relevant transmission logical circuit thereof can be in idle condition (promptly from FP102 to PHY104 without any data to be processed) at RX CLX130 and relevant receive logic circuit thereof.Similarly, if there is no import packet, RX CLX130 and correlation reception logical circuit thereof also can be in idle pulley, and TX CLX118 and interrelated logic circuit thereof then are in operational mode simultaneously, so that transmission is handled to the packet of phy interface 104.Last point, just as in disclosed embodiment above, receiving unit and send part and also can be in idle pulley simultaneously or be in operational mode simultaneously.

Need to prove: for the application scenario of CSMA/CD agreement, transmitter side also needs the data packet traffic on the network media is monitored, and carries out the moment that packet transmits to determine.For semiduplex environment, such measure is essential, in order to determine minimum interframe duration.In the Ethernet system of full duplex, do not need the network packet business of transmitter side is monitored.Thereby more reliable Logic Circuit Design will have the disposal ability to following three incidents: the RX on the receive logic circuit of mac controller 100 is excited incident; TX on the transmission logical circuit of mac controller 100 is excited incident; And the RX/TX on the partial logic circuit is excited incident, the data packet traffic on this partial logic circuit monitoring network media (in CSMA/CD uses).In the full duplex system, only just can drive RX/TX and be excited incident with the TX incident.

Flowcharting among Fig. 2 the overall various aspects of a preferred embodiment.To the discussion of this overall process when the supposition system is in idle condition (power management logic circuit 114 places stop mode with the RX CLX130 and the TX CLX118 of mac controller 100 before this).Flow process starts from a starting module, and shifts to a judge module 200, to judge whether to have taken place foregone conclusion spare.Unique restriction comes from individual's resolution of mac controller 100 designers to event number that can be detected.If judged result negates, then flow process is from functional block 202 of " N " route turning, in this module, RX CLX130 and TXCLX138 keep stop mode constant, and this stop mode has been closed the function of main body circuit part in mac controller 100 all circuit.Then, flow process turns back to the input point of judge module 200 from functional block 202, to continue to carry out the process whether event occurs that detects.On the other hand, if the incident predesignated has taken place, then flow process just turns to " Y " path of judge module 200, and leads to a functional block 204, thereby starts the work of transmitting clock (being respectively 118 and 130) that receives.

Flow process moves on and arrives judge module 206 places, to judge that whether detected incident is with relevant from phy interface 104 reception data.If judge it is sure, then flow process produces a functional module 208 from " Y " path, begins the corresponding affairs of this reception incident are handled.Then, flow process moves on and arrives a judge module 210, is used to judge that these receive affairs and whether are done.Also do not finish if receive affairs, then flow process just jumps to a functional module 212 from " N " path, makes reception/tranmitting data register (130 and 118) continue operation, thereby can finish said affairs.Whether then, the input point of judge module 210 is returned in the output point recirculation of functional block 212, finish to continue all affairs of monitoring.If reception/transmission affairs are finished, then flow process produces the functional module 214 from " Y " path of judge module 210, to stop the work of reception/tranmitting data register (130 and 118), thus mac controller is placed energy saver mode.

If at first detected incident is not a reception incident in judge module 200, then flow process just produces the judge module 216 from " N " path of judge module 206, to determine whether this incident is a transmission incident, if the result is sure, then flow process enters into a functional module 210 from " Y " path, judges whether that all affairs all finish.Afterwards, flow process just continues to carry out according to above-mentioned process.On the other hand, if detected incident is not a transmission incident, then flow process just forwards to the functional module 220 from " N " path of judge module 216, to take action according to the error detection situation that may occur.These action may comprise data frame re-transmission request signal of transmission; Or enter a holding state; Or a mark is set, be used to indicate and Frame occurred and detect mistake; Or carry out the operation that some other can be taked.Flow process enters into functional module 214 then, to stop the work of RX CLX130 and TX CLX118.Need to prove: this flow chart has only been described two incidents has been detected.But method disclosed herein is not limited to this two incidents, can detect incident but can have more, and this depends on freely deciding of designer.Whether as shown in the module 214, after clock work was stopped, flow process turned back to the input point place of judge module 200, have receiving/transmitting event to take place to continue monitoring.

It will also be appreciated that: the work of this system also can detect a plurality of different incidents simultaneously.For example, a detected reception incident causes mac controller 100 to be placed in operational mode.When in operational mode, may detect the incident that sends data from FP102 and take place, this incident also can cause power management logic circuit 114 will receive/tranmitting data register remains in the operational mode.The actual effect that had not only detected the reception incident but also detected the transmission incident is the same: promptly started reception/tranmitting data register (130 and 118).Thereby, just can handle a plurality of incidents and corresponding affairs simultaneously.

At work, an Event triggered affairs, these affairs are finished a job.When detecting an incident, reception/tranmitting data register (130 and 118) is just started working, and keeps operating state all to finish up to correspondent transaction always.Owing in the network service trade transactions, be usually directed to many Frames (and may be on both direction) in the per second, so can occur a plurality of transmissions/reception incident and affairs simultaneously to sending.Thereby, at reception/tranmitting data register because finishing of certain affairs and before will quitting work, the inspection that must make an overall situation is to have judged whether that other incident or affairs are still in process.If the result who judges is sure, then must keep the running status of clock, till all incidents and affairs have all been finished.After all affairs are all finished, clock will be stopped (being about to clock resetting in idle pulley) with the saving electric energy, and wait for the arrival of another incident.

In the disclosed embodiment, can detected incident for mac controller and corresponding affairs are contents as described below.When phy interface 104 detected carrier signal on the network media, power management logic circuit 114 just was interpreted as this fact an incident, and it is indicating that Frame will come.The corresponding affairs of being carried out by MAC control logic circuit 100 are that the Frame (one or more) that will receive is transferred among the FP102.When FP102 read postamble (EOF) data from asynchronous RX FIFO142 output, affairs had just been finished.When MAC control logic circuit 100 receives frame when sending request signal from FP102, another kind of incident has just appearred.The corresponding affairs of being carried out by MAC control logic circuit 100 this moment are that the packet of FP102 output is handled, and packet is sent to phy interface 104.After Frame has been sent out and minimum interframe time interval when having expired, these affairs have just been finished.Expiring of the interframe time interval shows that then this subsequent data frame should occur if there is another Frame to follow behind this first Frame in this aforementioned time period.If there is not appearance Frame subsequently at this moment, then just can infer does not have Frame to arrive again.Assert that another requirement that these affairs have terminated is will be vacant state in the asynchronous TX FIFO154.

Fig. 3 has represented a more detailed flow chart, has represented mac controller 100 new features disclosed according to the present invention and the corresponding affairs carried out when receiving incident.Hereinafter discuss to be under the current prerequisite that is in idle condition of supposition mac controller, to launch.Flow process starts from a starting point, and shifts to a judge module 300, and to judge whether to have taken place a reception incident, this receives being meant of incident and detects a situation from the carrier detect signal of phy interface 104 outputs.If the result negates that then flow process just produces from " N " path, and rotates back into the input point of judge module 300, the reception incident whether occurred to continue monitoring.If detect an incident, then flow process is exactly to produce the functional module 302 from " Y " path of judge module 300, with the work of beginning RX CLX110 (and TX CLX118).When RXCLX110 starts working, may there be one or more Frames to be sent to, and have temporarily been suffered at buffer 108 from phy interface 104.Then, flow process turns to a functional module 304, and the packet that receives in this module is handled by the receive logic circuit in the mac controller 100.This processing procedure comprises data is pressed in the RX control logic circuit 138 by the clock beat, checks the integrality of data mode and data, then its form is reformed, so that be inserted among the asynchronous RX FIFO142.Then, mac controller 100 sends to FP102 with Frame.This operation is finished by RX fifo control logic circuit 136, and control logic circuit 136 keeps communication to exchange to coordinate the data frame transfer from asynchronous RXFIFO142 with FP102.

Whether finish in order to detect the affairs of carrying out for this reception incident, will satisfy two criterions at least: 1) FP102, and 2 if must detect postamble signal (EOF)) be necessary for sky among the asynchronous RX FIFO142.For this purpose, when the processing data packets process finished, flow process just entered into a functional module 306, and so that the EOF data are written among the asynchronous RX FIFO142, this EOF has just been detected by FP102 then.Flow process enters into a functional module 308, to empty continuous-flow type (pipeline) the received signal device in the receive logic circuit.Flow process enters into a judge module 310 then, to judge whether to have detected another reception incident.If the result is sure, then the flow process input point that produces functional module 304 from " Y " path continues the cycle of treatment of packet.If do not detect other reception incident again, flow process just produces " N " path and arrives functional module 312, to stop the work of RX CLX130.But as mentioned above, RX CLX130 and TX CLX118 work together.Thereby, if judge again not from phy interface 104 and receive other packet and when turn-offing RX CLX130, the affairs inspection that power management logic circuit 114 also should be carried out an overall situation with guarantee close do not have other between two clocks (130 and 118) affairs still in commission.If do not have other incident or affairs to be in the execution, then all two clocks (130 and 118) just are stopped, and flow process moves on and arrive the input point of judge module 300 from the output point of functional block 312, thereby continue the reception incident is monitored.Power management logic circuit 114 is monitoring at the receive logic circuit and is sending in the logical circuit processing to packet.No matter be at the receive logic circuit or in the transmission logical circuit, as do not have packet to be carried out processing just to trigger power management logic circuit 114 and carry out a global-inspection, closing between two clocks (130 and 118) without any the incident and the affairs that are in the active state guaranteeing.

Fig. 4 has represented a more detailed flow chart, has represented the energy conservation characteristic when sending incident for.Flow process starts from a starting point, and enters into a judge module 400 subsequently, to judge whether needing to start full-duplex operation in the receive logic circuit owing to just there being the input data to be received.Send logical circuit and be triggered to operating state owing to the receive logic circuit can be independent of, and also set up conversely, thereby be understood that and require the receive logic circuit to be in full lotus operating state, just can start transmit operation.Thereby whether judge module 400 is also to having the reception incident to test.If do not need to carry out full-duplex operation owing to detect the reception incident, flow process just is moved out to another judge module 402 from " N " path of judge module 400, has begun in asynchronous TX FIFO154 to determine whether a new job.If there is not Frame to be written among the asynchronous TX FIFO154, flow process just from the input point of " N " route turning judge module 400, is monitored any other incident (reception incident or transmission incident) with continuation.By frame head data being written among the asynchronous TX FIFO154, FP102 begins to carry out process of transmitting.When this operation was judged module 402 and detects, flow process just produced the functional module 404 from " Y " path, to start the work of TX CLX118.As default situation, RX CLX130 is as mentioned above also to be activated.Flow process enters into a functional module 406 then, in this functional module, is written to the phy interface 104 from FP102 output and by the data that mac controller 100 is handled.Then, flow process moves on and arrives in the judge module 408, judges whether this write operation is finished.If do not finish, flow process just forwards the input point of functional module 406 to from " N " path, to continue to carry out the operation that writes data in the phy interface 104.

If this ablation process has been finished, flow process just enters into functional module 410 from " Y " path of judge module 408, measuring the interframe time interval (IFG), and this numerical value is loaded in the register.Flow process enters into a judge module 412 then, judges whether this IFG duration expires.The expiring of this time limit just shows unlikelyly have packet to send from FP102 again, can be interrupted to transmission (or writing) operation of phy interface 104.To being sent out the Frame that logical circuit is handled, all measure the IFG time between them for each.If the IFG time does not expire, then flow process enters into the input point of functional module 410 from " N " path of judge module 412, thereby continues to measure the IFG time, and time value is encased in the register, so that inquire about.Flow process enters into another judge module 414 from " Y " path of judge module 412, judges whether that new Frame is inserted among the asynchronous TX FIFO154.If answer is sure, flow process just forwards the input point of functional module 406 to from " Y " path, thereby begin to carry out the affairs that input data frame is handled, and Frame is written in the phy interface 104, all in turn carry out this operation for each frame data that is packed among the asynchronous TX FIFO154.If there are not new data to be inserted among the asynchronous TX FIFO154, then flow process just forwards to the judge module 416 from " N " path of judge module 414, comes global process's situation of monitoring incident and affairs again.If other incident and affairs still are in the process, then the flow process input point that just forwards functional module 410 from " Y " path to continues to carry out the operation of measuring the IFG time.If do not have other incident and affairs just processed, then flow process just from functional module 418 of " N " route turning, stops the work of TX CLX118.Then, flow process turns back to the input point of judge module 400, and begins process again by monitoring any incident.If judge module 400 does not detect incident, flow process just starts the work of TX CLX118 from functional module 420 of " Y " route turning.After coming out from functional module 420, flow process arrives the input point of functional module 410, to start measurement and loading to the IFG time.

Block diagram among Fig. 5 has been represented the signal source of clock when using the multiple interface that is independent of media.If interface is the RMII type, the signal source of clock of power management logic circuit 114 just is the reference clock 110 of phy interface 104 outputs.When interface was MII or GPSI type, the original TX clock signal 500 of the existing phy interface device 104 of the signal source of clock of power management logic circuit 114 also had the original RX clock signal 502 of phy interface device 104.Be under the situation of GMII or XGMII at interface for example, the source clock pulse of power management logic circuit 114 is to obtain from the reference clock 110 of phy interface 104 and original RX clock signal 502.At the MII interface is under the situation of GMII or XGMII type, be subjected to the tranmitting data register output 504 of power management logic circuit 114 controls also to be returned to interface 104, and this clock output does not stop.Under any circumstance, power management logic circuit 114 all is possessed of control power to RX CLX130 and TXCLX118.

Clock zone line of demarcation 506 has shown to receive fifo logic circuit 508 and send fifo logic circuit 510 provides clock signal by RX CLX130 and TX CLX118 respectively in the course of the work, and receives and send in the logical circuit (508 and 510) all some from system clock 109 receive clock pulses.

Fig. 6 is according to the shown gate circuit figure in RMII type interface environment of disclosed novel embodiment.As mentioned above, in this facility environment, the RMII reference clock signal 600 of reference clock 110 is used as the source time-of-the-day order of carrying out power management control.RX CLX signal 602 and TX CLX signal 604 are respectively by clock line 606,608 and synchronous with RMII reference clock signal 600.RMII reference clock signal 600 also is connected to one by clock line 614 and 614 respectively and receives on 610 and energy-conservation triggers of transmission of energy-conservation trigger (RX energy-saving appliance) (TX energy-saving appliance) 612, is used for providing clock pulse to them.The control signal of waking up of RX energy saver 610 is connected to a RX and wakes up on the input point 618, do not receive when professional to carry out to FP102 input packet when detecting from phy interface 104, closing control input signal 620 (show that RX affairs finish) has just started closing control again.Similarly, TX energy saver 612 has a TX and wakes input 622 up, when writing frame signal for one that detects that FP102 sends, energy saver will send logical circuit and place operational mode, and do not detecting from FP102 when phy interface 104 transfer data packets are professional carry out to send, closing control input signal (show that TX affairs finish) just begins to exercise closing control.The full duplex input can start full duplex work control at the appropriate time.

Fig. 7 is a system block diagram, and this system has adopted a plurality of subsystems, and each subsystem all may operate under the energy saver mode.System 700 (for example being a network changing-over device) comprises a plurality of subsystems (702,704,706 and 708), these subsystems are the equipment that is co-located in the consolidated network, for example be router, changing-over device, hub etc., and all adopted energy conservation characteristic disclosed herein in each subsystem.For example, system 700 is operated on the network media 710, be used for the data of leading to one or more subnettings (being also referred to as subnet) are carried out route guiding, each subnet of distinguishing mutually all is associated with a corresponding subsystem (702,704,706 or 708) respectively.As shown in the figure, system 700 is designed to have a center system power source management controller 712, comes to control by a strip system data and control bus 714 gated clock of each subsystems (702,704,706,708) with it.In this specific embodiment, power supply managing module 712 has just avoided being provided with each single power management logic control module 114 in each subsystem (702,704,706 and 708) situation is set.

At work, the Frame in the network media is to be transported in certain predetermined subnet by addressing, and only needs one of them subsystem (702,704,706 and 708) to be waken up these data are handled.For example, if data are placed on the media 710, and carried to first subnet that is associated with first subsystem 702 by addressing, then one first subsystem physical interface 716 just detects carrier detect signal, and gives power supply managing logical circuit 712 to the testing result of this signal through system's phy interface bus 718 circulars.Then, a receive clock of a mac controller 720 is (not shown in power supply managing logical circuit 712 gatings first subsystem 702, but be similar to RX CLX110), to start receive logic circuit (not shown, but be similar to) above with reference to the disclosed reception of Fig. 1 RX logic control circuit 130, RX fifo control circuit 136 and asynchronous RX FIFO142.Afterwards, mac controller 720 sends signal to its relevant Frame processor 722, notifies its Frame to be about to carry out frame and handles, and data are sent to Frame Handler 722.The operating process that continues execution subsequently is just identical with transmission shown in Figure 1 process partly, and for overall power-save operation, then whether power supply managing controller 712 may be according to existing data to close or start the reception/tranmitting data register of gate in the mac controller 720.

Described like that at the work of the mac controller among Fig. 1 100 as mentioned, may have a plurality of incidents or affairs and take place simultaneously.Similarly, in disclosed system embodiment, not only in same subsystem, have a plurality of incidents and affairs take place simultaneously, and, also have a plurality of incidents and affairs and take place simultaneously with respect to each subsystem (702,704,706 and 708).For example, when mac controller 720 in the subsystem 702 reception/when the transmission logical circuit was in idle pulley, 724 of mac controllers may start reception/transmission logical circuit in response to the incident of its receive logic circuit working of needs in the subsystem 704.Thereby when being in full lotus work, the other parts in each subsystem then may still be under the energy saver mode at the different aspect of each subsystem.

In an alternative, owing to independent separately power management logic circuit (as mentioned with reference to power management logic circuit 114 disclosed the sort of circuit) can be set, in each subsystem (702,704,706 and 708) so system 700 can save center system power management logic circuit 712.Like this, each subsystem module just can work alone according to foregone conclusion spare.

In another kind of alternative embodiment, system had both comprised a center system power management module 712, also in each subsystem (702,704,706 and 708), be provided with independent power management module 114, these module co-operation, and intercommunication mutually, so that realize disclosed energy conservation characteristic.

As mentioned above, novel feature disclosed in this invention is applicable to dissimilar physical interfaces.For example this power conservation feature is applicable to GPSI 7 interfaces, MII, RMII, SMII and gmii interfaces.The MII interface is a part of content in Fast Ethernet (Fast Ethernet) standard, and it has replaced the AUI interface (being Attachment Unit Interface) in the 10Base-T type Ethernet.MII is used to medium layer 100 is connected to physical layer 104.The RMII standard will reduce to 7 pins from every port one 6 pins as the concrete integrated circuit and the interface between the transceiver of mac controller 100, and SMII can be further the pin number of the every port of interface to be reduced to only be 2 pins.

Although above preferred embodiment has been made detailed description, but be understood that change, replacement and the change that can make various ways under the prerequisite that does not depart from the scope of the invention and design philosophy to preferred embodiment, wherein the scope of the invention is limited by the accompanying claims.

Claims

1. media access controller that can save energy, it comprises:

One is used for handling so that with the receive logic circuit of data transmission to a Frame Handler from physical interface equipment reception input data and to said input data;

One it be used to receive outer data of said Frame Handler and the said outer data of sending out handled data are transmitted the transmission logical circuit to said physical interface equipment; And

A power management logic control circuit, it is remained valid with said transmission logical circuit with said receive logic circuit and is connected, so that said receive logic circuit and said transmission logical circuit are controlled under one first pattern or one second pattern;

Wherein, said power management logic control circuit quits work by the main part that makes said reception, transmission logical circuit and media access controller is controlled under said first pattern, thereby saves energy;

Wherein, said power management logic control circuit is controlled at media access controller under said second pattern by making said receive logic circuit and said transmission logical circuit be in running status, and this pattern is full lotus operational mode.

2. controller according to claim 1 is characterized in that: said power management control logic circuit can be in response to the testing result of an event signal and control one or more clock circuits in said reception/transmission logical circuit.

3. controller according to claim 2 is characterized in that: said event signal is that of said physical interface is by the detected carrier detect signal of media access controller.

4. controller according to claim 3 is characterized in that: said event signal is that of said physical interface is by the detected carrier detect signal of said power management logic control circuit of media access controller.

5. controller according to claim 4, it is characterized in that: said power management logic control circuit detects said carrier detect signal, and starts a receive clock circuit in said one or more clocks of said receive logic circuit in response to the said carrier detect signal that is detected.

6. controller according to claim 5, it is characterized in that: said power management logic control circuit detects said carrier detect signal, and starts a receive clock and a tranmitting data register in said one or more clocks of said receive logic circuit in response to the said carrier detect signal that is detected.

7. controller according to claim 2, it is characterized in that: said event signal is a letter signal that is sent to media access controller from said Frame Handler, and the said outer data of sending out of said letter signal advice media access controller will arrive from said Frame Handler.

8. controller according to claim 7 is characterized in that: the said power management logic control circuit of said media access controller detects said letter signal, and starts a tranmitting data register of said transmission logical circuit in response to this signal.

9. controller according to claim 7 is characterized in that: said letter signal is a beginning write data signal, and this signal occurred write data in the said transmission logical circuit of media access controller before.

10. controller according to claim 7, it is characterized in that: the said power management logic control circuit of media access controller detects said letter signal, and starts a tranmitting data register of said transmission logical circuit and a receive clock of said receive logic circuit in response to this signal.

11. controller according to claim 2, it is characterized in that: have a transaction response to begin in the result who detects said incident to carry out, said power management logic control circuit is being monitored the process of said affairs, and controls said receive logic circuit and said transmission logical circuit according to the state of said affairs.

12. controller according to claim 11, it is characterized in that: when being handled by said receive logic circuit and said transmission logical circuit without any affairs, said power management logic control circuit just places media access controller under the said energy saver mode again.

13. controller according to claim 11 is characterized in that: if having at least affairs still being handled by said reception/transmission logical circuit, then said power management logic circuit just remains on media access controller said full lotus mode of operation.

14. controller according to claim 11 is characterized in that: the said affairs of said receive logic circuit are included in said input data are sent to said Frame Handler carries out form arrangement, inspection data mode and data before to said input data integrality.

15. controller according to claim 14 is characterized in that: when a postamble signal is written to one of said receive logic circuit when receiving among the FIFO, the said service termination of said receive logic circuit.

16. controller according to claim 11 is characterized in that: when an interFrameGap duration surpasses a predetermined value, the said service termination of said transmission logical circuit.

17. controller according to claim 11 is characterized in that: when a transmission FIFO of said transmission logical circuit is sky, the said service termination of said transmission logical circuit.

18. controller according to claim 1 is characterized in that: said power management logic control circuit is according to the type of coupled said physical interface and from the pulse of one or more signal source of clock receive clock.

19. controller according to claim 18 is characterized in that: be the reference clock of said physical interface equipment one of in said one or more signal source of clock.

20. controller according to claim 18 is characterized in that: be an original transmission/receive clock of said physical interface equipment one of in said one or more signal source of clock.

21. controller according to claim 18 is characterized in that: be a tranmitting data register of said transmission logical circuit one of in said one or more signal source of clock.

22. a method that makes media access controller have energy conservation characteristic, the method comprising the steps of:

Import Data Receiving to a receive logic circuit of media access controller from a physical interface equipment handle, and said input data are handled, so that data are transmitted to a Frame Handler;

Send to a transmission logical circuit of media access controller with sending out data outward from said Frame Handler, and this is sent out data outward handle, so that data are transmitted to said physical interface equipment; And

Control said receive logic circuit and said transmission logical circuit with one with their power management logic control circuits that is connected of remaining valid, so that said receive logic circuit and said transmission logical circuit are controlled under one first pattern or one second pattern;

Wherein, said power management control logic circuit quits work by the main part that makes reception, transmission logical circuit and media access controller is controlled under first pattern, thereby saves energy;

23. method according to claim 22, it is characterized in that: in the controlled step therein, said power management control logic circuit can be in response to the testing result of an event signal and control one or more clocks in said reception/transmission logical circuit.

24. method according to claim 23 is characterized in that: said event signal is that of said physical interface equipment is by the detected carrier detect signal of media access controller.

25. method according to claim 24 is characterized in that: said event signal is that of said physical interface is by the detected carrier detect signal of said power management logic control circuit of media access controller.

26. method according to claim 25, it is characterized in that: in the controlled step therein, said power management logic control circuit detects said carrier detect signal, and starts a receive clock in said one or more clocks of said receive logic circuit in response to the said carrier detect signal that is detected.

27. method according to claim 26, it is characterized in that: in the controlled step therein, said power management logic control circuit detects said carrier detect signal, and starts a receive clock and a tranmitting data register in said one or more clocks of said receive logic circuit in response to the said carrier detect signal that is detected.

28. method according to claim 23, it is characterized in that: said event signal is a letter signal that is sent to media access controller from said Frame Handler, and the said outer data of sending out of said letter signal advice media access controller will arrive from said Frame Handler.

29. method according to claim 28 is characterized in that: in the controlled step therein, said power management logic control circuit detects said letter signal, and starts a tranmitting data register of said transmission logical circuit in response to this signal.

30. method according to claim 28 is characterized in that: said letter signal is a beginning write data signal, and this signal occurred write data in the said transmission logical circuit of media access controller before.

31. method according to claim 28, it is characterized in that: in the controlled step therein, said power management logic control circuit detects said letter signal, and starts a tranmitting data register of said transmission logical circuit and a receive clock of said receive logic circuit in response to this signal.

32. method according to claim 23, it is characterized in that: have a transaction response to begin in detected said incident to carry out, said power management logic control circuit is being monitored the process of said affairs, and controls said receive logic circuit and said transmission logical circuit according to the state of said affairs in controlled step.

33. method according to claim 32, it is characterized in that: when being handled by said receive logic circuit and said transmission logical circuit without any affairs, said power management logic control circuit just places media access controller under the said energy saver mode again.

34. method according to claim 32 is characterized in that: if having at least affairs still being handled by said reception/transmission logical circuit, then said power management logic circuit just keeps the said full lotus mode of operation of media access controller.

35. method according to claim 32 is characterized in that: the said affairs of said receive logic circuit are included in said input data are sent to said Frame Handler carries out form arrangement, inspection data mode and data before to said input data integrality.

36. method according to claim 35 is characterized in that: when a postamble signal is written to one of said receive logic circuit when receiving among the FIFO, the said service termination of said receive logic circuit.

37. method according to claim 32 is characterized in that: when an interFrameGap duration surpasses a predetermined value, the said service termination of said transmission logical circuit.

38. method according to claim 32 is characterized in that: when a transmission FIFO of said transmission logical circuit is sky, the said service termination of said transmission logical circuit.

39. method according to claim 22 is characterized in that: said power management logic control circuit is according to the type of coupled said physical interface and from the pulse of one or more signal source of clock receive clock.

40., it is characterized in that: be the reference clock of said physical interface equipment one of in said one or more signal source of clock according to the described method of claim 39.

41., it is characterized in that: be the original transmission/receive clock of said physical interface equipment one of in said one or more signal source of clock according to the described method of claim 39.

42., it is characterized in that: be a tranmitting data register of said transmission logical circuit one of in said one or more signal source of clock according to the described method of claim 39.

43. one is used for realizing energy-conservation system at a plurality of media access controllers, this system comprises:

A plurality of media access controllers that effectively are connected with the corresponding physical interface equipment respectively, each media access controller has:

One is used for receiving the input data from said corresponding physical interface equipment, and with the receive logic circuit of said input data transmission to a Frame Handler;

Outer data that are used to receive said Frame Handler, and with said outer transmission logical circuit from the data transmission to said corresponding physical interface equipment that send out;

Be used for said input data and the said outer one or more Frame Handlers that effectively are connected with said a plurality of media access controllers that send out that data handle; And

With each said receive logic circuit and the power management logic control circuit that said transmission logical circuit effectively is connected, be used for the media access controller of correspondence is controlled at one first pattern or one second pattern;

Wherein, said power management logic control circuit quits work by the main part that makes said reception, sends logical circuit and the media access controller of correspondence is controlled under first pattern, thereby saves energy;

Wherein, said power management logic control circuit is by making said receive logic circuit and said transmission logical circuit and be in running status and media access controller being controlled under said second pattern, and this pattern is full lotus operational mode.

44. according to the described system of claim 43, it is characterized in that: said power management logic circuit effectively is connected with said transmission logical circuit with the said receive logic circuit of each media access controller, thereby can some selected media access controller in a plurality of media access controllers be placed said first pattern or said second pattern in response to one or more detected incidents, wherein, detected incident is to be associated with those media access controllers of selecting from a plurality of media access controllers.

45. according to the described system of claim 44, it is characterized in that: said detected incident is a carrier detect signal of said physical interface equipment, and this signal is detected by said power management logic control circuit.

46. according to the described system of claim 44, it is characterized in that: said detected incident is a beginning write data signal of said Frame Handler, and this signal is detected by said power management logic control circuit.

47. according to the described system of claim 43, it is characterized in that: when the one or more incidents corresponding with certain media access controller are detected, said power management logic control circuit should be controlled under said second pattern by the correspondence media access controller, and when this correspondence media access controller all affairs relevant with said one or more incidents all no longer were in the process, said power management logic control circuit should place under said first pattern by the correspondence media access controller.