CN1503939A - 多项式算术运算 - Google Patents

多项式算术运算 Download PDF

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CN1503939A
CN1503939A CNA028085418A CN02808541A CN1503939A CN 1503939 A CN1503939 A CN 1503939A CN A028085418 A CNA028085418 A CN A028085418A CN 02808541 A CN02808541 A CN 02808541A CN 1503939 A CN1503939 A CN 1503939A
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instruction
polynomial
register
result
polynomial arithmetic
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CN100422926C (zh
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M・斯特里贝克
M·斯特里贝克
基斯塞尔
K·D·基斯塞尔
锒
P·帕里尔
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Arm Overseas Finance Co ltd
Overpass Bridge Co ltd
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MIPS Technologies Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G06F7/725—Finite field arithmetic over elliptic curves

Abstract

提供了指令集体系结构(ISA)中的多项式运算指令(3010)。还提供了多项式乘－加(MADDP)指令和多项式乘(MULTP)指令(3013)。

Description

多项式算术运算
技术领域
本发明涉及用于执行多项式算术的微处理器指令，具体说涉及用于执行多项式乘法运算的微处理器指令。
背景
当业界朝向更庞大更复杂的指令集发展时，开发出了精简指令集计算机(RISC)体系结构。通过简化指令集设计，RISC体系结构使得应用例如流水线和高速缓冲技术更为容易，从而提高了系统的性能。
RISC体系结构一般具有在指令格式上几乎没什么变化的固定长度指令(例如16位，32位或64位)。指令集体系结构(ISA)中的每个指令可具有总处于相同位置的源寄存器。例如，32位ISA可具有总由位16-20和21-25指定的源寄存器。对每条指令而言，这允许无需任何复杂的指令译码就可读取指定寄存器。
概述
加密的系统(“密码系统”)越来越多地用于确保交易安全，对通信加密，对用户进行认证以及保护信息。许多专用密钥密码系统(例如数字加密算法(DES))，在计算上相对简单，并且常常可简化为对数据块进行一系列异或(XOR)、循环和置换运算的硬件解决方案。而另一方面，公共密钥密码系统比专用密钥密码系统在数学上更巧妙且在计算上更困难。
虽然不同的公共密钥密码系统方案依据不同的数学基础，但是它们往往都需要在数量级为1024位的大数值范围内进行整数运算。扩展精度运算常常基于模数(即以某个值域为模进行的运算)，而在某些情况下则是基于二进制多项式而非二进制补码。例如，RSA公共密钥密码系统采用扩展精度模取幂来对信息加密和解密，而椭圆曲线密码系统采用扩展精度模多项式乘法对信息加密和解密。
公共密钥密码系统已经广泛用于用户认证和安全密钥交换，而专用密钥密码系统广泛用于加密通信通道。随着公共密钥密码系统的应用增多，希望能够提高扩展精度模算术运算的性能。
一般而言，指令集体系结构包括用于执行多项式算术的指令。该指令包括一个或多个将此指令识别为用于执行多项式算术运算的指令的操作码。此外，该指令识别一个或多个寄存器。通过使用所识别的寄存器来执行多项式算术运算，从而可对该指令加以处理。
实现可提供执行二进制多项式加法的指令，该指令可采用乘法器来实施。多项式算术运算的结果可存于一个或多个结果寄存器中。多项式算术运算可包括乘法，其中，使所标识的寄存器的内容相乘。运算还可以包括多项式的乘加运算，其中，所标识的寄存器的内容相乘然后加到一个或多个结果寄存器中。结果寄存器可包括高阶寄存器和低阶寄存器。可对存于寄存器中的多项式进行多项式算术运算。多项式可编码为系数的二进制表示。
以下附图和说明书中对一个或多个实现加以阐述。从说明书和附图以及权利要求中可明显看出本发明的其他特征和优点。
附图说明
图1是可用于RISC体系结构中的五级流水线示例的框图，
图2是包括执行核心和乘/除运算单元的处理器核心的框图。
图3A和3B是执行多项式乘法和加法的例示指令的指令编码。
详细说明
许多公共密钥密码系统采用扩展精度模运算来对数据加密和解密。例如，多数椭圆曲线(EC)密码系统大量采用二进制多项式乘法和加法来对数据加密和解密。椭圆曲线密码系统的性能可通过修改编程CPU乘法器以响应新定义的专用于多项式运算的指令来加以提高。
当(如IEEE1363-2000标准所推荐的那样)采用定义于GF(2163)上的椭圆曲线时，所需的主要运算是在GF(2163)域上的乘法运算。在2163个元素中每一个元素可表示为系数为0或1的至多163次幂的多项式。在此表示中，两个元素可以采用简单的按位异或相加，而两个多项式a(X)和b(X)可通过计算a(X)b(X)mod P(X)而得到相乘的结果，乘积a(X)b(X)是326次多项式，P(X)是IEEE1363-2000标准规定的既约多项式。
多项式乘法与模数乘法具有相同的形式，在整数范围内执行abmod p，不同之处在于：(1)常规的加法由异或替代；和(2)常规的32位乘法由32位不带进位的乘法替代。因此，可采用移位和异或而不是移位和加法运算来执行多项式模数乘法运算。
参考图1，可用来实现多项式乘法运算的示范性的微处理器结构包括五级流水线，其中，指令可在每个时钟周期发出并在固定的时间例如5个时钟周期内执行。每条指令的执行分成5步：取指(IF)级1001，读寄存器(RD)级1002，算术/逻辑单元(ALU)级1003，存储(MEM)级1004和写回(WB)级1005。在IF级1001中，从指令高速缓冲器中取出指定指令。所取指令的一部分用于指定可用于执行指令的源寄存器。在读寄存器(RD)级1002中，系统将指定源寄存器的内容取出。所取得的值可用在ALU级1003中执行算术或逻辑运算。在MEM级1004中，执行指令可读/写数据高速缓冲器中的存储器。最后，在WB级1005中，通过执行指令而获得的值可写回到某个寄存器中。
因为有些运算，例如浮点运算和整数乘/除运算未必能够在一个时钟周期内完成，某些指令仅仅开始指令的执行。在经过足够的时钟周期后，另一指令可用于取回结果。例如，当整数乘法指令花费5个时钟周期时，一条指令可启动乘法计算，而另一条指令可在乘法运算完成后将乘积装入寄存器中。如果在需要结果的时候乘法运算还未完成，流水线可停止直到结果可得。
参考图2，作为示例给出示范性的RISC体系结构。处理器核心2000(也称为“微处理器核心”)包括如下单元：执行单元2010、乘/除运算单元(MDU)2020、系统控制协处理器(CPO)2030、存储管理单元2040、高速缓存控制器2050和总线接口单元(BIU)2060。
执行单元2010是在处理器核心2000内执行指令的主要机构。执行单元2010包括寄存器阵列2011和算术逻辑单元(ALU)2012。在一种实现中，寄存器阵列2011包括32个可用于例如标量整数运算和地址计算的32位通用寄存器。可将包括两个读端口和一个写端口的寄存器阵列2011完全旁路，以使流水线中的运算延迟最小。ALU2012支持逻辑和算术运算，例如加法、减法和移位。
MDU 2020执行乘法和除法运算。在一种实现中，MDU 2020包括32位乘16位(32×16)Booth编码的(Booth-encoded)乘法器(未显示)、结果寄存器(HI寄存器2021和LO寄存器2022)、除法状态机以及执行这些功能的所需的所有多路复用器和控制逻辑。在一种流水线式实现中，每时钟周期可将32×16乘法运算发送给MDU2020，以便每个时钟周期32位的数可同16位的数相乘。但是直到乘法运算完成后HI/LO寄存器(2021和2022)中才有可用结果。可用MFHI和MFLO指令来访问结果。这些指令将结果从HI寄存器2021和LO寄存器2022中分别移至指定的寄存器。例如“MFHI $7”将HI寄存器2021的内容移至通用寄存器$7中。
乘-加(MADD/MADDU)和乘-减(MSUB/MSUBU)这两条指令可用于执行乘-加和乘-减运算。MADD指令使两个数相乘后再将乘积加到HI寄存器2021和LO寄存器2022的当前内容中。然后将结果存于HI/LO寄存器(2021和2022)中。类似地，MSUB指令使两个操作数相乘后再将乘积从HI寄存器2021和LO寄存器2022中减去，然后将结果存于HI/LO寄存器(2021和2022)中。MADD和MSUB指令对符号数执行运算。MADDU和MSUBU指令对无符号数执行类似运算。
参考图3A，提供了多项式乘法(MULTP)指令3010的示范性的指令编码。MULTP指令3010有两个寄存器字段，即rs 3011和rt3012，用于指定包含将要参与相乘的多项式的源寄存器。在乘运算完成之后，结果存在HI寄存器2021和LO寄存器2022中。MULTP指令3010还包括一个或多个用于识别将要执行的运算的操作码3013。在一些实现中，可以不用指令字段的一部分，例如字段3014。
在一种实现中，由rs 3011和rt 3012标识的寄存器包含二进制多项式(即模2化简的多项式系数)。因此，各系数或为“1”或为“0”。在32位寄存器中对多项式进行编码，其中每一位表示一个多项式系数。例如将多项式“x4+x+1”编码为“10011”，因为x3和x2的系数为“0”，其余系数为“1”。
MULTP指令3010允许将两个多项式相乘。例如，(x4+x+1)(x+1)＝x5+x4+x2+2x+1。模2化简多项式得到x5+x4+x2+1。如果多项式以上述二进制编码，那么同一乘法可表示为(10011)(11)＝110101。
指令和操作数的长度可任意改变；所描述的32位设计仅为一个例子。在32位的实现中，存于rs 3011中的32位字的值可以同存于rt 3012中的32位字的值进行多项式的乘法，即将两个操作数均作为二进制多项式值，以产生64位的结果。低阶32位字可放在LO寄存器2022中，高阶32位字结果可放在HI寄存器2021中。在某些实现中，不会发生运算异常。如果由rs 3011和rt 3012所指定的寄存器不包含32位带符号扩展的值，那么运算的结果可能无法预料。
参考图3B，提供了多项式乘加(MADDP)指令3020的示范性指令编码。MADDP指令3020有两个参数字段，即rs 3021和rt 3022，用于指定源寄存器，该源寄存器包含要执行乘法运算并采用多项式加法(异或)加到HI 2021和LO 2022的内容中的多项式。乘法和加法运算完成之后，其结果存在HI寄存器2021和LO寄存器2022中。MADDP指令3020还可包括一个或多个识别所要执行的运算的操作码3023。在一些实现中，可以不用指令段的一部分，例如字段3024。
MADDP指令3020执行如上讨论的乘法运算。二进制多项式加法类似于按位异或运算。例如，二进制多项式加(x4+x+1)+(x+1)的结果是x4+2x+2。模2化简系数得到x4，x4可表示为“10000”。
同样地，指令和操作数的长度可任意改变。在一种实现中，存于rs 3021的32位字的值可与存于rt 3022中的32位字的值作基于多项式的乘法运算，即把两个操作数均作为二进制多项式的值，从而得到64位结果。然后该结果可采用多项式加法加到HI寄存器2021和LO寄存器2022中的内容中。64位的结果包括低阶32位字和高阶32位字。低阶32位字可放在LO寄存器2022中，高阶32位字结果可放在HI寄存器2021中。如果由rs 3021和rt 3022指定的寄存器不包含32位带符号扩展的值，那么运算的结果可能无法预料。
多项式算术的实现除可采用硬件(如在微处理器或微控制器内)实现，还可用软件实现，所述软件设置在例如经配置用于存储软件(即计算机可读程序代码)的计算机可用(如可读的)媒体中。所述程序代码可使本说明书所公开的系统和技术的功能或构造或者二者均得以实现。例如，这可以通过使用通用编程语言(如C，C++)、硬件描述语言(HDL)(包括Verilog HDL、VHDL、AHDL(Altera HDL)等)、或者其它可用的编程和/或电路捕获工具来完成。程序代码可配置在任何已知的计算机可用媒体中，包括半导体、磁碟片、光盘(例如CD-ROM，DVD-ROM)，以及配置为实现于计算机可用(如可读)传输媒体(如载波和任何别的包括数字的、光学的或基于模拟的媒体)中的计算机数据信号。这样，代码可通过包括因特网和企业内部网的通信网络来传输。
应理解，上述系统和技术所完成的功能和/或所提供的结构可以用于程序代码来实现的核心(如微处理器核心)来表示，并且可转换成作为集成电路产品一部分的硬件。所述系统和技术还可体现为硬件和软件的组合。因此，其它实现方式也在以下权利要求范围之内。

Claims (56)

1.一种在指令集体系结构中用于执行多项式算术的指令，所述指令为所述指令集体系结构的一部分并包括：
一个或多个将所述指令识别为用于执行多项式算术运算的指令的操作码；和
一个或多个寄存器标识符；
其中，使用所述一个或多个寄存器标识符来执行所述多项式算术运算从而处理所述指令。
2.如权利要求1所述的指令，其特征在于，所述多项式算术运算为二进制多项式加法。
3.如权利要求2所述的指令，其特征在于，所述二进制多项式加法采用乘法器来执行。
4.如权利要求1所述的指令，其特征在于，所述多项式算术运算的结果存于一个或多个结果寄存器中。
5.如权利要求4所述的指令，其特征在于，所述多项式算术运算包括：
将由所述一个或多个寄存器标识符标识的所述寄存器中的内容相乘而得到一个中间值；以及
将所述一个或多个结果寄存器的内容与所述中间值相加而得到结果。
6.如权利要求5所述的指令，其特征在于，所述结果存于所述一个或多个结果寄存器中。
7.如权利要求1所述的指令，其特征在于，所述多项式算术运算的结果存于高阶结果寄存器和低阶结果寄存器中。
8.如权利要求1所述的指令，其特征在于，所述多项式算术运算为多项式乘法。
9.如权利要求8所述的指令，其特征在于，由所述一个或多个寄存器标识符识别的各寄存器包含有多项式。
10.如权利要求9所述的指令，其特征在于，将每个多项式编码为系数的二进制表示。
11.如权利要求1所述的指令，其特征在于，所述指令集包括RISC指令集。
12.一种使用指令来执行多项式算术的方法，所述方法包括：
接收指令，所述指令包括：
一个或多个将所述指令识别为用于执行多项式算术运算的指令的操作码；和
一个或多个寄存器标识符；和
通过处理所述指令利用所述一个或多个寄存器标识符来执行多项式算术运算。
13.如权利要求12所述的方法，其特征在于，执行所述多项式算术运算包括执行二进制多项式加法。
14.如权利要求13所述的方法，其特征在于，执行所述二进制多项式加法包括使用乘法器。
15.如权利要求12所述的方法，其特征在于还包括将所述多项式算术运算的结果存于一个或多个结果寄存器中。
16.如权利要求15所述的方法，其特征在于，执行所述多项式算术运算包括：
将由所述一个或多个寄存器标识符标识的所述寄存器中的内容相乘而得到一个中间值；和
将所述一个或多个结果寄存器的内容与所述中间值相加而得到结果。
17.如权利要求16所述的方法，其特征在于还包括将所述结果存于所述一个或多个结果寄存器中。
18.如权利要求12所述的方法，还包括将所述多项式算术运算的结果存于高阶结果寄存器和低阶结果寄存器中。
19.如权利要求12所述的方法，其特征在于，执行所述多项式算术运算包括执行多项式乘法。
20.如权利要求19所述的方法，其特征在于，由所述一个或多个寄存器标识符识别的媒体各寄存器包含多项式。
21.如权利要求20所述的方法，其特征在于，将每个多项式编码为系数的二进制表示。
22.如权利要求12所述的方法，其特征在于，所述指令为指令集的一部分，并且所述指令集包括RISC指令集。
23.一种包括用软件实现的微处理器核心的计算机可读媒体，所述微处理器核心包括用于执行多项式算术的指令，所述指令包括：
将所述指令识别为一个或多个用于执行多项式算术运算的指令的操作码；和
一个或多个寄存器标识符；
其中，通过使用一个或多个寄存器标识符来执行所述多项式算术运算从而处理所述指令。
24.如权利要求23所述的计算机可读媒体，其特征在于，所述多项式算术运算为二进制多项式加法。
25.如权利要求24所述的计算机可读媒体，其特征在于，所述二进制多项式加法采用乘法器来执行。
26.如权利要求23所述的计算机可读媒体，其特征在于，所述多项式算术运算的结果存于一个或多个结果寄存器中。
27.如权利要求26所述的计算机可读媒体，其特征在于，所述多项式算术运算包括：
将由所述一个或多个寄存器标识符标识的所述寄存器中的内容相乘而得到一个中间值；和
将所述一个或多个结果寄存器的所述内容与所述中间值相加而得到结果。
28.如权利要求27所述的计算机可读媒体，其特征在于，所述结果存于所述一个或多个结果寄存器中。
29.如权利要求23所述的计算机可读媒体，其特征在于，所述多项式算术运算的结果存于高阶结果寄存器和低阶结果寄存器中。
30.如权利要求23所述的计算机可读媒体，其特征在于，所述多项式算术运算是多项式乘法。
31.如权利要求30所述的计算机可读媒体，其特征在于，由所述一个或多个寄存器标识符识别的各寄存器包含多项式。
32.如权利要求31所述的计算机可读媒体，其特征在于，将每个多项式编码为系数的二进制表示。
33.如权利要求23所述的计算机可读媒体，其特征在于，所述指令是指令集的一部分，并且所述指令集包括RISC指令集。
34.一种在公共密钥密码系统中用公共密钥对信息加密的方法，所述方法包括用于执行多项式算术的指令，所述指令包括：
一个或多个将所述指令识别为用于执行多项式算术运算的指令的操作码；和
一个或多个寄存器标识符；
其中，通过使用所述一个或多个寄存器标识符来执行所述多项式算术运算从而处理所述指令。
35.如权利要求34所述的方法，其特征在于，所述多项式算术运算是二进制多项式加法。
36.如权利要求35所述的方法，其特征在于，所述二进制多项式加法使用乘法器来执行。
37.如权利要求34所述的方法，其特征在于，所述多项式算术运算的结果存于一个或多个结果寄存器中。
38.如权利要求37所述的方法，其特征在于，所述多项式算术运算包括：
将由所述一个或多个寄存器标识符标识的所述寄存器中的内容相乘而得到一个中间值；和
将所述一个或多个结果寄存器的内容与所述中间值相加而得到结果。
39.如权利要求38所述的方法，其特征在于，所述结果存于所述一个或多个结果寄存器中。
40.如权利要求34所述的方法，其特征在于，所述多项式算术运算的结果存于高阶结果寄存器和低阶结果寄存器中。
41.如权利要求34所述的方法，其特征在于，所述多项式算术运算是多项式乘法。
42.如权利要求41所述的方法，其特征在于，由所述一个或多个寄存器标识符标识的媒体各寄存器包含多项式。
43.如权利要求42所述的方法，其特征在于，将每个多项式编码为系数的二进制表示。
44.如权利要求34所述的方法，其特征在于，所述指令是指令集的一部分，并且所述指令集包括RISC指令集。
45.一种在微处理器中用于执行多项式算术的指令，所述指令包括：
一个或多个将所述指令识别为用于执行多项式算术运算的指令的操作码；和
一个或多个寄存器标识符；
其中，通过使用所述一个或多个寄存器标识符来执行所述多项式算术运算从而处理所述指令。
46.如权利要求45所述的指令，其特征在于，所述多项式算术运算是二进制多项式加法。
47.如权利要求46所述的指令，其特征在于，所述二进制多项式加法采用乘法器来执行。
48.如权利要求45所述的指令，其特征在于，所述多项式算术运算包括：
将由所述一个或多个寄存器标识符标识的所述寄存器中的内容相乘而得到一个中间值；和
将所述一个或多个结果寄存器的内容与所述中间值相加而得到结果。
49.如权利要求45所述的指令，其特征在于，所述多项式算术运算是多项式乘法。
50.一种提供了一条或多条用于执行多项式算术的指令的微处理器，所述微处理器包括：
指令存储器；
执行单元，所述执行单元从所述指令存储器中取微处理器指令并处理所取指令；和
多项式算术单元，如果所取指令是所述一条或多条用于执行多项式算术的指令之一，则所述多项式算术单元在处理所取指令中由所述执行单元使用。
51.如权利要求50所述的微处理器，其特征在于，所述微处理器还包括乘/除单元。
52.如权利要求51所述的微处理器，其特征在于，所述多项式算术单元是所述乘/除单元的部件。
53.如权利要求50所述的微处理器，其特征在于，所述多项式算术单元可用于执行二进制多项式加法。
54.如权利要求50所述的微处理器，其特征在于，所述多项式算术单元可用于执行二进制多项式乘法。
55.如权利要求50所述的微处理器，其特征在于，所述微处理器还包括用于存储来自所述多项式算术单元的结果的结果寄存器。
56.如权利要求55所述的微处理器，其特征在于，通过执行二进制多项式乘法运算以确定中间结果并将所述中间结果加到所述结果寄存器中，所述多项式算术单元可用于执行二进制多项式乘-加操作。
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