CN1513208A - 具铅直mos晶体管之dram胞元排列及其制造方法 - Google Patents

具铅直mos晶体管之dram胞元排列及其制造方法 Download PDF

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CN1513208A
CN1513208A CNA028109082A CN02810908A CN1513208A CN 1513208 A CN1513208 A CN 1513208A CN A028109082 A CNA028109082 A CN A028109082A CN 02810908 A CN02810908 A CN 02810908A CN 1513208 A CN1513208 A CN 1513208A
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B·李
T·施莱塞
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Abstract

沿着内存胞元矩阵的某一行(column)所排列的信道区域(6)乃是一被闸极介电层(9)所围绕的肋条(7)之一部分。属于某列(row)的MOS晶体管之闸电极(11，12)则是一类似条状之字符线(10)的一部份，以致于在该内存胞元矩阵的每个交叉点都各具有一伴随着联合字符线(10)之闸电极(11，12)的铅直双闸极MOS晶体管，其中该联合字符线(10)系位于联合肋条(7)两侧上的沟渠(5)之中。

Description

具铅直MOS晶体管之DRAM胞元排列及其制造方法
本案系为一与具有铅直MOS晶体管之DRAM胞元排列及其制造方法有关的发明，其中该晶体管并不具有任何浮体(floating bodies)但却为完全空乏者。
当前，在一DRAM胞元排列中所使用的内存胞元，例如一动态的半导体内存，几乎都是单一晶体管的内存胞元，其系已为众所皆知之装置并且具有一MOS选择晶体管以及一电容器。在内存胞元内的信息乃是以电荷的形式储存于该电容器之中。该电容器以在该晶体管透过一字符线而被驱动之时该电容器的电荷便可透过一位线而被读出的方式来与该晶体管相连接。
一般而言，制作出一具有高封包密度的DRAM胞元排列乃是努力的方向之一。就此观点来看，把MOS晶体管设计成铅直晶体管将是有利的，其中在该铅直晶体管之中的源极、信道区域以及汲极乃彼此相叠。一此类型的MOS晶体管仅占有与频道长度无关的小空间。再者，把每个内存胞元的铅直晶体管及其相联合在一起的电容器以彼此相互铅直地排列在一半导体基板上则是另一努力方向。
一包含大量此类型内存胞元的排列已为人所知，例如，可由专利案DE 4,430,483 A1之中获知。每个内存胞元具有一类似柱状且铅直排列地选择晶体管与一电流频道，其中该选择晶体管在一半导体基板柱之中乃包含一汲极区域与一源极区域，而该电流频道则是在铅直方向上进行传播，并在该汲极与该源极之间运作，此外，该电流频道更是受到一环绕于该基板柱且与该基板柱之间仅以一层氧化物相隔的一控制闸极所控制。举例来说，包含有掺杂多晶硅以及各式内存胞元的控制闸极系为相互电连结，并形成了用以驱动该选择晶体管的字符线。
一此类已为人所熟知的MOS晶体管的特殊问题系为，举例来说，该类似柱状的信道区域，其系与该基板以及其内的电荷载体收集器相绝缘，乃可改变门槛电压值。此活性区域的完全绝缘亦会出现于其它基板上，例如绝缘层上硅晶(Silicon-on-Insulator，SOI)基板，其有一些优点但是同时亦导致了一些缺点，已知的缺点为浮体效应(floating body effects)。此等效应系因在该活性区域内生成的电荷载体无法流出而造成。此特别适用于就MOS晶体管的信道区域中所生成之电荷载体而言。
另一方面，在已为人熟知的MOS晶体管中，尽管该环绕于信道区域的该闸极并无法保证空乏区(depletion region)自该类似柱状之信道区域的周围就是以全方位的方式延伸至其中央，亦即并无法确定该MOS晶体管在被一完全充满该信道区域的空乏区之中是否真的处于完全空乏(fully depleted)的型态。
鉴于考量此类完全空乏之MOS晶体管的优点，各方对于其之需求乃是与日遽增，而此类完全空乏之MOS晶体管似乎仅在该P型掺杂信道区域(p-doped channel region)受到某些方法所限制的情况下方得以实现，其系与其它平面标准MOS晶体管的状况不同(在其它平面标准晶体管之中，该p型掺杂信道区域并无法自基板分离)。举例来说，对于已为人所熟知的晶体管之类似柱状的信道区域或是在一SOI基板上的平面MOS晶体管而言，上述情形便可能出现。然而，事实上，在这些情况之中，因为绝缘的缘故，信道区域与基板之间的连结并存在，另一方面，如上所述，已发现其实际上反而会导致一伴随有浮体的情况发生。
专利案DE 19,929,211 A1已揭露一DRAM胞元排列以及一制造方法，其中，MOS晶体管系被设计成铅直的晶体管，而并已避免其中发生浮体效应。在该文件中所述及的晶体管在具有新贴近之闸极的基板中形成一丘状的突起，而在该突起的另一侧，该信道区域系透过一传导结构而被电连结至该闸极，因此，在该信道区域内生成的电荷载体即可流走。然而，在此已为人熟知的胞元排列的整个结果系为一杂乱交织的结构，其系与制造方式同样地复杂。
本发明系以提供一DRAM胞元排列及其制造方法之目的为基础，本发明提供了处于完全空乏之型态(fully depleted type)下却尽可能地不具有浮体的晶体管，且在此同时，本发明亦确保所使用的方法系为一简单的制造过程。
根据本发明，上述目的系透过一具有权利要求第1项所列特征之DRAM胞元排列而达成。
本发明提供一具有铅直MOS晶体管的DRAM胞元排列，
-系包含一内存胞元的排列矩阵，其中每个内存胞元各具有一MOS晶体管以及一电容器，其中该MOS晶体管具有以层状由上至下相互堆栈的一上部源极/汲极区域、一信道区域以及一下部源极/汲极区域，而该电容器系与该MOS晶体管相连结，
-其中该内存胞元矩阵之MOS晶体管的信道区域系被排列于行(column)以及列(row)之中，且沿着某一行(column)所排列的信道区域系为在一基板中水平运行之肋条的一部份，
-其中每个肋条的两侧系分别被一闸极介电层(gatedielectriclayer)所围绕并且位在该上部源极/汲极之上，
-其中沿着该内存矩阵之某一列(row)排列的MOS晶体管之闸电极系为一类似条状之字符线的一部份，该字符线系与位在该肋条之上的该列(row)相平行之形式而运作，并自上方开始占用沟渠，其中该沟渠系被形成于沿着该行(column)方向的肋条之间，进以填补这些沟渠直到其超出该字符线之宽度；
-以致于内存胞元矩阵的每个交叉点都有一具有联合字符线之闸电极的铅直双闸极MOS晶体管，其中该联合字符线系位于相联合之肋条的两侧上之沟渠内。
首先，本发明的基本概念包含该铅直晶体管所具有之以信道区域的宽度与掺杂为基础的横向双闸极将很容易地使晶体管以空乏的形式而生成，其次则是，晶体管可透过与其相连结的肋条而与基板边缘的信道区域相接触，进以使得电荷载体可流走。
一较佳的实施例提供了一DRAM胞元排列，
-其中每个内存胞元各具有一电容器，其堆栈于该MOS晶体管之下且电连结于下部源极/汲极区域，
-而且有一金属位线在沿着某一行(column)并与其平行而排列的MOS晶体管之上运作，其中该金属位线系设于该等字符线之上并且与联合的MOS晶体管之上部源极/汲极区域相电连结，
一行(column)之上部源极/汲极区域可能利于成形类似条状(strip-like)的连续区域，而且亦可能连带地被连结至相对应的金属位线。
本发明进一步地提供了一制作如权利要求第1项所述之DRAM胞元排列的方法，其包含以下步骤：
-a)布植掺杂离子以便在一基板上生成一上部源极/汲极区域数组；
-b)以由微影制程所产生的光罩图案来蚀刻沟渠进以产生相连结而形成肋条的信道区域；
-c)在沟渠内产生一覆盖层并在肋条的表面产生一闸极介电层；
-d)沉淀并图案化该类似条状的字符线，而闸电极即被生成于各个MOS晶体管的两侧；
-e)在基板的前侧面(front surface)沉淀一具有晶圆接合能力的第一辅助层，之后再施用一第一辅助载体基板至该第一辅助层，接着再将该基板移除；
-f)布植掺杂离子以便在该信道区域上生成一下部源极/汲极区域数组；
-g)藉由浅沟渠绝缘(shallow trench isolation，STI)技术来产生浅绝缘沟渠(shallow isolation trenches)。
藉由下列的附加步骤，本发明特别开启了一从头到尾都非常简便的DRAM制作方法，该等附加步骤系包含：
-h)产生接触结构与电容器，其等乃堆栈在该第一辅助载体基板的前侧面之上，并且与联合的MOS晶体管的下部源极/汲极区域相连结
-i)在该第一辅助载体基板的前侧面沉淀一具有晶圆接合能力的第二辅助层，之后再施用一第二辅助载体基板至该第二辅助层，接着再移除该第一辅助载体基板与该第一辅助层；
-j)在该第二辅助载体基板的前侧面上形成一结构金属位线以直接与该上部源极/汲极区域电接触。
本发明之DRAM胞元排列及其制作方法的较佳实施例系伴随有附图而被描述于后，其中：
图1a、2a、3及4系呈现了图1b之截线A-A的截面图标，进以说明了本发明的DRAM胞元排列制作方法所包含的成功处理步骤；
图1b与2c系分别呈现了根据图1a与2c中所示的本发明处理步骤而制成的DRAM胞元排列之平面图；
图2b则呈现了图2c中之截线B-B的截面图标。
本发明的DRAM胞元排列制作方法中所包含的个别处理步骤系伴随有图1至图4而被描述于后。
举例来说，图1b呈现了一四内存胞元的排列(数组)，其中，当类似条状且定义了该矩阵的行(column)之上部源极/汲极区域4在每个个案之中皆在排列于某一行中的晶体管之上运作时，呈现于图1b之平面图中的类似条状字符线10(闸极)系定义了该矩阵的列(row)并且与在一列之中彼此相连而排列的晶体管相接触。
图1a呈现了一通过图1b中之截线A-A上的胞元排列之截面。如同将在后续内容中被更详细解释的部分，由一SOI基板来作为启使的制作技术乃是有利的，换言之即是由具有一p型硅层(p-siliconlayer)3以及一埋藏式氧化物层(buried oxide layer)2的基板1开始进行制作，其中该p型硅层3系被图案化(patterned)至该基板之上，而该埋藏式氧化物层2系位于p型硅层3该与该基板1之间。
由图1a可知，一开始的布植步骤乃在于在SOI晶圆上，即在该p型硅层3之上，产生一上部n型掺杂(n-doped)源极/汲极区域。就此处理程序的观点来看，其它的布植步骤(源井、接口设备等等之数组)以及针对于接口设备而藉由使用STI技术所产生的沟渠绝缘都将因而更容易地被执行。
接着则是以经过微影蚀刻所产生之光罩图案来干蚀刻沿着行(column)方向所运行的沟渠5，进以留下被沟渠5所界定的连续性之p型硅肋条7(请参考第图2b)。彼此相连的晶体管之信道区域6因而导致了该列方向(请参考图1a)。
举例来说，在下一步骤中，氮化硅系经由化学机械研磨(chemicalmechanical polishing，CMP)过程而被沉淀，接着亦被回蚀，以致于其次作为覆盖层8的氮化物层被生成于沟渠5之中。接着，闸极氧化物9即被生成于肋条7的两侧以及上部，如果适当的话，此程序可分别针对在该胞元数组或是接口设备中的晶体管而实施。该闸极氧化物9特别可藉一热生长氧化物层(thermally grown oxide layer)的帮助而生成。
下一处理步骤则包含类似条状之字符线10的堆积、微影蚀刻图案化以及蚀刻。导电物质，例如掺杂的多晶硅、钨、氮化硅(siliconnitride，SiN)，或是一具有中间氮化钨层的层状系统将充填该沟渠5，以致于闸电极11与12即被生成。蚀刻字元线10之后，其它的SiN堆及以及蚀刻步骤可被执行，特别是在微细垫片(spacers)的制作之中。再者，举例而言，其它的源极/汲极区域可被布植于接口设备之中，以利于在芯片上产生逻辑电路。最后，一具有晶圆接合能力的第一辅助层13即被堆积，而且，若是有需要，该第一辅助层13系为平面式的堆积而呈现出了图1a所示之生成状态，其中典型的第一辅助层13系为一氧化物层或者也可能是一硼磷硅酸盐玻璃(Borophospho-silicate Glass，BPSG)层。
在进一步的步骤中，系为一晶圆接合步骤，一第一辅助载体基板14即被施用或是黏合至该平面状的辅助(氧化物)层13。此可藉由加热相反的表面并接着予以结合而实现。在接合面已被结合并冷却之后，一无法松脱的化学接合便在预定的时间之后生成于该辅助(氧化物)层13与该第一辅助载体基板14之间。
对于其它处理步骤而言，此刚开始形成的结构之制作系发生在相反的两侧。因此，整个结构即被”翻转(turned over)”，而且位于顶部并伴随着利于作为蚀刻物的埋藏式氧化物层2的基板1即经湿式蚀刻而被蚀去。然后，该埋藏式氧化物层2系便随着覆盖层8一起透过一化学机械平面化作用CMP或是藉其它蚀刻步骤而被移除，其中该覆盖层8一般为氮化硅层，并已预先被生成以便用来在闸极氧化物9之前终止这些过程。
请参考图2a，掺杂离子被布植入尚未被覆盖的表面，亦即前述的背面，以便在信道区域6之上产生一下部源极/汲极区域的数组15。接着，请参考第2b与c图，浅隔离沟渠16即透过一般的方式(微影蚀刻，蚀刻，氧化物沉淀或是CMP)来使用STI技术而以条状的形式产生，其原因在于该下部源极/汲极区域并不像该上部源极/汲极区域必须是绝缘地。
此导致了如图2所示的结果。假使结合图2a与图2b结合在一起看，那么本发明的基本概念即可以一最简单地方式来描述，其中该图2a与图2b各呈现了一图2c中所示之平面图中的两条线的其一截面，而该等被呈现之截面系为彼此相互垂直的两截面。
图2a清楚的呈现了铅直MOS晶体管，其各包含一上部源极/汲极区域4、一下部源极/汲极区域15以及一信道区域6，其中该信道区域6系与该上部源极/汲极区域4以及该下部源极/汲极区域15相垂直而运行，如同该闸极氧化物9一般。藉由类似条状之字符线10所相互连结的闸电极11与12便生成于各个沟渠5至边缘的区域之中，也就是说，生成于信道区域6的左边与右边。
因此，这些即为根据本发明所得到之具有横向双闸极的铅直晶体管，因此，头一回，根据该信道区域6的宽度与掺杂，产生真正完全空乏的晶体管成为一件可能的事情。这些晶体管系以一方式而沿着列(row)的方向而彼此相黏合，该方式系为每个位在横向上的晶体管都具有两个闸电极11与12，而每个位在沟渠5之中的闸电极则可被认为是属于两个相邻的晶体管。
其次，该铅直晶体管系以一方式而沿着行(column)的方向相互堆栈，请参考图2b，其中该信道区域6即被生成为连续性的肋条7。该晶体管，或是更严格的说该是每一行(column)之晶体管的信道区域6，将不会形成彼此绝缘的个别硅行(silicon column)，但是却可能形成一类似墙状的结构，那就是肋条7。这些结构可在考量其之尺寸的情况下应用其所具有的类似基板状之特性，或是至少可以开启在基板边缘形成接触的可能性。浮体效应可被认为是降低了或是可认为是透过信道区域6而被完全消除，其中该信道区域6系被环绕，因为接触皆在基板的边缘形成。
建议利用内存胞元来制作胞元排列，其中每个排列各包含一铅直晶体管、一排列于该铅直晶体管下方的电容器，以及一设置于该铅直晶体管上方的金属位线。此将实质地需要下列的附加步骤：
首先，先在第一辅助载体基板14的前侧面(front surface)生成接触结构17，并且该接触结构之上生成堆状的电容器。在各种情况下的接触装置17皆被用来连接每个晶体管的下部源极/汲极区域15与该电容器的第一电极18，其中该电容器系堆栈于该晶体管之下。介电质19，例如五氧化钽(tantalum pentoxide)，在各个个案之中都是用来区隔该第一电极18与该电容器的相反电极，其中该电容器在各个个案之中都被设计并且连结成为一共享的电容器板20。就一堆栈状的电容器而言，所有的传统实施例(盒状、柱状等等)都可适用，而且也同样适用于各种物质、金属电极以及介电质，特别是具有较高介电常数的介电质。因此，整个电容器便具有一简单、低阻抗的连结，并且可能得以不受限于金属化作用所造成的比例，如同可能伴随着沟渠电容器而发生。
在该堆栈状的电容器已被生成之后，一第二辅助(氧化物)层24便接着被沉淀于该电容器之上，而且一第二辅助载体基板22亦在一晶圆接合步骤之中被施用或是黏合。然后，正个结构便再次被翻转，因此其现在便可藉由使用传统的步骤方法而于辅助载体基板22的前侧面(front surface)之上生成金属位线23以及接触(未图标)。
如图4所示，并且是在”翻转”操作已被执行两次之后，的本发明DRAM胞元排列此刻便具有所想要的排列(基板，在其上的埋藏式电容器，然后则是该铅直晶体管以及位在顶端的金属位线)，其提供了一很大规模的整合，其系考量了铅直排列地选择晶体管以及堆栈于其下方的电容器。一内存胞元的尺寸约为4F2，系伴随有尺寸F不及0.2um(F＜0.2um)的最小微影蚀刻特征(lithographic feature)。
用来制作本发明之DRAM胞元排列的制作方法是非常简单，特别是在微影蚀刻方面，另外此制作方法同时也特别包含了一非常简单的金属化作用的操作过程。
特别地，因为此制作方法在处理程序当中使用了多重晶圆接合，故其得以结合了沟渠技术的基本优点(简单的金属化作用，铅直晶体管的整合容易度，其原因在于电容与金属化作用系沿着不同方向而延伸，如本装置中所示者)与堆栈技术的基本优点(制程中的装置、电容器以及金属化作用将具有较低的热预算(thermal budget))。

Claims (6)

1.一种具有铅直MOS晶体管的DRAM胞元排列，
-系包含一内存胞元的排列矩阵，其中每个内存胞元各具有一MOS晶体管以及一与该MOS晶体管相连结的电容器(18，19，20)，其中该MOS晶体管各具有以层状而由上至下相互堆栈的一上部源极/汲极区域(4)、一信道区域(6)以及一下部源极/汲极区域(15)，
-其中该内存胞元矩阵之MOS晶体管的信道区域(6)系被排列于列(row)以及行(column)之中，且沿着其中一行(column)所排列的信道区域(6)系为在一基板(1)中水平运作之肋条(7)的一部份，
-其中每个肋条(7)的两侧系分别被一闸极介电层(9)所围绕并且是位在该上部源极/汲极(4)之上，
-其中沿着该内存矩阵之某一列(row)所排列的MOS晶体管之闸电极(11，12)系为一类似条状之字符线(10)的一部份，该字符线(10)系与位在该肋条(7)之上的该列(row)相平行而运作，并自上方开始充填沿着行(column)方向的肋条(7)之间而产生的沟渠(5)，直到其超出该字符线(10)之宽度，
-以致于在内存胞元矩阵的每个交叉点都有一具有联合字符线(10)的闸电极(11，12)的铅直双闸极MOS晶体管，其中该联合字符线(10)系位于联合肋条(7)的两侧上之沟渠(5)之中。
2.如权利要求第1项所述的DRAM胞元排列，
-其中每个内存胞元各具有一电容器(18，19，20)，其堆栈于该MOS晶体管之下并且电连结于下部源极/汲极区域(15)，
-而且其中还有一金属位线(23)在沿着某一行(column)并与其平行而排列的MOS晶体管之上运作，其中该金属位线系设于该字符线(10)之上并且与联合MOS晶体管之上部源极/汲极区域(4)电连结。
3.如权利要求第2项所述的DRAM胞元排列，其中一排列于该电容器(18，19，20)下方的辅助载体基板(22)乃伴随着一辅助层(21)而被提供，其中该辅助层(21)系具有晶圆接合能力而嵌于该两组件之间。
4.一制作如权利要求第1项所述之DRAM胞元排列的方法，其包含以下步骤：
-a)布植掺杂离子以便在一基板(1)上生成一上部源极/汲极区域数组(2)；
-b)以由微影制程所产生的光罩图案来蚀刻沟渠(5)进而产生相连结以形成肋条(7)的信道区域(6)；
-c)在沟渠(5)内产生一覆盖层(8)并在肋条(7)的表面产生一闸极介电层(9)；
-d)沉淀并图案化类似条状的字符线(10)，而闸电极(11，12)即被生成于每个MOS晶体管的两侧；
-e)在基板(1)的前侧面(front surface)沉淀一具有晶圆接合能力的第一辅助层(13)，然后再施用一第一辅助载体基板(14)至该第一辅助层(13)并接着移除该基板(1)；
-f)布植掺杂离子以便在该信道区域(6)上生成一下部源极/汲极区域数组(15)；
-g)藉由STI技术来产生浅绝缘沟渠(16)。
5.如权利要求第4项所述之方法，系包含下述之附加步骤：
-h)产生接触结构(17)与电容器(18，19，20)，其系堆栈在该第一辅助载体基板(14)的前侧面之上并且与联合MOS晶体管的下部源极/汲极区域(15)相连结，
-i)在该第一辅助载体基板(14)的前侧面沉淀一具有晶圆接合能力的第二辅助层(21)，然后再施用一第二辅助载体基板(22)至该第二辅助层(21)，并接着移除该第一辅助载体基板(14)与该第一辅助层(13)；
-j)在该第二辅助载体基板(22)的前侧面上形成一结构金属位线(23)以便与该上部源极/汲极区域(4)产生直接的电接触。
6.如权利要求第4或5项所述之方法，其中
-在处理步骤a)中，系有一SOI基板(1，2，3)被使用，
而在处理步骤e)的结尾，则是硅基板(1)先被回蚀或是移除，接着便是该SOI基板(1，2，3)的埋藏式氧化物层(2)被移除。
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