CN1532924A - 晶片级封装、多封装叠层、及其制造方法 - Google Patents

晶片级封装、多封装叠层、及其制造方法 Download PDF

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CN1532924A
CN1532924A CNA2003101188522A CN200310118852A CN1532924A CN 1532924 A CN1532924 A CN 1532924A CN A2003101188522 A CNA2003101188522 A CN A2003101188522A CN 200310118852 A CN200310118852 A CN 200310118852A CN 1532924 A CN1532924 A CN 1532924A
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pcb
hole
semiconductor
circuit board
printed circuit
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CN1320644C (zh
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金亨燮
郑泰敬
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L2924/1433—Application-specific integrated circuit [ASIC]

Abstract

一种半导体芯片封装，包括：半导体芯片，该芯片具有从有源第一表面到无源第二表面的贯穿其中的通孔。第一导电焊盘在所述半导体芯片的有源第一表面上至少部分地围绕所述通孔。该封装还包括印刷电路板，其具有一个连接到所述半导体芯片的无源第二表面上的第一表面以及与所述半导体芯片的通孔对齐的第二导电焊盘。导电材料充满所述通孔，并接触所述第一和第二导电焊盘。

Description

晶片级封装、多封装叠层、及其制造方法
技术领域
本发明总的来说涉及半导体芯片(semiconductor chips)的封装。更具体地说，本发明涉及一种晶片级封装(wafer level packages)、晶片级封装的多封装叠层(multi-package stacks)、以及制造晶片级封装和多封装叠层的方法。
背景技术
电子器件的微型化导致用于将半导体集成电路(IC)芯片包含在越来越小的封装中的技术的发展。电子设备工程联合委员会(JEDEC)已提出用名称“芯片尺寸封装(CSP)”来表示一种几乎与半导体芯片本身一样小的半导体芯片封装。具体地说，JEDEC将CSP定义为一种外形为包含在该封装中的半导体芯片外形的1.2倍或更小的封装。CSP技术适于封装用在电子产品，如数字摄像放像机(digital camcorders)、笔记本式计算机、存储卡，中的IC。具体地说，CSP技术的主要应用包括数字信号处理器(DSP)、微处理器、专用集成电路(ASIC)、动态随机存取存储器(DRAM)、以及快闪存储器(flash memories)。
然而，CSP技术的一个缺点是这种封装的制造相对较昂贵，特别是与更为传统的和常用的塑料封装，如球栅阵列(BGA)封装和薄小外形封装(TSOP)，相比尤其如此。
在努力降低成本的过程中，已经推出了晶片级封装(WLP)技术。晶片级封装形成为晶片级(于是降低了成本)，然后被切成单个器件。该封装本身的特征在于外部端子，如金属焊料凸起或焊球，在该封装底面上分布成二维阵列。这减小了半导体芯片至封装I/O位置(location)的信号通路，借此提高了该器件的运算速度。此外，与其他的具有从该封装的侧面延伸的周边引线的芯片包装不同，WLP占有印刷电路板(PCB)表面的面积粗略地说不多于该芯片本身的尺寸。
图1是表示传统WLP 20的一部分的平面图，图2是沿图1的I-I’线剖开的横截面视图。在半导体基板(semiconductor substrate)12上，半导体集成电路芯片14包括多个芯片焊盘(chip pad)11和一层钝化层13。钝化层13由二氧化硅、氮化硅或其组合层。芯片焊盘11由铝形成。聚酰亚胺第一介电层22形成于半导体芯片14上。多个金属迹线图案(metal trace pattern)21形成于第一介电层22之上。每个金属迹线图案21与相应的一个芯片焊盘11相接触。在金属迹线图案21和第一介电层22上形成第二介电层24。金属迹线图案21、第一介电层22和第二介电层24构成了重选路径层(rerouting layer)21’。多个焊球28置于金属迹线图案21的另一端。随后，制得的结构经受回流处理(reflow process)，以便将焊球28连接到金属迹线图案21上。
然而，不幸地，焊球接点往往不可靠。其主要原因在于由WLP20和外部印刷电路板(PCB)的热膨胀系数(CTE)不同而产生的应力。也就是说，一般，WLP安装在PCB上，从而WLP的焊球连接于WLP和PCB之间。当工作期间电力耗散时，半导体芯片14变热，并且接着在不工作时冷却下来。连接在焊球相对侧的WLP和PCB之间膨胀率的不同在焊球内产生了机械应力，有时导致裂缝或其它缺陷。
同时，近来的建议方案包括叠置多个晶片级封装以便形成一个用于安装在单个印刷电路板上的多封装叠层。
例如，美国专利号6,429,096即指向一种传统的形成如图3所示的多封装叠层10的方法。在晶片级，孔穿过半导体晶片而形成，并且这些孔用导电塞(conductive plug)2充满。然后，将半导体晶片切成小块并分成多个封装1。至少两个封装1通过使用连接在相邻封装的塞2之间的凸起(bump)3而被叠置，借此形成多封装叠层10。通过利用在最底层封装1a上的凸起3a，多封装叠层10被安装在外部PCB4的放置盘(landing pad)5上。
然而，最底层封装1a和外部印刷电路板(PCB)的热膨胀系数(CTE)又有差异。结果，由焊球3a形成的接点也不可靠并易于损坏。
发明内容
根据本发明的一个方面，提供一种包括一个半导体芯片的半导体芯片封装，该半导体芯片具有从有源(active)第一表面到无源(inactive)第二表面的贯穿其中的通孔。第一导电焊盘在所述半导体芯片的有源第一表面上至少部分地围绕所述通孔。该封装还包括一个印刷电路板，其具有连接到所述半导体芯片无源第二表面上的第一表面，以及与所述半导体芯片的通孔对齐的第二导电焊盘。导电材料充满所述通孔，并接触第一和第二导电焊盘。
根据本发明的另一个方面，提供一种半导体多封装叠层，其包括多个叠置的半导体芯片封装。每个芯片封装包括一个半导体芯片，该芯片具有从有源第一表面到无源第二表面的贯穿其中的通孔。第一导电焊盘在每个半导体芯片的有源第一表面上至少部分地围绕所述通孔。每个封装还包括一个印刷电路板，该印刷电路板具有连接到所述半导体芯片无源第二表面上的第一表面以及与所述半导体芯片的通孔对齐的第二导电焊盘。导电材料充满了每个半导体芯片的通孔，并接触第一和第二导电焊盘。
根据本发明的又一个方面，提供一种制造半导体芯片封装的方法，该方法包括形成穿过一个半导体芯片的通孔，从而所述通孔从该半导体芯片的有源第一表面延伸至所述半导体芯片的相对的无源第二表面，并且在所述半导体芯片的第一表面上，第一导电焊盘至少部分地围绕所述通孔。然后将一个印刷电路板的第一表面连接到所述芯片的第二表面，从而所述印刷电路板的第二导电焊盘与所述半导体芯片的通孔对齐。然后，用导电材料填满所述通孔，从而所述导电材料接触所述第一和第二导电焊盘。
根据本发明再一个方面，提供一种制造半导体芯片封装的方法，该方法包括形成多个穿过包含在一个晶片中的相应多个半导体芯片的通孔。所述通孔从所述晶片的有源第一表面延伸至该晶片的相对的无源第二表面，并且在所述晶片的第一表面上，第一导电焊盘至少部分地围绕每个通孔。在印刷电路板的第一表面上形成多个第二导电焊盘，并将印刷电路板的第一表面连接到所述晶片的第二表面上，从而所述多个第二导电焊盘分别与所述晶片的多个通孔对齐。然后，用导电材料填满所述多个通孔，从而所述导电材料接触每个通孔的所述第一和第二导电焊盘。
附图说明
通过以下参照附图的详细描述，本发明的各个方面和特征将变得显然，其中：
图1是表示传统晶片级封装的一部分的平面图；
图2是沿图1的I-I’线剖开的示意性横截面视图；
图3是传统的多封装叠层的示意性横截面视图；
图4是根据本发明的一个实施例的晶片级封装的示意性横截面视图；
图5至16是用来解释形成图4的晶片级封装的连续工序的图；
图17是表示根据本发明的一个实施例的多封装叠层的示意性横截面视图；
图18是表示根据本发明的另一个实施例的晶片级封装的示意性横截面视图；
图19至21是用来解释形成图18的晶片级封装的连续工序的图；
图22是表示根据本发明的另一个实施例的多封装叠层的示意性横截面视图；
图23至26是表示根据本发明的另一个实施例的晶片级封装和多封装叠层的示意性横截面视图；
图27至30是表示根据本发明的另一个实施例的晶片级封装和多封装叠层的示意性横截面视图；以及
图31是表示根据本发明另一个实施例的多封装叠层的示意性横截面视图；
具体实施方式
下面将通过几个非限制性的优选实施例来详细描述本发明。
图4是根据本发明的一个实施例的晶片级封装(WLP)80的横截面视图。WLP80包括一个通常由一个半导体基板32形成的半导体芯片34，在半导体基板32的有源上表面上有一层钝化层33。钝化层33的例子包括二氧化硅、氮化硅以及它们的组合物。
至少一个通孔37从芯片34有源上表面穿过芯片34到达无源底面。并且，在半导体芯片34的有源第一表面上，导电芯片焊盘31至少部分地围绕着每个通孔37。举例来说，导电芯片焊盘31可以由铝形成。
WLP80还包括一个上表面连接到半导体芯片34的无源底面上的印刷电路板(PCB)42。例如，PCB42可以通过粘结剂72附着在芯片34上。另外，PCB42包括至少一个与半导体芯片34的各个通孔37相对准的导电PCB焊盘45。
导电塞50填满每个通孔37，并与导电焊盘31和45相接触。如此，在芯片34的芯片焊盘31与PCB42的导电PCB焊盘45之间建立了电接触。并且，绝缘层38可以形成于通孔37的侧壁上，以便使导电塞50与基板32绝缘。
优选地，导电塞50由焊料制成。更为优选地，如图4所示，导电塞50由从PCB42的导电焊盘45伸入通孔中的金属PCB凸起52和围绕PCB凸起52的焊料54的组合来形成。
印刷电路板42优选包括在与每个通孔相对一侧上在每个导电焊盘之下的对齐的孔49。孔49露出导电焊盘45的底面，并如后面的实施例所述，可用于叠置WLP80和/或用于将WLP80连接到外部印刷电路板上。例如，焊球(用于外部连接)可以连接到导电PCB焊盘45的底面上，从而从PCB42的下表面通过孔49向下伸出。然而，可替换地，在没有设置孔49的情况，焊球可以形成在PCB42的下表面上并且通过PCB42与PCB焊盘45电连接。
现在将参考图5至16，这些图是用来解释制造图4的晶片级封装80的连续工序的图。
首先参见图5，设置了一个包括一个半导体基板32的硅晶片30，该基板具有多个半导体集成电路芯片34。如图所示，芯片划片线36将芯片34彼此分开。
图6显示出图5的晶片30的芯片34的一部分的示意性顶视图，图7是沿图6的VII-VII’线剖开的示意性横截面视图。在半导体基板32上，每个集成电路芯片34在半导体基片上包括多个芯片焊盘31和一层钝化层33。钝化层33包括露出芯片焊盘31一部分表面的开口。钝化层33可由二氧化硅、氮化硅或它们的组合物形成。芯片焊盘31可由铝形成。
参见图8，设置了一个包括一个不导电PCB基板42的PCB盘40，该基板具有多个形成于划片线46之间的PCB芯片区域44。PCB芯片区域44与硅晶片30的芯片34(图5)重合，并且PCB盘40的外周边尺寸优选与硅晶片30的相似。然而，优选地，PCB盘40不如硅晶片30那样厚。例如，在8英寸直径晶片的情况，PCB盘40的厚度为约130um。
图9显示出图8的PCB盘40的芯片区域44的一部分的示意性顶视图，图10是沿图9的X-X’线剖开的横截面视图。每个PCB芯片区域44包括在不导电PCB基板42上的多个PCB焊盘45。PCB焊盘45可由铜形成，并且在从上面看时具有正方形形状。PCB基板42具有多个穿过其形成的PCB窗口49。每个PCB窗口49露出对应的PCB焊盘45的底面部分。而且，PCB凸起52形成于每个PCB焊盘45的顶面上。PCB凸起可以通过将一层导电材料，优选一层铜，沉积在PCB盘40和PCB焊盘45顶面41上，然后使该沉积层经受光刻处理而形成。如图所示，PCB凸起52与PCB窗口49对齐。而且，PCB凸起52和PCB焊盘45可以镀上一层金层或一个镍和金的组合层。
参见图11至13，现在将对图5至7的硅晶片30中的通孔的形成进行描述。通孔相应于图4所示的芯片34的通孔37而形成。
首先参见图11，多个槽(trenches)37’穿过芯片焊盘31并到达图7所示的结构内一深度而形成。槽37’可以通过激光打孔、干蚀刻或湿蚀刻(wetetching)而形成。例如，在直径8英寸的晶片的情况下，槽37’的深度为约100um。
参见图12A，一层绝缘层38a形成于硅晶片30的有源表面(activesurface)35之上。绝缘层38a优选由相对于芯片焊盘31和钝化层33具有蚀刻选择性的材料，如二氧化硅、氮化硅或它们的组合物，形成。
参见图12B，光刻胶(photoresist)71沉积在图12A的结构上，由此将槽37’填满。
参见图12C，光刻胶71经受反蚀刻(etchback)技术，从而光刻胶71仅保持在槽37’中。
参见图12D，绝缘层38a用保持在槽37’之内的光刻胶71作蚀刻掩模来进行有选择地蚀刻。
参见图12E，将槽37’内的光刻胶71除去。
作为图12A至12E的过程的结果，获得了其中槽37’的侧壁覆盖有一层绝缘体38的结构。
下面参见图13，硅晶片30的无源表面39经受机械研磨，以便形成完全贯穿硅晶片30的孔37。例如，在直径8英寸、最初厚度为约720um的晶片的情况下，研磨过程后晶片30的厚度为约80um。人们意识到硅晶片30的无源表面39可以改为经受化学机械抛光(CMP)来形成孔37。
下面参见图14至16，现在将描述如何由图8至10的PCB盘40和根据图11至13加工的硅晶片30的组合来形成晶片级封装。
参见图14，硅晶片30相对于PCB盘40而定位，从而集成电路芯片34和硅晶片30的划片线36与PCB盘40的PCB芯片区域44和划片线对齐。用粘结剂72将PCB盘40的顶面连接到硅晶片30的下部无源表面39上。如此，PCB盘40的PCB凸起52插入硅晶片30的孔37中。
参见图15，多个互连凸起54被形成，从而将芯片焊盘31电连接到PCB凸起52上。绝缘体38使得互连凸起54与半导体基板32电绝缘。互连凸起54，优选为焊球，可以通过球放置(ball placement)技术、电镀技术、模板印刷技术或金属喷射技术来形成。在该实施例中，互连凸起54为通过模板印刷和回流而形成的半球状焊球。每对互连凸起54和PCB凸起52组成了塞50。
参见图16，如参考标号78所表示的，在芯片划片线36和PCB划片线46处将制得的图15的结构分成多个封装80。在PCB窗口49上形成了外部端子，未示出。外部端子优选由焊球形成，但是也可由金或镍而不是由焊料来形成。并且，可以在将图15的结构分成多个封装80之前形成外部端子。
于是，封装80是集成电路芯片34和PCB芯片44的组合物，并且PCB芯片44位于半导体集成电路芯片34和外部端子(例如焊球)之间。封装80的外部端子安装在外部印刷电路板上，在这种状态下，PCB芯片44充当减小封装80与外部印刷电路板之间的热膨胀差异的缓冲器。如此，减小了施加到外部端子上的潜在的破坏应力值。
上面描述的晶片级封装80可以用许多不同的方法来改进。例如，PCB窗口45不必在PCB凸起52下对齐，而改为可以与PCB凸起52偏离一段距离。在这种情况下，PCB焊盘可以是细长的，并从PCB凸起52延伸至偏置的PCB窗口45。也就是说，PCB焊盘45可以形成为条状重选路径导电图案。
并且，PCB基板可以不设置PCB窗口。在这种情况下，每个PCB焊盘45将由一个上PCB焊盘和一个下PCB焊盘所取代。上PCB焊盘将形成在PCB基板的顶面上，并且其上形成有PCB凸起52。下PCB焊盘将形成在PCB基板42的下表面上，并且其上形成有外部端子(例如，焊球)。如果上下PCB焊盘彼此对齐，则它们将通过一个贯穿PCB基板42的通孔电连接。如果上下PCB焊盘彼此不对齐，则它们将通过贯穿PCB基板42的通孔和PCB基板42表面上的导电图案的结合而电连接。
在另一种改进中，PCB盘40可以由粘性的带状介质构成，而不是由相对刚性的基板构成。
图17是表示根据本发明一个实施例的多封装叠层90的示意性横截面视图。如图所示，多封装叠层90包括一个叠置在另一个上的多个晶片级封装80。每个晶片级封装80相当于图4中所示的并在上面已描述的晶片级封装。
在该实施例中，在叠层90中，每个晶片级封装80的导电塞50的焊料与PCB焊盘相连并通过上面的晶片级封装80的窗口47。
外部端子60形成于PCB焊盘的底面上，并穿过叠层90的最下层封装80的窗口47。外部端子60优选由焊球形成，但也可由金或镍而不是焊料形成。叠层90的外部端子60安装在一个外部印刷电路板(未示出)上，并且在这种状态下，最下层封装80的PCB芯片44充当减小叠层90与外部印刷电路板之间的热膨胀差异的缓冲器。如此，减小了施加到外部端子60上的潜在的破坏应力值。
图18至20是表示本发明另一个实施例的示意性横截面视图。除了如图18所示的保护层74的形成以外，该实施例与前面的实施例基本上相同。
也就是说，首先参见图19，液体型树脂的保护层74形成于根据图15所示并具有在前面描述的结构的芯片34的有源表面上。液体型树脂通过传递模塑技术(transfer molding technique)、注模技术、丝网印刷技术或分配技术来施加。
参见图20和21，外部端子60以与前面描述的相同的方式形成于PCB底面上，并且如图21的参考标号78所表示的，制得的结构被分成多个封装80。人们注意到，外部端子60可以在封装80分开之后再安装。
在分开之后，得到了图18的结构。其保护层74作用来保护半导体芯片34的有源表面不受外部环境的影响。
图22是表示本发明另一个实施例的多封装叠层190的示意性横截面视图。该实施例与前面所述的图17的叠层的区别在于该实施例最上层的封装180包括图18的保护层74。
图23、24、25和26是表示本发明的另一种改进了的实施例的示意性横截面视图。图23、24、25和26分别与前面描述的图16、17、21和22的区别仅在于在该改进的实施例中没有PCB凸起。
图27、28、29和30是表示本发明另一个实施例的示意性横截面视图。图27、28、29和30分别与前面描述的图23、24、25和26的区别仅在于PCB芯片44和集成电路芯片34的连接是通过各向异性导电薄膜(ACF)ACF 452来实现的。该薄膜的特征在于在垂直于其表面的方向上是导电的，而在平行于其表面的方向上则是不导电的。于是，ACF 452可以施加到芯片的整个底面或PCB的整个顶面上。该实施例的优点在于不需要使前面实施例的粘结剂72形成图案。
图31是表示根据本发明的另一个实施例的多封装叠层690的示意性横截面视图。在与前面的实施例相比，该实施例的特征在于至少两个封装80是倒置的。另外，最底层封装80的互连凸起54被连接到重选路径PCB芯片44上。重选路径PCB芯片44包括PCB焊盘48，每个PCB焊盘48由一个上PCB焊盘45和一个下焊盘47形成。上PCB焊盘45和下PCB焊盘47分别形成于PCB基板42的上、下表面上。外部端子60形成于下PCB焊盘47上。上PCB焊盘45与最底层封装80的孔37对齐，而下PCB焊盘47与孔37不对齐。贯穿PCB基板42形成的信号通路677使每组上PCB焊盘45和下PCB焊盘47电连接。上PCB焊盘45、下PCB焊盘47和信号通路677组成重选路径导电图案。在PCB基板42的上下表面上分别形成一层阻焊剂层688。
叠层690的外部端子60安装在一个外部印刷电路板(未示出)上，并且在这种状态下，在叠层底部的重选路径PCB芯片44充当减小叠层690和外部印刷电路板之间的热膨胀差异的缓冲器。如此，减小了施加到外部端子60上的潜在的破坏应力值。
在附图和说明书中，已经公开了本发明的典型的优选实施例，尽管所阐明的是具体的例子，然而它们仅仅是在一般意义上和描述意义上来使用的，而不是为了限定。很清楚，本发明的保护范围应由附加的权利要求来解释，而不是由这些示例性实施例来解释。

Claims (48)

1、一种半导体芯片封装，包括：
半导体芯片，其包括从有源第一表面到无源第二表面的贯穿其中的通孔；
第一导电焊盘，其在所述半导体芯片的有源第一表面上至少部分地围绕所述通孔；
印刷电路板，其包括连接到所述半导体芯片的无源第二表面上的第一表面，其还包括与所述半导体芯片的通孔对齐的第二导电焊盘；以及
导电材料，其充满所述通孔，并接触所述第一和第二导电焊盘。
2、如权利要求1所述的半导体芯片封装，其中所述导电材料包括焊料。
3、如权利要求2所述的半导体芯片封装，其中所述焊料在所述半导体芯片的有源第一表面上形成焊料凸起。
4、如权利要求1所述的半导体芯片封装，其中所述导电材料包括从所述印刷电路板第二导电焊盘伸入所述通孔中的金属塞以及围绕金属塞的焊料。
5、如权利要求4所述的半导体芯片封装，其中所述焊料在所述半导体芯片有源第一表面上形成焊料凸起。
6、如权利要求1所述的半导体芯片封装，其中所述印刷电路板包括孔，该孔在所述第二导电焊盘之下与所述通孔相对并对齐。
7、如权利要求4所述的半导体芯片封装，进一步包括电极，其与所述第二导电焊盘电连接，并且穿过所述印刷电路板中的所述孔伸出。
8、如权利要求7所述的半导体芯片封装，其中所述电极是焊球。
9、如权利要求1所述的半导体芯片封装，进一步包括电极，其与所述第二导电焊盘电连接，并且被安装在与所述印刷电路板第一表面相对的印刷电路板的第二表面上。
10、如权利要求9所述的半导体芯片封装，其中所述电极是焊球。
11、如权利要求1所述的半导体芯片封装，进一步包括位于所述半导体芯片的通孔侧壁上的绝缘层。
12、如权利要求1所述的半导体芯片封装，进一步包括置于所述半导体芯片无源第二表面与所述印刷电路板第一表面之间的粘结剂层。
13、如权利要求1所述的半导体芯片封装，进一步包括置于所述半导体芯片无源第二表面与所述印刷电路板第一表面之间的各向异性导电薄膜。
14、如权利要求1所述的半导体芯片封装，进一步包括覆盖所述半导体芯片的有源第一表面的保护层。
15、一种半导体多封装叠层，包括：
多个叠置的半导体芯片封装，每个芯片封装包括(a)半导体芯片，其包括从有源第一表面到无源第二表面的贯穿其中的通孔，(b)第一导电焊盘，其在所述半导体芯片的有源第一表面上至少部分地围绕所述通孔，(c)印刷电路板，其包括连接到所述半导体芯片的无源第二表面上的第一表面以及与所述半导体芯片的通孔对齐的第二导电焊盘，以及(d)导电材料，其充满所述通孔，并接触所述第一和第二导电焊盘。
16、如权利要求15所述的半导体多封装叠层，其中所述半导体芯片封装叠置，从而下面的芯片封装的导电材料与相邻的上面芯片封装的印刷电路板相接触。
17、如权利要求16所述的半导体多封装叠层，其中每个半导体芯片封装的导电材料包括焊料。
18、如权利要求17所述的半导体多封装叠层，其中所述焊料在每个半导体芯片封装的半导体芯片有源第一表面上形成焊料凸起。
19、如权利要求18所述的半导体多封装叠层，其中所述每个半导体芯片封装的导电材料包括从所述印刷电路板第二导电焊盘伸入所述通孔中的金属塞以及围绕金属塞的焊料。
20、如权利要求19所述的半导体多封装叠层，其中所述焊料在每个半导体芯片封装的所述半导体芯片有源第一表面上形成焊料凸起。
21、如权利要求16所述的半导体多封装叠层，其中所述每个半导体芯片封装的印刷电路板包括孔，该孔在所述第二导电焊盘之下与所述通孔相对并对齐，并且下面芯片封装的导电材料通过相邻的上面芯片封装的孔与相邻的上面芯片封装的印刷电路板的第二导电焊盘相接触。
22、如权利要求16所述的半导体多封装叠层，进一步包括电极，其与最底层的半导体芯片封装的第二导电焊盘电连接，并且穿过所述最底层半导体芯片封装的印刷电路板中的所述孔伸出。
23、如权利要求16所述的半导体多封装叠层，其中所述电极是焊球。
24、如权利要求16所述的半导体多封装叠层，进一步包括电极，其与最底层半导体芯片封装的第二导电焊盘电连接，并且被安装在与所述印刷电路板第一表面相对的印刷电路板的第二表面上。
25、如权利要求24所述的半导体多封装叠层，其中所述电极是焊球。
26、如权利要求16所述的半导体多封装叠层，进一步包括位于每个半导体芯片封装的半导体芯片的所述通孔侧壁上的绝缘层。
27、如权利要求16所述的半导体多封装叠层，进一步包括置于每个半导体芯片封装的所述半导体芯片无源第二表面与所述印刷电路板第一表面之间的粘结剂层。
28、如权利要求16所述的半导体多封装叠层，进一步包括置于每个半导体芯片封装的所述半导体芯片无源第二表面与所述印刷电路板第一表面之间的各向异性导电薄膜。
29、如权利要求16所述的半导体多封装叠层，进一步包括一层覆盖最上层半导体芯片封装的半导体芯片的有源第一表面的保护层。
30、如权利要求15所述的半导体多封装叠层，其中半导体芯片封装叠置，从而上面的芯片封装的导电材料与相邻的下面的芯片封装的印刷电路板相接触。
31、如权利要求30所述的半导体多封装叠层，进一步包括外部印刷电路板，该外部印刷电路板具有形成于第一表面上的第一导电焊盘和形成于相对的第二表面上的第二导电焊盘，并还具有连接到所述第二导电焊盘上的外部电极，其中最底层半导体芯片封装的导电材料连接到所述外部印刷电路板的第一导电焊盘上，并且所述外部印刷电路板的第一和第二导电焊盘电连接。
32、如权利要求31所述的半导体多封装叠层，其中所述外部电极是焊球。
33、一种制造半导体芯片封装的方法，所述方法包括：
形成穿过半导体芯片的通孔，所述通孔从该半导体芯片的有源第一表面延伸至所述半导体芯片的相对的无源第二表面，其中在所述半导体芯片第一表面上，第一导电焊盘至少部分地围绕所述通孔；
将印刷电路板的第一表面连接到所述芯片的第二表面，从而所述印刷电路板的第二导电焊盘与所述半导体芯片的通孔对齐；以及
用导电材料填满所述通孔，从而所述导电材料接触所述第一和第二导电焊盘。
34、如权利要求33所述的方法，还包括形成从所述第二导电焊盘伸出的金属塞，并在将所述印刷电路板第一表面连接到所述半导体芯片第二表面上时，将所述金属塞插入所述半导体芯片的所述通孔中。
35、如权利要求33所述的方法，其中在形成所述通孔之前，所述第一导电焊盘形成于所述芯片的有源第一表面上，并且通孔穿过所述第一导电焊盘而形成，从而所述第一导电焊盘的剩余部分至少部分地围绕着所述通孔。
36、如权利要求33所述的方法，其中所述通孔的所述形成过程包括：
在所述半导体芯片第一表面上形成槽；
将一层绝缘层至少沉积在所述槽的侧壁上；以及
除去所述半导体芯片第二表面的表面部分以便露出所述槽。
37、如权利要求36所述的方法，其中所述半导体芯片第二表面的所述表面部分通过机械研磨而除去。
38、如权利要求36所述的方法，其中所述半导体芯片第二表面的所述表面部分通过化学机械抛光而除去。
39、如权利要求33所述的方法，其中利用粘结剂将所述印刷电路板第一表面连接到所述半导体芯片第二表面上。
40、如权利要求33所述的方法，其中利用各向异性的导电薄膜将所述印刷电路板第一表面连接到所述半导体芯片第二表面上。
41、如权利要求33所述的方法，其中所述导电材料通过所述各向异性导电薄膜与所述第二导电焊盘电连接。
42、一种制造半导体芯片封装的方法，所述方法包括：
形成多个穿过包含在晶片中的相应的多个半导体芯片的通孔，所述通孔从所述晶片的有源第一表面延伸至该晶片的相对的无源第二表面，其中在所述晶片的第一表面上，第一导电焊盘至少部分地围绕每个通孔；
在印刷电路板的第一表面上形成多个第二导电焊盘；
将印刷电路板的所述第一表面连接到所述晶片的第二表面上，从而所述多个第二导电焊盘分别与所述多个通孔对齐；以及
用一种导电材料填满所述多个通孔，从而所述导电材料接触每个通孔的所述第一和第二导电焊盘。
43、如权利要求42所述的方法，还包括将所述印刷电路板固定于其上的所述晶片切成多个半导体芯片封装。
44、如权利要求42所述的方法，其中所述通孔的所述形成包括：
在所述晶片的每个半导体芯片的第一表面上形成槽；
将一层绝缘层至少沉积在所述晶片的每个半导体芯片的所述槽的侧壁上；以及
除去所述晶片第二表面的表面部分以便露出所述晶片的每个半导体芯片的所述槽。
45、如权利要求44所述的方法，其中所述晶片第二表面的所述表面部分通过机械研磨而除去。
46、如权利要求44所述的方法，其中所述晶片第二表面的所述表面部分通过化学机械抛光而除去。
47、如权利要求42所述的方法，其中利用一种粘结剂将所述印刷电路板第一表面连接到所述晶片的第二表面上。
48、如权利要求42所述的方法，其中利用各向异性的导电薄膜将所述印刷电路板第一表面连接到所述晶片第二表面上。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7746663B2 (en) 2005-07-06 2010-06-29 Seiko Epson Corporation Electronic substrate and electronic device
CN101330071B (zh) * 2007-06-19 2011-03-16 三星电机株式会社 安装基板及其制造方法
CN101452919B (zh) * 2007-12-07 2011-03-16 南茂科技股份有限公司 多晶片交互交错堆叠封装结构
US8053902B2 (en) 2008-12-02 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure for protecting dielectric layers from degradation
US8093703B2 (en) 2007-08-10 2012-01-10 Samsung Electronics Co., Ltd. Semiconductor package having buried post in encapsulant and method of manufacturing the same
US8227902B2 (en) 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
CN102881665A (zh) * 2011-07-14 2013-01-16 英飞凌科技股份有限公司 用于晶片级封装的系统和方法

Families Citing this family (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
JP4074862B2 (ja) * 2004-03-24 2008-04-16 ローム株式会社 半導体装置の製造方法、半導体装置、および半導体チップ
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US20050269680A1 (en) * 2004-06-08 2005-12-08 Min-Chih Hsuan System-in-package (SIP) structure and fabrication thereof
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US20060019468A1 (en) 2004-07-21 2006-01-26 Beatty John J Method of manufacturing a plurality of electronic assemblies
US7425499B2 (en) * 2004-08-24 2008-09-16 Micron Technology, Inc. Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
US7083425B2 (en) * 2004-08-27 2006-08-01 Micron Technology, Inc. Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
DE102004046227B3 (de) * 2004-09-22 2006-04-20 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten durch eine Kunststoffgehäusemasse und entsprechendes Halbleiterbauteil
US20060097400A1 (en) * 2004-11-03 2006-05-11 Texas Instruments Incorporated Substrate via pad structure providing reliable connectivity in array package devices
JP4528100B2 (ja) * 2004-11-25 2010-08-18 新光電気工業株式会社 半導体装置及びその製造方法
JP4063277B2 (ja) * 2004-12-21 2008-03-19 セイコーエプソン株式会社 半導体装置の製造方法
JP4349278B2 (ja) * 2004-12-24 2009-10-21 セイコーエプソン株式会社 半導体装置の製造方法
US7271482B2 (en) * 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7394159B2 (en) * 2005-02-23 2008-07-01 Intel Corporation Delamination reduction between vias and conductive pads
DE102005010272A1 (de) * 2005-03-03 2006-09-14 Infineon Technologies Ag Halbleiterbauelement sowie Verfahren zum Herstellen eines Halbleiterbauelements
JP4551255B2 (ja) * 2005-03-31 2010-09-22 ルネサスエレクトロニクス株式会社 半導体装置
TWI263284B (en) * 2005-05-03 2006-10-01 Advanced Semiconductor Eng Method of fabricating wafer level package
US7768113B2 (en) * 2005-05-26 2010-08-03 Volkan Ozguz Stackable tier structure comprising prefabricated high density feedthrough
US7919844B2 (en) * 2005-05-26 2011-04-05 Aprolase Development Co., Llc Tier structure with tier frame having a feedthrough structure
US7317256B2 (en) * 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7622377B2 (en) * 2005-09-01 2009-11-24 Micron Technology, Inc. Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
JP5222459B2 (ja) * 2005-10-18 2013-06-26 新光電気工業株式会社 半導体チップの製造方法、マルチチップパッケージ
KR100652440B1 (ko) * 2005-10-27 2006-12-01 삼성전자주식회사 반도체 패키지, 그 패키지를 이용한 스택 패키지 및 그스택 패키지 형성 방법
US8114771B2 (en) * 2006-01-13 2012-02-14 Stats Chippac Ltd. Semiconductor wafer scale package system
TW200737506A (en) * 2006-03-07 2007-10-01 Sanyo Electric Co Semiconductor device and manufacturing method of the same
KR100780692B1 (ko) * 2006-03-29 2007-11-30 주식회사 하이닉스반도체 칩 스택 패키지
TW200741959A (en) * 2006-04-20 2007-11-01 Min-Chang Dong A die and method fabricating the same
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US7385283B2 (en) * 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
US7605019B2 (en) * 2006-07-07 2009-10-20 Qimonda Ag Semiconductor device with stacked chips and method for manufacturing thereof
US7446424B2 (en) * 2006-07-19 2008-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for semiconductor package
US8102039B2 (en) * 2006-08-11 2012-01-24 Sanyo Semiconductor Co., Ltd. Semiconductor device and manufacturing method thereof
US7629249B2 (en) * 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
JP4322903B2 (ja) * 2006-08-29 2009-09-02 シャープ株式会社 半導体装置、および半導体装置の製造方法
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
DE102006042774A1 (de) * 2006-09-12 2008-03-27 Qimonda Ag Verfahren zur Herstellung einer elektrischen Ankontaktierung
WO2008054119A2 (en) 2006-10-30 2008-05-08 Lg Electronics Inc. Methods for transmitting access channel message and response message, and mobile communication terminals
JP5010247B2 (ja) * 2006-11-20 2012-08-29 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
KR100833194B1 (ko) * 2006-12-19 2008-05-28 삼성전자주식회사 반도체 칩의 배선층이 기판에 직접 연결된 반도체 패키지및 그 제조방법
SG166773A1 (en) * 2007-04-24 2010-12-29 United Test & Assembly Ct Lt Bump on via-packaging and methodologies
US8829663B2 (en) * 2007-07-02 2014-09-09 Infineon Technologies Ag Stackable semiconductor package with encapsulant and electrically conductive feed-through
KR100906065B1 (ko) * 2007-07-12 2009-07-03 주식회사 동부하이텍 반도체칩, 이의 제조 방법 및 이를 가지는 적층 패키지
SG149710A1 (en) * 2007-07-12 2009-02-27 Micron Technology Inc Interconnects for packaged semiconductor devices and methods for manufacturing such devices
KR101387701B1 (ko) 2007-08-01 2014-04-23 삼성전자주식회사 반도체 패키지 및 이의 제조방법
TWI345296B (en) * 2007-08-07 2011-07-11 Advanced Semiconductor Eng Package having a self-aligned die and the method for making the same, and a stacked package and the method for making the same
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
US20090085207A1 (en) * 2007-09-28 2009-04-02 Texas Instruments, Inc. Ball grid array substrate package and solder pad
KR20090047776A (ko) * 2007-11-08 2009-05-13 삼성전자주식회사 반도체 소자 및 그 형성 방법
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US8399973B2 (en) * 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
CN101681848B (zh) * 2008-05-21 2011-11-02 精材科技股份有限公司 电子元件封装体
KR100974244B1 (ko) * 2008-06-12 2010-08-05 엘지이노텍 주식회사 반도체 패키지 기판 및 반도체 패키지 기판의 제조방법
JP2010040862A (ja) * 2008-08-06 2010-02-18 Fujikura Ltd 半導体装置
JP4674622B2 (ja) * 2008-09-05 2011-04-20 ミツミ電機株式会社 センサモジュール及びその製造方法
US7872332B2 (en) 2008-09-11 2011-01-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US8058732B2 (en) * 2008-11-20 2011-11-15 Fairchild Semiconductor Corporation Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same
JP5308145B2 (ja) * 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
KR101028573B1 (ko) 2008-12-24 2011-04-12 주식회사 심텍 칩스케일 패키지 및 그 제조 방법
US8264077B2 (en) * 2008-12-29 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips
US7894230B2 (en) 2009-02-24 2011-02-22 Mosaid Technologies Incorporated Stacked semiconductor devices including a master device
KR101069288B1 (ko) * 2009-08-10 2011-10-05 주식회사 하이닉스반도체 반도체 패키지
US8329575B2 (en) * 2010-12-22 2012-12-11 Applied Materials, Inc. Fabrication of through-silicon vias on silicon wafers
KR101253976B1 (ko) * 2011-06-03 2013-04-12 에스티에스반도체통신 주식회사 반도체 패키지 장치 및 이의 제조방법
US9324673B2 (en) 2011-06-23 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with wafer level reconfiguration and method of manufacture thereof
KR101411810B1 (ko) 2012-09-27 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9240331B2 (en) * 2012-12-20 2016-01-19 Stats Chippac, Ltd. Semiconductor device and method of making bumpless flipchip interconnect structures
CN103165543B (zh) * 2013-02-08 2015-11-18 日月光半导体制造股份有限公司 半导体元件及其制造方法与封装构造
KR101640076B1 (ko) * 2014-11-05 2016-07-15 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨의 칩 적층형 패키지 및 이의 제조 방법
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
US10043740B2 (en) * 2016-07-12 2018-08-07 Intel Coporation Package with passivated interconnects
CN108335986B (zh) * 2017-09-30 2021-04-06 中芯集成电路（宁波）有限公司 一种晶圆级系统封装方法
US10535636B2 (en) 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
DE102018124695A1 (de) 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
TWI665948B (zh) * 2018-07-04 2019-07-11 欣興電子股份有限公司 電路板元件及其製作方法
US11705420B2 (en) * 2020-10-29 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-bump connection to interconnect structure and manufacturing method thereof

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US520754A (en) * 1894-05-29 Frederick burmeister
US4700473A (en) * 1986-01-03 1987-10-20 Motorola Inc. Method of making an ultra high density pad array chip carrier
US4700276A (en) * 1986-01-03 1987-10-13 Motorola Inc. Ultra high density pad array chip carrier
US5046238A (en) * 1990-03-15 1991-09-10 Rogers Corporation Method of manufacturing a multilayer circuit board
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5202754A (en) 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
DE4433833A1 (de) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung unter Erreichung hoher Systemausbeuten
JP2916086B2 (ja) * 1994-10-28 1999-07-05 株式会社日立製作所 電子部品の実装方法
JP3186941B2 (ja) 1995-02-07 2001-07-11 シャープ株式会社 半導体チップおよびマルチチップ半導体モジュール
US5973396A (en) 1996-02-16 1999-10-26 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
JPH09307013A (ja) 1996-05-10 1997-11-28 Mitsui High Tec Inc 半導体集積回路装置およびその製造方法
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
JP3920399B2 (ja) 1997-04-25 2007-05-30 株式会社東芝 マルチチップ半導体装置用チップの位置合わせ方法、およびマルチチップ半導体装置の製造方法・製造装置
KR19990003745A (ko) 1997-06-26 1999-01-15 이형도 디지탈블럭 및 아날로그블럭이 구비된 집적회로의 안정화회로
JPH11163521A (ja) 1997-11-26 1999-06-18 Matsushita Electric Works Ltd 多層プリント配線板の製造方法
JPH11163251A (ja) 1997-11-28 1999-06-18 Matsushita Electron Corp 半導体装置
JP3563604B2 (ja) 1998-07-29 2004-09-08 株式会社東芝 マルチチップ半導体装置及びメモリカード
US6488661B1 (en) * 1998-07-31 2002-12-03 Medrad, Inc. Pressure control systems for medical injectors and syringes used therewith
JP4547728B2 (ja) * 1999-03-29 2010-09-22 ソニー株式会社 半導体装置及びその製造方法
JP3360655B2 (ja) 1999-07-08 2002-12-24 日本電気株式会社 半導体装置
JP4245754B2 (ja) 1999-11-02 2009-04-02 パナソニック株式会社 半導体装置
JP2001148457A (ja) 1999-11-22 2001-05-29 Matsushita Electronics Industry Corp 高周波用半導体装置
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
JP3757766B2 (ja) 2000-07-07 2006-03-22 セイコーエプソン株式会社 半導体装置及びその製造方法、並びに電子機器
US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
JP3951091B2 (ja) * 2000-08-04 2007-08-01 セイコーエプソン株式会社 半導体装置の製造方法
US6379982B1 (en) 2000-08-17 2002-04-30 Micron Technology, Inc. Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
US6459150B1 (en) * 2000-08-17 2002-10-01 Industrial Technology Research Institute Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer
JP2002064265A (ja) * 2000-08-18 2002-02-28 Toshiba It & Control Systems Corp Ｂｇａ実装方法
JP2002076247A (ja) 2000-08-25 2002-03-15 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
JP3854054B2 (ja) 2000-10-10 2006-12-06 株式会社東芝 半導体装置
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8416578B2 (en) 2005-07-06 2013-04-09 Seiko Epson Corporation Manufacturing method for an electronic substrate
US9496202B2 (en) 2005-07-06 2016-11-15 Seiko Epson Corporation Electronic substrate
US9087820B2 (en) 2005-07-06 2015-07-21 Seiko Epson Corporation Electronic substrate
US8284566B2 (en) 2005-07-06 2012-10-09 Seiko Epson Corporation Electronic substrate
US7746663B2 (en) 2005-07-06 2010-06-29 Seiko Epson Corporation Electronic substrate and electronic device
CN101330071B (zh) * 2007-06-19 2011-03-16 三星电机株式会社 安装基板及其制造方法
US8093703B2 (en) 2007-08-10 2012-01-10 Samsung Electronics Co., Ltd. Semiconductor package having buried post in encapsulant and method of manufacturing the same
US8846446B2 (en) 2007-08-10 2014-09-30 Samsung Electronics Co., Ltd. Semiconductor package having buried post in encapsulant and method of manufacturing the same
US8604594B2 (en) 2007-11-26 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US8227902B2 (en) 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
CN101452919B (zh) * 2007-12-07 2011-03-16 南茂科技股份有限公司 多晶片交互交错堆叠封装结构
US8053902B2 (en) 2008-12-02 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure for protecting dielectric layers from degradation
CN102881665A (zh) * 2011-07-14 2013-01-16 英飞凌科技股份有限公司 用于晶片级封装的系统和方法
CN102881665B (zh) * 2011-07-14 2015-06-03 英飞凌科技股份有限公司 用于晶片级封装的系统和方法

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