CN1547695A - 具有基于活动线程号的寄存器分配的多线程微处理器 - Google Patents

具有基于活动线程号的寄存器分配的多线程微处理器 Download PDF

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CN1547695A
CN1547695A CNA028167732A CN02816773A CN1547695A CN 1547695 A CN1547695 A CN 1547695A CN A028167732 A CNA028167732 A CN A028167732A CN 02816773 A CN02816773 A CN 02816773A CN 1547695 A CN1547695 A CN 1547695A
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M����ɭ��³˹
M·罗森布鲁斯
C·沃尔里奇
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D·伯恩斯坦恩
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Abstract

多线程处理器中的一种机制，用于根据指示多少线程正在使用中的配置信息来分配资源。

Description

具有基于活动线程号的寄存器分配的多线程微处理器
                      相关申请的交叉参考
本申请要求以下申请的优先权：美国临时专利申请序列号60/315144(代理人摘要号为10559-579P01)，于2001年8月27日提交。
                            背景
一般而言，多线程微处理器的硬件实现为每个线程的使用提供了固定数目的资源，比如寄存器、程序计数器等等。根据在微处理器上执行的应用程序内的对应量，不会使用某些线程。因此，未使用的线程资源被浪费，尤其是那些资源所耗用的功率和硅面积。
                         附图描述
图1示出一通信系统的框图，该通信系统采用了具有多线程微型发动机的处理器来支持多线程的执行。
图2示出微型发动机(图1的)的框图。
图3示出用于选择多个“使用中”线程的微型发动机控制和状态寄存器(CSR)。
图4示出(图2的微型发动机的)通用寄存器(GPS)文件的双库实现的示意图，该文件使用所选数目的“使用中”线程为线程分配寄存器。
图5示出八个“使用中”线程和四个“使用中”线程的线程GPR分配表。
图6A和6B分别示出按照八个“使用中”线程和四个“使用中”线程的线程GPR分配在GPR文件内的寄存器分区。
                         详细描述
参照图1，通信系统10包括处理器12，处理器12耦合到一个或多个I/O设备，比如网络设备14和16，还包括存储器系统18。处理器12是多线程的微处理器，因此尤其用于可被分成并行的子任务或函数的任务。在一个实施例中，如图所示，处理器12包括多个微型发动机20，每个都有多个硬件控制的程序线程22，这些线程可以是同时活动的，并且独立地对一个任务起作用。在所示示例中，有“n”个微型发动机20，每个微型发动机20都能处理多个程序线程22，下面将更完整地描述。在所述实施例中，所支持的环境线程的最大数目“N”为八，但也可以提供其它最大数。最好是，每个微型发动机20都连接到相邻的微型发动机并且与之通信。
处理器12还包括处理器24，处理器24帮助加载对处理器12的其它资源的微码控制，并且执行诸如处理协议和异常这样的其它通用计算机类型函数。在网络处理应用中，处理器24还可以为不能被微型发动机20处理的较高层网络处理任务提供支持。在一个实施例中，处理器24是基于StrongARM(ARM是英国ARM有限公司的商标)内核的结构。处理器(或内核)24具有一操作系统，处理器24通过该操作系统可以调用函数来操作微型发动机20。处理器24可以使用任何被支持的操作系统，最好是实时操作系统。也可以使用其它处理器结构。
微型发动机20各自与共享资源一起操作，共享资源包括：存储器系统18、PCI总线接口26、I/O接口28、哈希单元30和便笺式存储器32。PCI总线接口26向PCI总线(未示出)提供一接口。I/O接口28负责控制处理器12并将其接入网络设备14、16。存储器系统18包括用DRAM控制器36存取的动态随机存取存储器(DRAM)34、以及用SRAM控制器40存取的静态随机存取存储器(SRAM)38。尽管未示出，处理器12还会包括用于支持启动操作的非易失性存储器。DRAM34和DRAM控制器36一般用于处理大体积的数据，如处理来自网络分组的有效负载。在网络实现中，SRAM38和SRAM控制器40用于低等待时间的、快速存取任务，如存取处理器24的查找表、存储器等等。微型发动机20可以执行到DRAM控制器36或SRAM控制器40的存储器引用指令。
设备14和16可以是能发送并且/或者接收网络话务数据的任何网络设备，比如组帧/MAC设备，例如用于连接到10/100BaseT以太网、千兆比特以太网、ATM或其它类型的网络，或者用于连接到开关结构的设备。例如，在一种布局中，网络设备14可以是向处理器12发送分组数据的以太网MAC设备(连接到以太网网络，未示出)，而设备16可以是从处理器12接收被处理的分组数据的开关结构设备用于发送到开关结构上。在这种实现中，也就是，当处理要被发送到开关结构的话务时，处理器12会担当入口网络处理器。或者，处理器12会担当出口网络处理器，处理从开关结构接收到的并且指向另一网络设备的话务，另一网络设备有：网络设备14，或者耦合到这种设备的网络。尽管处理器12可以工作在单机模式，支持两种话务方向，然而可以理解，为了达到较高的性能，可能希望使用两个专用处理器，一个作为入口处理器，另一个作为出口处理器。这两个专用处理器各自与设备14和16耦合。此外，各个网络设备14、16可以包括要被处理器12服务的多个端口。因此，I/O接口28支持一类或多类接口，比如用于物理层(PHY)设备和较高协议层(如链路层)之间的分组和单元传输的接口、或者用于异步传输模式(ATM)、因特网协议(IP)、以太网和类似的数据通信应用的话务管理器和开关结构之间的接口。I/O接口28包括分开的接收和发送块，每个块都单独地用于处理器12所支持的特定接口。
处理器12还可以服务其它设备，比如主机和/或PCI外部设备(未示出)，它们可以耦合到PC接口26所控制的PCI总线。
通常，作为网络处理器，处理器12可以接到接收/发送大量数据的任何类型的通信设备或接口。充当网络处理器的处理器12会从像网络设备14这样的网络设备接收分组数据单元，并且以并行方式处理那些分组数据单元，如下所述。分组数据单元会包括整个网络分组(如以太网分组)或者一部分这样的分组，如一个单元或一个分组段。
处理器12的每个功能性单元都耦合到内部总线结构42。存储器总线44a、44b分别把存储器控制器36和40耦合到存储器系统18的相应存储器单元DRAM34和SRAM38。I/O接口28分别通过分开的I/O总线46a和46b耦合到设备14和16。
参照图2，示出一个示例性的微型发动机20。微型发动机(ME)20包括一个控制单元50，控制单元50包括控制存储器51、控制逻辑(即微控制器)52和环境判优器/事件逻辑53。控制存储器51用于存储微程序。微程序可以由处理器24加载。
微控制器52包括每个所支持线程的指令解码器和程序计数器单元。环境判优器/事件逻辑53从每一个共享资源接收消息(如SRAM事件应答)，共享资源如：SRAM38、DRAM34或处理器内核24等等。这些消息提供了与所请求的函数是否完成有关的信息。
环境判优器/事件逻辑53对八个线程判优。在一个实施例中，判优是一个循环机制。然而，也可以使用其它判优技术，比如优先级队列或加权的合理队列。
微型发动机20还包括执行数据通路54以及耦合到控制单元50的通用寄存器(GPR)文件单元56。数据通路54包括几个数据通路元件，如图所示，第一数据通路元件58、第二数据通路元件59和第三数据通路元件60。数据通路元件可以包括例如ALU和乘法器。GPR文件单元56向各个数据通路元件提供操作数。GPR文件单元56的寄存器在程序控制下被专门地读写。GPR在用作指令内来源时向数据通路54提供操作数。在用作指令内的目的地时，用数据通路54的结果写入它们。指令指定了为源或目的地选择的特定GPR的寄存器号目。控制单元50所提供的指令内的操作码位选择了哪个数据通路元件要执行指令所定义的操作。
微型发动机20还包括写传输寄存器文件62和读传输寄存器文件64。写传输寄存器文件62存储要被写入微型发动机外部的资源(例如DRAM存储器或SRAM存储器)的数据。读传输寄存器文件64用于存储来自微型发动机20外部的资源的返回数据。在数据到达之后或同时，可以提供来自相应共享资源(如存储器控制器36、40或内核24)的事件信号64，来警告请求该数据的线程：数据可用或者已经被发送。两个传输寄存器文件62、64都连接到数据通路54、GPR文件单元56、以及控制单元50。
微型发动机20内还包括本地存储器66。本地存储器66由寄存器68a、68b定址，它也向数据通路54提供操作数。本地存储器66从数据通路54接收结果作为目的地。微型发动机20还包括：本地控制和状态寄存器(CSR)70，用于存储本地线程间和全局事件信令信息以及其它信息；以及耦合到传输寄存器的CRC单元72，与执行数据通路54并行操作并且为ATM单元执行CRC计算。本地CSR和CRC单元72耦合到传输寄存器、数据通路54和GPR文件单元56。
除了向写传输单元62提供输出以外，数据通路54还可以在线80上向GPR文件56提供输出。这样，每个数据通路元件从可以自被执行时返回一个结果值。
微型发动机线程22的功能是由为特定用户的应用程序被加载(通过内核处理器24)到每个微型发动机的控制存储器51内的微码来确定的。例如，在一个示例性线程任务指定中，指定一个线程作为接收调度器线程，指定另一个作为发送调度器线程，把多个线程配置为接收处理线程和发送处理线程，而其它线程任务指定包括发送判优器以及一个或多个内核通信线程。一旦被起动，线程就独立地执行它的功能。
参照图3，CSR70包括环境使能寄存器(“CTX_Enable”)90，该寄存器90包括“使用中”环境字段92，字段92用于指示使用中的预先选择的线程或环境数目。“使用中”环境字段92存储单个位，该位在被清除时(X＝0)指示所有的8个可用线程都在使用中，而当被设定时(X＝1)指示仅有预定义数目的线程在使用中，例如4个，更具体地说是线程0、2、4和6。
如图4所示，GPR文件单元56的GPR可以物理地和逻辑地被包含在两个库内，A库56a和B库56b。两个库内的GPR都包括数据部分100和地址部分102。多路复用器104与每个寄存器地址路径102耦合，从控制单元50接收线程号104和寄存器号106(来自指令)作为输入。多路复用器104的输出受使能信号110控制，该输出也就是被提供给地址路径102以选择寄存器109之一的“地址”形式。使能信号110的状态通过在CTX_Enable寄存器90的字段92内设定“In_Use”环境位来确定。
通常，每个线程具有为其分配的固定百分比的寄存器，例如在支持八个线程时为百分之一。如果未使用某些线程，则那些未使用线程专用的寄存器也不被使用。
相反，通过CTX_Enable CSR 90内的“使用中”环境配置信息控制的多路复用器104的使用允许重新划分寄存器地址内活动线程号/指令(寄存器号)位的位数，以及从而把寄存器重新分配给线程。更具体地说，当字段92内的位等于“0”时，“使用中”的线程数为8，且使能110控制多路复用器104选择活动线程号106的所有位以及由当前指令指定的寄存器号108的除最高有效位以外的所有位。相反，当字段92内的位被设为“1”时，“使用中”的线程数减少一半，且重新分布可用于分配的寄存器数目，使得每线程分配的寄存器数目加倍。
图5示出32个寄存器的寄存器文件的线程分配。对于8个线程，线程号0到7而言，每个线程分配到总共四个寄存器。对于4个线程，线程号0、2、4和6而言，每个线程分配到总共八个寄存器。
图6A和6B示出具有32个寄存器的寄存器文件(例如单个库，寄存器文件56a)，这32个寄存器可用于在最大八个所支持线程中间的线程分配和重新分配。在8线程的配置120中，也就是有八个使用中的线程的情况，如图6A所示，每个线程都分配到四个寄存器。由于使能110为低，因此多路复用器104选择线程号的二进制表示的所有三个位、以及自指令的寄存器号的二进制表示中除最高有效位以外的所有位(也就是，选择两个位(位0和1))。对于4线程的配置122而言，也就是当使能110为高因此有四个线程时，如图6所示，四个线程的每一个都分配到八个寄存器。多路复用器104选择线程号的二进制表示的除最低有效位以外的所有位(在该情况下，选择两个位，位1和2)、以及自指令的寄存器号的二进制表示的所有位。这样，寄存器文件内的地址是当前活动的线程号的位与来自指令的寄存器号的位的并置，且通过设定CTX_Enable寄存器90(来自图3)内的In_Use环境位92来确定对每个起作用的位数。
这样，GPR被逻辑地细分成相等的区域，使得每个环境都对区域之一有相对存取。区域数目在In_Use环境字段92内被配置，或为4或为8。这样，环境有关的寄存器数目实际上与多个不同的物理寄存器相关。通过环境以上述方式作出存取请求，即与寄存器号并置的环境号，来确定要存取的实际寄存器。环境有关的存取是强有力的特征，它能使八个或四个不同的线程共享相同的代码图像，仍然保持分开的数据。这样，指令指定了环境有关的地址(寄存器号)。对于八个活动的环境而言，指令总是在范围0-3内指定寄存器。对于四个活动的环境而言，指令总是在范围0-7内指定寄存器。
回过头参照图4所示的表，绝对GPR寄存器号是由寄存器地址路径(解码逻辑)实际用来存取指定的环境有关寄存器的寄存器号。例如，根据8个活动的环境，环境(或线程)2的环境有关的线程0为8。
上述线程GPR分配方案可以扩展到不同的线程和寄存器数目(基于2的倍数)，例如，把总共128个寄存器从最大数8个“使用中”线程(每个有16个寄存器)重新分配为4个“使用中”的线程(每个有32个寄存器)，或者把总共128个寄存器从最大数16个“使用中”线程(每个有8个寄存器)重新分配为8个“使用中”的线程(每个有16个寄存器)。
其它实施例也在所附权利要求的范围内。

Claims (18)

1.一种在多线程处理器内分配资源的方法，包括：
提供由多线程处理器支持的执行线程所用的资源；以及
向资源选择应用配置信息，以便在活动的执行线程中分配资源。
2.如权利要求1所述的方法，其特征在于，所述资源包括：
通用寄存器文件内的寄存器。
3.如权利要求1所述的方法，其特征在于，所述配置信息包括：
配置位，当被清除时指示所有所支持的执行线程是活动的执行线程，并且当被设定时指示一部分所支持的执行线程是活动的执行线程。
4.如权利要求1所述的方法，其特征在于，所述配置信息包括：
配置位，当被清除时指示所有所支持的执行线程是活动的执行线程，并且当被设定时指示所支持的执行线程的一半是活动的执行线程。
5.如权利要求3所述的方法，其特征在于，所述配置位驻留在控制和状态寄存器内。
6.如权利要求2所述的方法，其特征在于，所述通用寄存器文件包括一个地址解码部分和与所述地址解码部分耦合的多路复用器，所述多路复用器用于接收一个线程号和寄存器号作为输入，并且用于根据配置信息选择线程号和寄存器号的位，以形成对应于一个寄存器的地址。
7.如权利要求6所述的方法，其特征在于，所述配置信息指示选择线程号的除最低有效位以外的所有位以及寄存器号的所有位。
8.如权利要求6所述的方法，其特征在于，所述配置信息指示选择寄存器号的除最高有效位以外的所有位以及线程号的所有位。
9.如权利要求6所述的方法，其特征在于，寄存器号的所选位形成线程有关的寄存器号。
10.一种处理器，包括：
由处理器所支持的执行线程所使用的资源；以及
资源选择器，用于接收配置信息，并且用于根据配置信息在活动的执行线程中分配资源。
11.如权利要求10所述的处理器，其特征在于，所述资源包括：
通用寄存器文件内的寄存器。
12.如权利要求10所述的处理器，其特征在于，所述配置信息包括：
配置位，当被清除时指示所有所支持的执行线程是活动的执行线程，并且当被设定时指示一部分所支持的执行线程是活动的执行线程。
13.如权利要求10所述的处理器，其特征在于，所述配置信息包括：
配置位，当被清除时指示所有所支持的执行线程是活动的执行线程，并且当被设定时指示所支持的执行线程的一半是活动的执行线程。
14.如权利要求12所述的处理器，其特征在于，所述配置位驻留在控制和状态寄存器内。
15.如权利要求11所述的处理器，其特征在于，所述通用寄存器文件包括一个地址解码部分，资源选择器是与所述地址解码部分耦合的多路复用器，所述多路复用器用于接收一个线程号和寄存器号作为输入，并且用于根据配置信息选择线程号和寄存器号的位，以形成对应于一个寄存器的地址。
16.如权利要求15所述的处理器，其特征在于，所述配置信息指示选择线程号的除最低有效位以外的所有位以及寄存器号的所有位。
17.如权利要求15所述的处理器，其特征在于，所述配置信息指示选择寄存器号的除最高有效位以外的所有位以及线程号的所有位。
18.如权利要求15所述的处理器，其特征在于，寄存器号的所选位形成线程有关的寄存器号。
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US20090182989A1 (en) 2009-07-16
CA2456541A1 (en) 2003-03-06
WO2003019358A1 (en) 2003-03-06
DE60223917D1 (de) 2008-01-17
KR20040014604A (ko) 2004-02-14
TWI315824B (en) 2009-10-11
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US7487505B2 (en) 2009-02-03
US20030041228A1 (en) 2003-02-27

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