CN1608249A - 多核心多线程处理器 - Google Patents

多核心多线程处理器 Download PDF

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CN1608249A
CN1608249A CNA028259432A CN02825943A CN1608249A CN 1608249 A CN1608249 A CN 1608249A CN A028259432 A CNA028259432 A CN A028259432A CN 02825943 A CN02825943 A CN 02825943A CN 1608249 A CN1608249 A CN 1608249A
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cores
server
thread
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CN1286019C (zh
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L·D·科恩
K·A·奥卢科顿
M·K·王
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Sun Microsystems Inc
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Abstract

在一个实施例中提供一种处理器。该处理器包括至少两个核心，其中每一个核心都包括一个一级高速缓存。每一个核心都被多线程。在另一个实施例中，每一个核心都包括四个线程。在另一个实施例中包括一个纵横开关。提供多个二级缓存区，通过纵横开关与该核心连通。多个缓存区存储器的每一个都与一个主存储器接口连通。在另一个实施例中还包括与多个缓存区存储器连通的一个缓存交换核心。还提供了用于优化一个多线程处理器核心的应用的服务器和方法。

Description

多核心多线程处理器
发明背景
1.发明领域
本发明涉及服务器，尤其涉及用于经过网络把数据供应到客户机的一种处理器结构和方法。
2.相关技术的描述
随互联网的引入而带来的网络蓬勃发展，具有用于服务多客户机的多线程的服务器应用量正在增加。电子商务创造了大企业服务于潜在的数百万消费者的需求。为了支持这种不可阻挡的需求，该服务应用具有的存储器特性不同于用于桌面应用的存储器特性。具体地说，该服务应用要求大的主存储器带宽并且具有相对差的缓存性能，以便适应大量的客户机。
此外，传统的处理器关注的是指令级提高性能的并行性。因此，处理器趋向于很大并且流水线很复杂。结果是，由于处理器，例如INTEL处理器流水线的复杂性，在冲模上仅有一个核心。因此，当出现缓存错过主存储器或某些其它长等待时间事件时，例如分支丢失预测时，通常出现拖延而引起流水线空载。结果是，具有大存储器覆盖区和不良缓存位置和分支可预测性的服务应用程序每线程将有很小的指令级并行性。因此，因为传统的处理器关注在指令级的并行性，所以利用服务器工作负荷的应用程序的传统的处理器的实施方案的特性将导致不良的硬件利用和不必要的功率耗散。
另外，基于指令级并行性的处理器的性能作为冲模尺寸的函数，其功率和复杂性达到了一个饱和点。图1的曲线描述了基于指令级并行性的传统处理器的性能与功率/尺寸之间的关系。如图1曲线100所示，由于该指令级并行性(ILP)结构的约束，增加传统处理器的功率和尺寸将不同时提供性能的线性增加。传统的ILP处理器包括公知处理器，如PENTIUMTM、ITANTUMTM、POWERTM、ULTRASPARCTM等家族。
由前述内容看来，需要一种具有更好地适合于服务应用程序的结构的处理器，其中该结构的构成来开发服务应用程序的多的线程特性。
发明概要
概括地说，本发明通过提供具有构成来高效处理服务器应用程序的一个结构的处理器而满足了这些需要。应该理解，本发明能够以很多方式实施，包含如一个设备、一个系统、一种装置或一个方法。下面描述本发明有创造性的几个实施例。
在一个实施例中提供一种处理器。该处理器包括至少两个核心，其中每一个核心都包括第一级高速缓存。每一个核心都被多线程。在另一个实施例中，每一个核心都包括四个线程。包括一个纵横开关。提供多个二级缓存区，通过纵横开关与该核心连通。多个二级缓存区存储器的每一个都与一个主存储器接口连通。还包括与多个缓存区存储器连通的一个缓存交换核心。
在另一个实施例中，提供一个服务器。该服务器包括一个应用程序处理器芯片。该应用程序处理器芯片包括多个多线程的中央处理单元核心。多个多线程的中央处理单元核心的每一个都包括一个一级高速缓存。该应用程序处理器芯片包括一个纵横开关和多个通过该纵横开关与该核心连通的缓存区存储器。多个二级缓存区存储器的每一个都与一个主存储器接口连通。该应用程序处理器芯片包括与多个缓存区存储器的每一个连通的一个缓存交换核心。
在另一实施例中，提供了用于优化一个多线程处理器核心的利用方法。该方法以通过一个第一线程操作接入一个处理器的操作开始。随后，在该第一线程操作已经完成接入该处理器核心之后，经过该第一线程执行一个长等待操作。随后中止该第一线程。随后，标识和选择准备接入该处理器核心的第二线程操作。在该背景下该第一线程执行该长等待时间操作的同时，通过该处理器核心处理该第二线程操作。
从下列结合附图的以实例的方式对本发明原理的详细描述中，本发明的其它方面和优点将变得显见。
附图描述
通过下面结合附图的详述描述将容易理解本发明，并且相同的参考数字表示相同的结构成分。
图1的曲线描述了基于指令级并行性的传统处理器的性能与功率/尺寸之间的关系。
图2是根据本发明一个实施例的服务器的高级简化示意图，利用具有基于线程等级并行性(TLP)的结构的一个处理器。
图3是根据本发明一个实施例的具有利用多线程的多个处理核心的处理器芯片的简化示意图，其中每一个核心都包括一级缓存和多核心共享的二级缓存。
图4是根据本发明一个实施例的具有8个多线程处理器核心的一个处理器芯片的更详细的示意图。
图5是根据本发明一个实施例的具有32个多线程处理器核心的一个处理器芯片的更详细的示意图。
图6是图5的处理器芯片的一种可选示意表示。
图7是根据本发明一个实施例的利用具有四个线程的一个处理器核心的流水线的图形表示。
图8是根据本发明一个实施例的按在一个线程中执行的流水线顺序用于单一发送的流水线级的简化示意图。
图9是根据本发明一个实施例的用于优化多线程处理器核心的利用的操作方法的流程图。
最佳实施例的详细描述
下面描述用于提高运行商业应用程序工作负荷的处理器的吞吐量和效率的设备和方法的一个发明。但是本专业技术人员显然知道本发明本发明可以在没有这些详细说明的某些或全部的条件下实践。在其它情况中，没有详细描述公知的处理操作，以便避免不必要地淡化本发明。其中使用的术语‘大约’是指对应值的+/-10％的范围。
在此描述的实施例具有在一个芯片上的多个简单的核心，其中每一个核心都具有其自己的一级缓存，并且该核心通过一个纵横开关而共享一个二级缓存。另外，每一核心都具有两个或多个线程。通过多线程，隐藏了由于存储器加载、缓存丢失、分支和其它长等待时间事件引起的等待时间。在一个实施例中，长等待时间指令使得一个线程被中止直到指令的结果被准备好为止。随即选择被保持准备好在该核心上运行线程的指令的结果，在随后的时钟上在该流水线中执行(不引入内容转换的额外开销)。在一个实施例中，一种编排算法在该准备好的指令当中选择，以便在每一个核心运行线程。因此，由于在该背景中执行该长等待时间事件并且该中央处理单元的使用由该多线程所优化，所以实现一种高吞吐量的结构。
图2是根据本发明一个实施例的服务器的高级简化示意图，利用具有基于线程等级并行性(TLP)的结构的一个处理器。服务器110包括处理器112，例如一种中央处理单元(CPU)。处理器112包括在一个芯片上的多个核心，其中多个核心的每一个都具有两个或多个线程，如下面将更详细地解释的那样。服务器110与例如互联网络114的一个分布式网络连通，使得服务器110能够连通1-n个客户机116a-116n。在一个实施例中，服务器110是用于一个商业应用程序的服务器，例如应用服务器应用程序、数据库应用程序等。
图3是根据本发明一个实施例的具有利用多线程的多个处理核心的处理器芯片的简化示意图，其中每一个核心都包括一级缓存和多核心共享的二级缓存。处理器芯片112包括处理器核心0至n，118-1至118-n。在一个实施例中，处理器芯片112包括8个处理器核心，但是应该理解，本发明不局限于8个处理器核心。处理器核心118-1至118-n的每一个都分别包括一级缓存124-1至124-n。每一核心都通过纵横开关120共享二级缓存122。纵横开关120使得能够在处理器核心118-1至118-n和二级缓存122之间沟通。在一个实施例中，纵横开关120被配置来适应在每一个时钟周期上进行的大量独立存取。
图4是根据本发明一个实施例的具有8个多线程处理器核心的一个处理器芯片的更详细的示意图。线程核心118-1至118-8的每一个都分别包括一级缓存124-1至124-8。一级缓存124-1包括指令缓存(I$)部分和数据缓存(D$)部分。负载/存储单元128-1包括在线程核心118-1之内。应该理解，处理器核心118-1至118-8的每一个都包括一个指令缓存、一个数据缓存和一个负载存储单元。在另一个实施例中，每一处理器核心都基于本发明受让人的PARC V9结构。处理器核心118-1至118-8的每一个都与纵横开关120连通。针对处理器的业务量优化纵横开关120，其中期望获得很低的等待时间。2级(L2)缓存区122-1至122-4由处理器核心118-1至118-8共享。应该理解，通过共享L2缓存区122-1至122-4，实现同时对多个区的并行存取，从而限定一个高带宽的存储系统。在一个实施例中，每一个L2缓存区具有大约1兆字节(MM)的大小。应该理解，虽然图4示出了四个L2缓存区122-1至122-4，但是本发明不局限于四个L2缓存区。即，L2缓存区的数量足以提供来自L2缓存充足带宽，以便保持大部分情况下的所有的核心的占用。在一个实施例中，每一个处理器核心包括4个线程。因此，具有八个核心的单个处理器芯片将在此结构中具有32个线程。L2缓存区122-1至122-4的每一个都与主存储器接口126-1至126-4连通，以便提供对主存储器的接入。应该理解，由于图4是示例性的而不是限制，所以虽然在处理器芯片上描述了8个核心，但是能够包括更多或更少的核心。对本专业技术人员显见的是，由该互连结构，即纵横开关120和缓冲交换核心130提供的功能可以通过适于在缓存区122-1至122-4、处理核心118-1至118-8和I/O装置132-1至132-n之间处理信号的等效的并且在本专业公知的结构来提供。
仍然参考图4，缓存器交换核心(BSC)130是一个被优化来对该主存储器提供用于I/O直接存储器存取(DMA)事务处理的最大带宽的一个单元。在一个实施例中，由于不同的I/O装置和与BSC 130连通的I/O接口，BSC 130的转换结构可以起到一个DMA业务开关的作用，用于控制若干端口。在另一个实施例中，BSC 130实现执行存储器排队。BSC 130包括配置用于把各种不同I/O接口通过I/O端口连通并且缓冲由I/O装置产生的DMA业务的电路。缓存的信号被排队，然后发送到L2缓存区122-1至122-4中。反过来，L2缓存区122-1至122-4保持着在L2缓存区中的数据和在主存储器中的对应数据之间的连贯性。
在一个实施例中，包括图4的BCS 130 L2缓存区122-1至122-4和主存储器接口126-1至126-4的通道被用于执行在I/O装置132-1至132-n以及主存储器之间的直接存储器存取(DMA)。为了控制对该I/O装置的寄存器访问，在纵横开关120上的一个附加端口与I/O桥接器134连通，I/O桥接器134又与I/O装置132-1至132-n连通。因此，处理器核心118-1至118-8实现对I/O装置132-1至132-n的任何之一中的寄存器的直接存取而不通过存储器。例如，处理器核心118-1至118-8之一可以发送一个加载指令到纵横开关120。然后纵横开关120把该信号发送到I/O桥接器134，而不是L2缓存区122-1至122-4。然后I/O桥接器134产生对应于I/O装置132-1至132-n的一个事务处理，以便获得必要的数据。一旦数据已经由I/O桥接器134接收，则该数据被发送回到纵横开关120，并且随后发送到分别的处理器核心118-1至118-8。因此，处理器核心118-1至118-8的任何之一、或处理器核心的任意线程都能够访问I/O装置132-1至132-n，同时旁路L2缓存区122-1至122-4，以便编程该I/O装置用于DMA传送。对本专业技术人员显见的是，在执行DMA传送之前，某些参数必须被设置在I/O装置132-1至132-n中。在I/O装置132-1至132-n中设置的参数示例包括传输长度、传送地址和传送数目等。在一个实施例中，I/O桥接器134处理控制信号，例如指令建立控制信号和读出一个状态。因此，在I/O装置132-1至132-n、I/O桥接器134和纵横开关120之间的通道定义了一个控制路径。在纵横开关120、缓存区122-1至122-4、BSC130和主存储器接口126-1至126-4之间定义的通道限定了一个数据通道。
图5是根据本发明一个实施例的具有32个多线程处理器核心的一个处理器芯片的更详细的示意图。其中，在处理器芯片140上提供了4组处理器核心118a1-118a8、118b1-118b8、118c1-118c8、和118d1-118d8。四组的每一个都包括8个核心。在一个实施例中，每一个处理器核心都包括四个线程，因此在本实施例中的处理器芯片140包括线程的总数为128。当然，每一处理器能够包括更多或更少的线程，并且在该处理器芯片上能够包括更多或更少的处理器核心。如上参照图4所述，针对处理器核心的每一组的数据通道通过纵横开关120、分别的L2缓存区122a1-122a4、122b1-122b4、122c1-122c4和122d1-122d4、缓冲交换核心(BSC)130以及分别的主存储器接口126a1-126a4、126b1-126b4、126c1-126c4和126d1-126d4来定义。应该理解，由于说明的局限性该BSC130被示出了四次。即，其中单一BSC 130把全部的I/O装置132a1-132an、132b1-132bn、132c1-132cn和132d1-132dn连接到二级缓存区122a1-122a4、122b1-122b4、122c1-122c4和122d1-122d4的每一个。同样，针对每一处理器核心组的控制通道通过纵横开关120、I/O桥接器134、以及分别的I/O装置132a1-132an、132b1-132bn、132c1-132cn和132d1-132dn定义。如将在下面更详细地解释的那样，通过使用按顺序执行的单一发出流水线而针对每一处理器核心来优化功率和冲模尺寸比性能的折衷。因此，通过提供具有多线程的多个简单核心来增加该性能，其中线程等级并行性结合一个简化的流水线，使得该处理器芯片能够安装在一个更小的冲模上，消耗比基于指令级并行性的一个传统处理器更少的功率。
图6是图5的处理器芯片的一种可选示意表示。其中，纵横开关120与数据通道144a-144d、BSC 130和L2缓存区122连通。应该理解，由于以二维示出此结构的限制，仅示出两组缓存区122。提供另外两个没示出的缓存区，使得数据通道144a-144d的每一个都与一个缓存区相关。以太网接口142a和142b提供了对于分布式网络的接入。在一个实施例中，以太网接口142a和142b是吉比特以太网接口。一级高速缓存146a-146d被提供用于每一个处理器核心与数据通道144a-144d的关联。
图7是根据本发明一个实施例的针对具有四个线程的一个处理器核心的高吞吐量结构的图形表示。线程0使用中央处理单元(CPU)然后在存储器中启动。例如，一个长等待时间事件可能使得该线程在存储器中启动。在线程0在存储器中启动的同时，线程1接入CPU，用于线程3和4的每一个。应该理解，在存储器中的启动的线程的操作是在该背景中执行的。而且，由于在此描述的存储系统是一个并行存储器系统，所以能够同时出现多个基准。因此，以一种交错技术按核心优化CPU的使用。流水线复杂性较低，即单一发出流水线而没有指令级并行性，并且能够在与传统指令级并行流水线相同的区域被复制若干次。本质上，该流水线重叠该多线程的执行来最大化CPU流水线的利用。
图8是根据本发明一个实施例的按在一个线程中执行的流水线顺序用于单一发送的流水线级的简化示意图。流水线的第一级是取指令，其中获得一个指令。流水线的第二级是解码级，也称作一个寄存器取出级，其中解码指令操作码、运算信源/目的地以及控制信号。第三级是切换级，选择一个线程以便发送到属于是该流水线的第四级的该执行级，在每一个时钟周期执行。应该理解，如上所述该处理器核心具有四个线程，四个硬件线程被提供用于级1-3。在一个实施例中，针对在级4中的负载和存储指令计算有效地址。在另一个实施例中，贯穿全部级1-6，以任何一个级处理一个指令，即该流水线属于是单一发出流水线，与传统的ILP处理器相反，其中在对应的级可能存在一个以上的指令。级5是寄存器误码校正级，而级6是写回级，其中一个具体线程的结果被写到一个寄存器文件。
图9是根据本发明一个实施例的用于优化多线程处理器核心的利用的操作方法的流程图。该方法以操作160启始，其中通过一个第一线程操作接入一个处理器。应该理解，该处理器核心是一个多线程核心，具有如上所述的至少两个线程。该方法随后进到操作162，其中在该第一线程操作已经完全接入该处理器核心之后，执行一个长等待时间操作。例如，该线程可被按照参照图7讨论的那样被启动。该长等待时间操作包括一个缓存丢失、一个分支和一个浮点操作。然后该方法进到操作164，中止该第一线程。如参考图7提到的那样，在该背景中正在运行存储器中同时启动的第一线程。该方法随后进入操作166，其中标识准备好接入该处理器核心的一个第二线程操作。如参考图8提到的那样，在该流水线的交换级标识和选择该第二线程操作。在一个实施例中，一种编排算法被用于选择该第二线程。该方法随后进到操作168，其中通过处理器核心处理该第二线程操作，同时在该背景中执行与该第一线程相关的长等待时间操作，例如在存储器中的启动。当然，可从第二线程发送多个指令，直到该第一线程的长等待时间指令结束为止。因此，多个线程被重叠以便最大化流水线使用。
总之，上述实施例提供了在一个芯片上的多个核心，其中每一个核心都至少具有两个线程。该多线程的多个核心限定一个高吞吐量结构，构成来高效支持能够服务若干客户的一个服务器应用程序。另外，该结构开发一个服务器应用程序的多个线程。在一个实施例中，由于该线程级并行性以及该简化的流水线，即单一发出流水线，简化了该处理器的结构。
而且本发明可以利用其它计算机系统结构实践，包括手持装置、微处理机系统、以微处理机为基础或可编程的消费电子装置、小型计算机、大型计算机等。本发明还可以在分布式计算环境中实践，其中通过经贯穿一个络链接的远程处理装置执行任务。
考虑上述的实施例，应该理解，本发明可以采用包括存储在计算机系统中的数据的各种计算机执行的操作。这些操作是物理量所需要的物理操作。尽管不是必须，但这些量通常采用的是能够由存储、传输、组合、比较以及其它操作所处理得电或磁信号的形式。而且，执行的操作时常称之为例如产生、标识、确定或比较。
在此描述的形成本发明一部分的任何操作都是有用的机器操作。本发明还涉及用于执行这些操作的装置或设备。该设备可以是用于需要用途的专门构成的设备，或可以是一个通用计算机，由存储在该计算机中的一个计算机程序有选择地启动或配置。具体地说，利用根据在此指教的计算机程序的写入而可以使用各种常规用途的计算机，或可以更方便地构成一个多专用设备来执行需要的操作。
虽然为了清晰理解的目的已经相当详细地描述了上述发明，但是在所附的权利要求书的范围之内显见将有某些改变和改进可以实践。因此，该本实施例被认为被说明性的而不是限制性的，并且本发明将并不局限于其中给出的细节，而是可以在所附的权利要求书的等效范围之内修改。

Claims (20)

1.一种处理器，包括：
至少两个核心，该至少两个核心的每一个都具有一级高速缓存，该至少两个核心的每一个都是多线程的核心；
一个互连结构；
通过该互连结构与该至少两个核心连通的多个缓存区存储器，多个缓存区内存的每一个都与一个主存储器接口连通。
2.权利要求1的处理器，其中该互连结构包括与多个缓存区存储器和至少两个核心连通的一个纵横开关，以及与多个缓存区存储器的每一个连通的一个缓存器交换核心。
3.权利要求2的处理器，进一步包括：
与该纵横开关和一个输入输出设备连通的一个输入/输出桥接器，该输入/输出桥接器实现控制寄存器与该输入/输出装置的传送。
4.权利要求2的处理器，其中该缓存器交换核心实现直接存储器存取。
5.权利要求1的处理器，其中该一级高速缓存包括一个指令缓存单元和一个数据缓存单元。
6.权利要求1的处理器，其中与该至少两个核心相关的每一个线程被构成在一个流水线上运行。
7.权利要求5的处理器，其中该流水线是单一发出流水线。
8.权利要求1的处理器，其中该缓存区存储器是单一端口的静态随机存取存储器。
9.一种服务器，包括：
一个应用程序处理器芯片，该应用程序处理器芯片包括：
多个多线程的中央处理单元核心，该多个多线程的中央处理单元核心的每一个都具有一个一级高速缓存；
一个互连结构；
通过该互连结构与该至少两个核心连通的多个缓存区存储器，多个缓存区内存的每一个都与一个主存储器接口连通。
10.权利要求9的服务器，其中该互连结构包括与多个缓存区存储器和多个多线程的中央处理单元核心的每一个连通的一个纵横开关，以及与多个缓存区存储器的每一个连通的一个缓存器交换核心。
11.权利要求9的服务器，其中该服务器是从包括Web服务器、应用服务器和数据库服务器的组中所选的服务器。
12.权利要求10的服务器，其中该应用程序处理器芯片包括：与纵横开关和输入输出设备连通的一个输入/输出桥接器，该输入/输出桥接器实现控制寄存器与该输入/输出设备的传送。
13.权利要求9的服务器，其中该一级高速缓存包括一个指令缓存单元和一个数据缓存单元。
14.权利要求9的服务器，该中央处理单元核心的每一个线程被构成来在单一发出流水线上运行。
15.用于优化一个多线程处理器核心的应用的方法，包括步骤：
通过一个第一线程操作接入一个处理器核心；
通过该第一线程发出一个长等待时间操作；
中止该第一线程；
标识一个第二线程操作准备好接入该处理器核心；和
通过该处理器核心处理该第二线程操作，同时该第一线程执行在该背景中的长等待时间操作。
16.权利要求15的方法，其中标识一个第二线程操作准备好接入该处理器核心的方法操作包括步骤：
根据一个编排算法选择该第二线程操作。
17.权利要求15的方法，其中核心包括四个线程。
18.权利要求15的方法，进一步包括步骤：
提供具有八个处理器核心的一个集成电路芯片，其中每一个处理器核心都包括四个线程。
19.权利要求15的方法，其中中止该第一线程的方法操作包括步骤；
从该长等待时间操作获得一个结果；和
在从该长等待时间操作获得该结果之后，指示该第一线程已准备好在该处理器核心上运行。
20.权利要求15的方法，其中该多线程处理器核心的每一个线程被配置为使用按顺序执行的单一发出流水线。
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