CN1613041A - 时钟分配系统 - Google Patents

时钟分配系统 Download PDF

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CN1613041A
CN1613041A CNA02808148XA CN02808148A CN1613041A CN 1613041 A CN1613041 A CN 1613041A CN A02808148X A CNA02808148X A CN A02808148XA CN 02808148 A CN02808148 A CN 02808148A CN 1613041 A CN1613041 A CN 1613041A
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functional block
clock
delay
time
bus node
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I·斯瓦布里克
D·威廉斯
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ClearSpeed Technology PLC
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/742—Route cache; Operation thereof

Abstract

一种用于集成电路的时钟分配系统，它包括通过通信总线(12)连接的多个区域(1、2、3)。每一个区域包括功能块(10a、10b、10c)以及用于将相应的功能块与通信总线(12)连接的至少一个总线节点(14a、14b、14c)。允许分配的时钟信号(16)在区域之间时滞、但在各个区域范围内同步。将预定时钟插入延时(20a、20b、20c、22a、22b、22c)插入每一个功能块和总线节点。

Description

时钟分配系统
发明领域
本发明涉及时钟分配系统，具体地说，涉及用于集成电路的时钟分配系统。
发明背景
集成电路需要计时方案，以便执行指令以及以同步方式在集成电路上的功能块之间传递数据。传统的集成电路目的是让时钟信号同时到达每个电路元件或模块、使得这些电路元件同步工作。因此，通常这样设计集成电路、以便从中心定位时钟基准开始以对称方式在整个芯片上分配时钟信号。
尽管与先有技术的时钟分配方案相关的对称性，但电路导体中的缺陷以及引入制造工艺过程的变化产生电路元件或模块之间的时钟时滞。
设计集成电路的现有开发工具具有自动化处理过程，用于在芯片上这样分配平衡时钟、使得芯片上的每一个功能单元同步工作。用于平衡时钟的自动化处理过程包括两级过程。首先，把时钟树插入每一个功能块。每一块具有不同的插入延时。一旦在布局平面布置图上设置了各功能块，则第二级过程包含平衡时钟树，以便将时钟时滞减少到可接受的限度。这个过程包含将附加缓冲器插入每一条路径，以便在芯片上每一个寄存器的所有时钟输入端平衡时滞。采用这种技术，时钟树可以被平衡到200-300ps范围内。
上述传统工艺具有许多缺陷。例如，虽然将缓冲器插入功能单元的每一条路径的任务是相对自动化的，但第二级过程要求更多的人工干预，也就是说，必须指示这些工具要插入附加时钟缓冲器的位置。这个过程耗费时间，并且难以确定时钟时滞是否处于可接受的允许限度之内。提高时钟频率这一始终如一的愿望意味着上述问题更加密切相关。因此难以在合理的时帧中模拟大型集成电路。
上述平衡时钟树是同步设计方法学的标准组成部分。但是，这种技术的另一个缺点在于：整个芯片上的所有寄存器均借助于时钟脉冲边沿的到达来更新，在流过芯片的电流中产生大尖峰信号。这种电流浪涌在许多方面都是不希望有的。例如，电流浪涌会引起不希望有的电磁发射，并且还会因电迁移故障而导致可靠性问题。
另一个缺点在于：印刷线的尺寸大小必需比处理大电流浪涌所需的大。另外，必需保留未用的硅面积、以便能够插入顶层时钟驱动器。
本发明的目的是提供一种用于集成电路的时钟分配系统，它容许时钟时滞并且简化设计大规模集成电路的过程。
发明概述
根据本发明的第一方面，提供一种用于集成电路的时钟分配系统，所述集成电路包括通过通信总线连接的多个区域，每一个区域包括功能块和用于将功能块连接到通信总线的至少一个总线节点，其特征在于：允许分配的时钟信号在区域之间时滞；以及所述时钟信号在各个区域中同步。
所述时钟信号最好被分配给每一个功能块和总线节点，以及把预定的时钟插入延时插入每一个功能块和总线节点。
根据本发明的第二方面，提供一种将时钟信号分配给集成电路上通过总线连接的多个区域的方法，每一个区域包括功能块和至少一个总线节点，所述方法包括以下步骤：允许时钟在集成电路上的各区域之间时滞；以及使集成电路上各个区域中的时钟同步。
根据本发明的第三方面，提供一种集成电路，它包括：多个区域；总线，用于连接所述多个区域；时钟分配网络，它配置成为时钟信号选择到达所述多个区域的路由；其特征在于：所述时钟网络配置成以同步方式为各个区域中的时钟信号选择路由；以及在各个区域之间以时滞方式为时钟信号选择路由。
根据本发明的第四方面，提供一种降低集成电路中的峰值电流的方法，所述方法包括以下步骤：将集成电路分为多个功能块；向各个功能块这样分配时钟信号、使得至少两个功能块采用彼此时滞的时钟信号进行工作、从而降低集成电路中的峰值功率。
根据本发明的第五方面，提供一种设计集成电路的方法，所述方法包括以下步骤：将集成电路分为多个区域，每一个区域具有功能块和至少一个总线节点；利用通信总线连接这些区域；沿通信总线向各个功能块分配时钟信号；以及把预定的时钟插入延时赋予每一个功能块和总线节点。
附图简述
图1A和1B说明与时钟时滞相关的问题；
图2说明由时钟时滞引起的可能的保持时间破坏；
图3说明补偿时钟时滞的传统方法；
图4说明根据本发明的第一实施例的时钟分配系统；
图5说明根据本发明的第二实施例的时钟分配系统；
图6说明图5所示第二实施例中时钟信号之间的相位关系；
图7说明图5所示第二实施例的时钟桥的实例；
图8说明根据本发明的第三实施例的时钟分配系统。
本发明的最佳实施例的详细说明
图1A和1B说明与集成电路中时钟时滞相关的问题之一的一个实例。当时钟信号1按照与数据信号3相同的方向传播时，如图1A所示，它引起正时滞，并会导致保持时间问题。当时钟信号1按照与数据信号3相反的方向传播时，如图1B所示，它引起负时滞。虽然不存在与负时滞相关的保持时间问题，但其缺点是减小有效的时钟周期。
因此就存在一种危险，当数据按照与时钟信号相同的方向传播时，就存在数据可能按时到达下一个寄存器而引起保持破坏。为了消除这个危险，传统技术旨在确保寄存器之间有足够的逻辑延时，以避免这个问题。
图2详细说明这个问题。数据按照与沿着其分配时钟的方向相同的方向传播。对于工作的电路：
Tclk→Q+tlogic-thold≥tskew
对于可靠工作，tskew的最坏条件(即最大)值以及“最快”条件下的Tclk→Q和tlogic的值必须是已知的。应当使用thold的最大值。
这个方法假定时钟时滞仅仅是容许的，由逻辑延时屏蔽。为了处理分配给相同功能块中的不同寄存器的时钟信号之间的时滞，通常向逻辑合成软件提供时钟不定性数值。然后，设计工具再查找可能的保持时间破坏，并确定有足够的逻辑延时来防止其发生。
虽然这种技术对于功能块内时钟分配是可容许的，但必需插入大量的逻辑以容许大时滞。解决这个问题的一个已知方法是采用半锁存器，如图3所示。当时钟A的正沿出现时，锁存器闭合(即不导通)。这避免数据超过时钟信号，引起保持破坏。这种技术可用来掩盖时滞的一半时钟周期。
图4说明根据本发明的第一方面的时钟分配系统。多个功能块10a、10b、10c通过通信总线12互相连接。总线最好是一种管道总线。应当指出，术语“功能块”用来表示虚拟处理块、例如多个可再用芯片内功能块或虚拟组件块之一。功能块有时称作“芯片内系统”块。各功能块10a、10b、10c由相应总线节点14a、14b、14c连接到通信总线12。功能块10a、10b、10c经总线节点14a、14b、14c以及通信总线12相互通信。总线节点14a、14b、14c作为功能块10a、10b、10c与总线12之间的接口，并涉及例如对地址解码和协议翻译的处理。
根据本发明，时钟信号16最好沿通信总线12连接到各种功能块10a、10b、10c，允许时钟信号16在功能块之间传播时时滞。图4中由延时元件18示意表示时滞。
每一个功能块10a、10b、10c分别配备有时钟插入延时20a、20b、20c。同样，每一个总线节点14a、14b、14c也配备有时钟插入延时22a、22b、22c。为功能块10a的时钟插入延时20a分配一个值，所述值基本上等于总线节点14a的时钟插入延时22a。例如，如果相邻功能块10a和10b之间的时滞已知为小于300ps，则可选择3.4ns的延时作为功能块10a和总线节点14a的时钟插入延时。这意味着功能块10a与其相应的总线节点14a同步。
同样，为功能块10b的时钟插入延时20b分配一个基本上等于总线节点14b的时钟插入延时22b的时钟插入延时。为功能块10c的时钟插入延时20c分配一个基本上等于总线节点14c的时钟插入延时22c的时钟插入延时。
最好为功能块10a、10b、10c的时钟插入延时20a、20b、20c以及总线节点14a、14b、14c的时钟插入延时22a、22b、22c分配相同的时钟插入延时。
另一个备选方案是，鉴于为每一个功能块及相关的总线节点分配相同的时钟插入延时，可以为单独的功能块及其相关的总线节点分配一个时钟插入延时，所述时钟插入延时是时钟周期的倍数加上所述插入延时。例如，如果块周期是2.5ns，且功能块10a的插入延时为3.4ns，则可为其它块的时钟插入延时分配以下时钟插入延时：
N×2.5ns+3.4ns
其中N是大于或等于零的正整数。
换句话说，只要使其它节点上的时钟边沿同步到第一功能块上的时钟边沿的可接受限度之内，则可以利用用于对第一功能块计时的时钟信号的若干时钟周期下游的实时时钟信号来对其它节点进行定时。总线节点相对于其相邻节点时滞一定数量、例如少于300ps(用于使信号传播大约1mm所需的时间)。应当指出，就第二对节点之间的时滞而论，第一对节点之间的时滞可以变化。对于总线节点之间的所有信号，通过将时钟不定性设置为大于例如300ps，来处理时滞。这样，虽然功能块10c上的时钟相对于功能块10a上的时钟时滞600ps，但如果将时钟不定性设置为大于300ps，则它并不影响电路的运行，因为每一个功能块10a和10c与其自身的总线节点14a、14c同步。设置时钟不定性涉及为合成工具提供信息，使它能够计算两个时钟边沿之间的最坏情况下的定时关系，其中适当的定时用来指导逻辑合成，以便不违反设置及保持时间。
图5说明根据本发明的第二方面的时钟分配系统的一个实例。尽管图4中的功能块10a、10b、10c较小、使得每个功能块只需要一个总线节点14a、14b、14c，但图5所示电路表示较大的功能块30，后者具有经由多个总线节点33a、33b、33c到达通信总线的多个接口。
如上所述，最好沿总线12把时钟信号16分配给功能块30以及每一个总线节点33a、33b、33c。为功能块30分配时钟插入延时39，后者基本上等于分配给总线节点33a的时钟插入延时37a。最好为总线节点33b、33c的时钟插入延时37b、37c分配与总线节点33a相同的时钟插入延时值。另一个备选方案是，时钟插入延时37b、37c可以是时钟周期的倍数加上时钟插入延时37a，如以上结合图4所述。
由于功能块30大于图4所示的功能块10a，因此时钟插入延时必需相应地增加。例如，假定总线节点33a/33b和33b/33c之间的时滞小于300ps，则可以把5.9ns的时钟插入延时分配给每一个时钟插入延时装置39、37a、37b以及37c。或者，时钟插入延时37b和37c可以是时钟周期的倍数。较大功能块(例如功能块30)的最小可能插入延时会高于总线节点的插入延时，因此所选插入延时数值必须大到足以适应系统中的最大功能块。
功能块30和相应的总线节点33b、33c之间的通信将会不同相。图6中示出每一块中时钟之间的相位关系。
参考图6，可以看到，总线节点33a与功能块30同步，因为两个元件都具有相同的插入延时。为了允许多个总线节点33a、33b、33c与同一个功能块30连接，分别为与功能块30不同步的总线节点33b、33c提供时钟桥35b、35c。时钟桥35b、35c最好是标准块，在需要它们的情况下均可插入到电路设计中。
图7说明实现时钟桥35b、35c的方式的实例。所示的时钟桥是双向的，为简洁起见，在每一个方向上给出一位数据通路。大家知道，同样的方法适用于更广泛的数据通路。本例中，时钟时滞600ps，但这个值可以更大，只要小于时钟周期的一半(具有一定的安全性余量)。当功能块30上的时钟为高电平时，相邻锁存器41关闭，防止数据D“贯通”。数据以相反方向(从滞后于时钟到超前于时钟)传播时不需要锁存器43，但最好包含这个元件，使所述单元对称。这意味着时钟桥反接时仍然会进行工作。同样，来自总线节点33b的时钟信号连接到锁存器47、49及51。当来自总线节点33b的时钟信号为高电平时，锁存器51不传导，从而防止数据“贯通”。锁存器41、43、47、49的引入防止设计工具流程、诸如形式验证中的问题。采用锁存器时，难以了解设计人员的意图。在时钟桥的情况下，它是一种能够被仔细检验然后用于整个芯片上的元件。
或者，可以使用逻辑门来建立所需的延时。但是，这种方法的缺点是消耗更多功率且使用集成电路上的更大面积。
目前提出的解决方案允许多个总线节点与一个功能块连接。图5所示的实例说明功能块30中的时钟与第一总线节点33a的时钟匹配。另一个备选方案是，功能块30中的时钟能够与最接近功能块30的中心的总线节点、即图5所示实例中的节点33b匹配。它的优点是增加容许的总时滞量。
根据本发明的第二方面的上述时钟分配系统具有能够被容许的时滞量的极限。例如，对于很大的功能块(例如接口之间大于6-8mm)，难以管理时钟时滞。此外，增加时钟桥35b和35c增加了总线接口上的时钟等待时间的周期。
图8说明根据本发明的第三方面的时钟分配系统的实例。允许时钟在第一区域、即功能块50a、50c以及总线节点53a所在的集成电路的部分中时滞。功能块50a具有5.8ns的插入延时，与其相应的总线节点53a的插入延时51匹配(就是说，也具有5.8ns的插入延时)。同样，功能块50c具有5.8ns的插入延时，与其相应的总线节点53e的插入延时匹配。
本实施例在总线节点53c/53d和功能块50b之间不是采用时钟桥，而是采用顶层插入来平衡属于功能块50b的总线节点53b、53c、53d。例如，如果功能块50b具有5.8ns的插入延时57，则总线节点53b、53c、53d被安排成具有3.3ns的插入延时(表示为55b、55c、55d)。借助于提供2.5ns插入延时的缓冲器65的顶层插入延时，来实现各总线节点53b、53c、53d和功能块50b之间的同步。缓冲器65的2.5ns延时与各总线节点53b、53c、53d中的3.3ns的插入延时结合，来实现5.8ns的有效插入延时，即对应于功能块30b。应当指出，在上述实例中，缓冲器65的时钟插入延时与时钟周期、即2.5ns匹配。这样，当总线节点55d与节点55e通话时，它们之间的差值则为相对时钟时滞，(相比之下最接近的时钟边沿而不是绝对时钟边沿)。
因此，集成电路的这个区域中的时钟分配系统采用传统的“树”法。时钟沿总线传播时，仍然允许它时滞，直至到达大功能块50b。连接到功能块50b的总线节点53b、53c、53d具有平衡时钟(低于100ps)。从所述段下行分配的时钟信号则被允许再次开始时滞。根据本实施例，在连接到功能块50b的总线节点中需要保留空间，以便允许留出平衡进入功能块50b的时钟和进入总线节点的时钟的时钟缓冲器的空间。
根据本发明的第三方面，电路保持上述改进的时钟分配系统的大部分优点，其表现在于：大部分时钟插入预先进行，同时对于极大功能块、即太大而不能采用时滞法的功能块，只需要“后端”的最少的平衡。本实施例的优点是允许时钟拖影、使得峰值功率降低，但却没有时钟桥带来的等待时间开销。
下面将指出，集成电路可以具有以上公开的方案的任何组合。例如，一个区域可以具有分配给每个功能块的一个总线节点，而另一个区域则具有分配给每个功能块的多个总线节点。此外，当多个总线节点分配给每个功能块时，系统可在使用图5所示的“时钟桥”方法、图8所示的“平衡树”方法或者同一集成电路上的两种系统组合之间进行选择。
上述实施例实现以减小的顶层计时结构来研制集成电路。总线节点和功能块包含所需元件来分配时钟信号，允许总线节点和功能块以简单方式连接在一起，同时时钟桥提供所需接口。通过在顶层时钟结构的电路设计中提供空间来处理较大功能块，但这是远小于平衡整个芯片上的时钟的开销。
如上所述，本发明的优点是容许时钟时滞而不是尝试将其消除。这使芯片上的不同寄存器具有不同的时钟边沿，从而使通常产生的大电流峰值平滑。因此，功率分配更简便，使印刷线大小缩小。另外，通过金属印刷线的减小的电流密度会改善可靠性，尤其是对于电迁移故障。
时钟分配系统的另一个优点是再用性。相同的布局可在多个芯片上再用，只要它们具有相同的时钟频率并使用插入延时的相同规则。
应当指出，虽然最佳实施例表明，功能节点的时钟插入延时选择为基本上等于其相应的总线节点的时钟插入延时，但也可以按照以上对于各种功能块所述的方式进偏移这些时钟插入延时，即时钟插入延时偏离第一时钟插入延时+/-N个时钟周期再加上所述时钟插入延时，其中N为零或正整数。

Claims (41)

1.一种用于集成电路的时钟分配系统，它包括通过通信总线连接的多个区域，每一个区域包括功能块和用于将所述功能块连接到所述通信总线的至少一个总线节点，其特征在于：允许分配的时钟信号在区域之间时滞；以及所述时钟信号在各个区域范围内同步。
2.如权利要求1中所述的时钟分配系统，其特征在于：把所述时钟信号分配给每一个功能块和总线节点；以及把预定的时钟插入延时插入每一个功能块和总线节点。
3.如权利要求1或2所述的时钟分配系统，其特征在于：至少一个区域具有连接到功能块的两个或两个以上的总线节点，第一个所述总线节点直接连接到所述功能块、而其余所述总线节点经延时装置连接到所述功能块。
4.如权利要求3所述的时钟分配系统，其特征在于：所述延时装置包括设置在所述各个总线节点和功能块之间的时钟桥。
5.如权利要求4所述的时钟分配系统，其特征在于：所述时钟桥构成所述功能块的一部分。
6.如权利要求3至5中任何一项所述的时钟分配系统，其特征在于：所述第一总线节点连接到所述功能块的中央部分。
7.如权利要求2至6中任何一项所述的时钟分配系统，其特征在于：每一个功能块和总线节点的所述时钟插入延时基本上相等。
8.如权利要求2至6中任何一项所述的时钟分配系统，其特征在于：一个功能块或总线节点的所述时钟插入延时按照预定量偏离另一个功能块或总线节点的所述时钟插入延时。
9.如权利要求8中所述的时钟分配系统，其特征在于：所述预定量与所述时钟插入延时加上或减去N个时钟周期有关，其中N为零或正整数。
10.如以上权利要求中任何一项所述的时钟分配系统，其特征在于：根据连接到所述通信总线的所述最大功能块的大小来选择所述时钟插入延时。
11.如以上权利要求中任何一项所述的时钟分配系统，其特征在于：所述区域中至少一个具有连接到功能块(50b)的两个或两个以上总线节点(53b、53c、53d)，每一个所述总线节点(53b、53c、53d)具有基本上相等的时钟插入延时(55b、55c、55d)，所述总线节点的所述时钟插入延时(55b、55c、55d)不同于所述功能块(50b)的所述时钟插入延时(57)；以及为所述区域中的所述时钟信号选择经延时缓冲器(65)到达每一个所述总线节点(53b、53c、53d)的路由。
12.如权利要求11所述的时钟分配系统，其特征在于：所述功能块(50b)的所述时钟插入延时基本上等于由所述延时缓冲器(65)提供的所述延时与由各个总线节点提供的所述时钟插入延时(55b、55c、55d)之和。
13.如以上权利要求中任何一项所述的时钟分配系统，其特征在于：所述时钟信号沿所述通信总线分配给每一个功能块和总线节点。
14.一种把时钟信号分配给集成电路上的多个区域的方法，所述区域通过总线连接，每一个区域包括功能块和至少一个总线节点，所述方法包括以下步骤：
允许所述时钟在所述集成电路上的各区域之间时滞；以及
使所述时钟在所述集成电路上的各个区域范围内同步。
15.如权利要求14所述的方法，其特征在于：把所述时钟信号分配给每一个功能块和总线节点；以及所述方法还包括在每一个功能块和总线节点中插入预定的时钟插入延时的步骤。
16.如权利要求14或15所述的方法，其特征在于还包括以下步骤：
将两个或两个以上总线节点连接到至少一个区域中的功能块；以及
这样设置所述区域中的所述总线节点、使得第一个所述总线节点直接连接到所述功能块而其余所述总线节点经延时装置连接到所述功能块。
17.如权利要求16所述的方法，其特征在于：所述延时装置包括设置在所述各个总线节点和功能块之间的时钟桥。
18.如权利要求17所述的方法，其特征在于：所述时钟桥构成所述功能块的一部分。
19.如权利要求16至18中任何一项所述的方法，其特征在于：所述第一总线节点连接到所述功能块的中央部分。
20.如权利要求15至19中任何一项所述的方法，其特征在于：每一个功能块和总线节点的所述时钟插入延时基本上相等。
21.如权利要求15至19中任何一项所述的方法，其特征在于：一个功能块或总线节点的所述时钟插入延时按照预定量偏离另一个功能块或总线节点的所述时钟插入延时。
22.如权利要求21所述的方法，其特征在于：所述预定量与所述时钟插入延时加上或减去N个时钟周期有关，其中N为零或正整数。
23.如权利要求14至22中任何一项所述的方法，其特征在于：根据连接到所述通信总线的所述最大功能块的大小来选择所述时钟插入延时。
24.如权利要求14至23中任何一项所述的方法，其特征在于还包括以下步骤：
将两个或两个以上总线节点(53b、53c、53d)连接到至少一个区域中的功能块(50b)，每一个所述总线节点(53b、53c、53d)具有基本上相等的时钟插入延时(55b、55c、55d)，所述总线节点的所述时钟插入延时(55b、55c、55d)不同于所述功能块(50b)的所述时钟插入延时(57)；以及
为所述区域中的所述时钟信号选择经延时缓冲器(65)到达每一个所述总线节点(53b、53c、53d)的路由。
25.如权利要求24所述的方法，其特征在于：所述功能块(50b)的所述时钟插入延时基本上等于由所述延时缓冲器(65)提供的所述延时与由各个总线节点提供的所述时钟插入延时(55b、55c、55d)之和。
26.如权利要求14至25中任何一项所述的方法，其特征在于：所述时钟信号沿所述通信总线分配给每一个功能块和总线节点。
27.一种集成电路，它包括：
多个区域；
用于连接所述多个区域的总线；
时钟分配网络，它配置成为时钟信号选择到达所述多个区域的路由；
其特征在于：所述时钟分配网络配置成在各个区域中以同步方式为所述时钟信号选择路由、而在各个区域之间以时滞方式为所述时钟信号选择路由。
28.如权利要求27所述的集成电路，其特征在于：每一个区域包括功能块和至少一个总线节点，把所述时钟信号分配给所述每一个区域的所述功能块及总线节点；以及每一个功能块和总线节点被赋予预定的时钟插入延时。
29.如权利要求27或28所述的集成电路，其特征在于：至少一个区域具有连接到功能块的两个或两个以上总线节点，第一个所述总线节点直接连接到所述功能块、而其余所述总线节点经延时装置连接到所述功能块。
30.如权利要求29所述的集成电路，其特征在于：所述延时装置包括设置在所述各个总线节点和功能块之间的时钟桥。
31.如权利要求30所述的集成电路，其特征在于：所述时钟桥构成所述功能块的一部分。
32.如权利要求29至31中任何一项所述的集成电路，其特征在于：所述第一总线节点连接到所述功能块的中央部分。
33.如权利要求28至32中任何一项所述的集成电路，其特征在于：每一个功能块和总线节点的所述时钟插入延时基本上相等。
34.如权利要求28至32中任何一项所述的集成电路，其特征在于：一个功能块或总线节点的所述时钟插入延时按照预定量偏离另一个功能块或总线节点的所述时钟插入延时。
35.如权利要求34所述的集成电路，其特征在于：所述预定量与所述时钟插入延时加上或减去N个时钟周期有关，其中N为零或正整数。
36.如权利要求27至35中任何一项所述的集成电路，其特征在于：根据连接到所述通信总线的所述最大功能块的大小来选择所述时钟插入延时。
37.如权利要求27至36中任何一项所述的集成电路，其特征在于：所述区域中至少一个具有连接到功能块(50b)的两个或两个以上总线节点(53b、53c、53d)，每一个所述总线节点(53b、53c、53d)具有基本上相等的时钟插入延时(55b、55c、55d)，所述总线节点的所述时钟插入延时(55b、55c、55d)不同于所述功能块(50b)的所述时钟插入延时(57)；以及为所述区域中的所述时钟信号选择经延时缓冲器(65)到达每一个所述总线节点(53b、53c、53d)的路由。
38.如权利要求37所述的集成电路，其特征在于：所述功能块(50b)的所述时钟插入延时基本上等于由所述延时缓冲器(65)提供的所述延时与由各个总线节点提供的所述时钟插入延时(55b、55c、55d)之和。
39.如权利要求27至38中任何一项所述的集成电路，其特征在于：所述时钟信号沿所述通信总线分配给每一个功能块和总线节点。
40.一种降低集成电路中的峰值功率的方法，所述方法包括以下步骤：将所述集成电路分为多个功能块；向所述各个功能块这样分配时钟信号、使得至少两个功能块采用彼此时滞的时钟信号进行工作、从而降低所述集成电路中的峰值功率。
41.一种设计集成电路的方法，所述方法包括以下步骤：
将所述集成电路分为多个区域，每一个区域具有功能块和至少一个总线节点；
利用通信总线连接所述区域；
沿所述通信总线向所述各个功能块分配时钟信号；以及
把预定的时钟插入延时赋予每一个功能块和总线节点。
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