CN1639871A - 高频半导体器件及制造方法 - Google Patents

高频半导体器件及制造方法 Download PDF

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CN1639871A
CN1639871A CNA038048132A CN03804813A CN1639871A CN 1639871 A CN1639871 A CN 1639871A CN A038048132 A CNA038048132 A CN A038048132A CN 03804813 A CN03804813 A CN 03804813A CN 1639871 A CN1639871 A CN 1639871A
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克里斯托弗·P·卓根
韦恩·R·博格尔
丹尼尔·J·莱弥
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NXP USA Inc
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Abstract

一种半导体器件(10)，具有栅极(15)、源极(19)和漏极(20)以及用第一金属层构图形成的栅极总线(25)和第一接地屏蔽(24)以及用第二金属层构图形成的第二接地屏蔽(31)。第一接地屏蔽(24)和第二接地屏蔽(31)降低了器件(10)的电容，从而使其适用于高频应用和封装在塑料封装中。

Description

高频半导体器件及制造方法
技术领域
本发明一般涉及半导体器件，更具体地，涉及制造横向扩散金属氧化物半导体(LDMOS)器件的结构和方法。
背景技术
在例如蜂窝基站等应用中所用的半导体器件要求在高频下工作。对于这种类型的应用，由于射频(RF)LDMOS功率晶体管在从100MHz到约2GHz的频率范围内可以提供好的性能，所以受到关注。
由于散热的原因，RFLDMOS器件通常封装在昂贵的金属/陶瓷封装中。但是，由于塑料封装工艺成本较低，所以对于某些低到中功率应用，希望在塑料封装中封装这些器件。另外，塑料封装技术最近取得了改进，现在可以用来封装用在更高功率应用中的器件。
构成塑料封装的塑料注模化合物在器件内引起某些寄生电容增加，并使器件不能在器件的电容变得至关重要的GHz频率范围内使用。器件中的电容是寄生的，会降低RF性能，例如，功率增益和漏极效率。
发明内容
因此，需要提供一种LDMOS器件，特别是为高频应用设计的RF LDMOS器件，当封装在塑料封装中时具有低的电容。
根据本发明的一方面，提供一种制造半导体器件的方法，包括以下步骤：提供半导体本体；在半导体本体上形成栅极结构；在半导体本体中形成源极区和漏极区，其中源极区与栅极结构的一侧相邻，漏极区与栅极结构的另一侧相邻；在栅极结构上和与源极区相邻的半导体本体的一部分上形成第一介质层；形成电连接到源极区的源极接触；在与源极区相邻的第一介质层上形成栅极总线；在栅极总线和源极接触上形成第二介质层；以及在栅极总线上的第二介质层的一部分上形成金属层，并且电连接到源极接触。
根据本发明的另一方面，提供一种制造LDMOS器件的方法，包括以下步骤：提供半导体本体；在半导体本体上形成栅极结构；在半导体本体中形成源极区和漏极区，其中源极区与栅极结构的一侧相邻，漏极区与栅极结构的另一侧相邻；在栅极结构上和与源极区相邻的半导体本体的一部分上形成第一层间介质层；形成电连接到源极区并覆盖栅极结构的第一接地屏蔽；在与源极区相邻的第一介质层上形成栅极总线；在栅极总线和第一接地屏蔽上形成第二层间介质层；以及在栅极总线上的第二介质层的一部分上形成第二接地屏蔽，并且电连接到第一接地屏蔽上。
根据本发明的另一方面，提供一种半导体器件，包括：半导体本体；在半导体本体上的栅极结构；在半导体本体中的源极区和漏极区，其中源极区与栅极结构的一侧相邻，漏极区与栅极结构的另一侧相邻；在栅极结构上和与源极区相邻的半导体本体的一部分上的第一介质层；源极接触电连接到源极区；在与源极区相邻的第一介质层上的栅极总线；在栅极总线和源极接触上的第二介质层；以及在栅极总线上的第二介质层的一部分上的金属层，并且电连接到源极接触上。
附图说明
图1示出了在根据本发明的制造的开始阶段器件的一部分的剖面图；
图2示出了在根据本发明进一步处理图1的器件的剖面图；
图3示出了在根据本发明进一步处理图2的器件的剖面图；以及
图4示出了图3的器件的顶部布局图。
具体实施方式
通常，本发明提供形成即使密封在塑料封装中也具有较低电容的半导体器件的设计和方法，在高频应用中特别有用。具体地，利用第一和第二接地屏蔽的横向扩散金属氧化物半导体(LDMOS)器件设计提供低寄生电容。
图1示出了在根据本发明的制造的开始阶段器件10的实施例的一部分的放大剖面图。描述和示出了LDMOS器件的简化形式，以便将注意力集中在本发明的新颖特性上，包括栅极总线以及在第一金属层中形成的接地屏蔽和在第二金属层中形成的接地屏蔽的设计，如在下面更详细介绍的那样。在属于本发明的相同受让人，Motorola，Inc.，的Costa等人发表的美国专利No.5,578,860中介绍了没有本发明的新颖特性的形成LDMOS器件的结构和工艺，并且引入作为参考。
仍然参考图1，器件10包括半导体本体11。半导体本体11最好为P型硅材料，并且一般包括P+掺杂的衬底12和在P+掺杂的衬底12上形成的轻掺杂P外延层13。通过光刻、离子注入和扩散/退火技术在P掺杂的外延层13中至少到达P+掺杂的衬底12形成吸收区(sinker region)14。吸收区14是重掺杂的(P+型)，从而形成到源极区19的背侧连接(从P+掺杂的衬底12的外表面)的低阻通路(将在下面介绍)。
然后，在半导体本体11上形成栅极结构15。为了方便说明，以高度简化的方式示出了栅极结构15。栅极结构15由栅极介质层和栅极电极(没有单独示出)构成。最好，栅极电极包括重掺杂多晶半导体层和在多晶半导体层上形成的栅极欧姆或金属层。最好，栅极金属层由钨/硅合金构成，但是，其它材料也是合适的，包括钛、氮化钛、钼等。多晶半导体层一般为N型掺杂。
然后在器件10上形成并构图掩模层或光致抗蚀剂层17，留下形成都是N型掺杂区的源极区19和漏极区20的开口。最好，通过光致抗蚀剂17的开口在半导体本体11中选择性的离子注入砷形成源极区19和漏极区20。离子注入之后通常是退火工艺。栅极结构15的一部分也作为掩模，从而所形成的源极区19自对准栅极结构15的一侧。在形成源极区19的栅极结构15的另一侧的半导体本体11中形成漏极区20。
图2示出了进一步处理的图1的器件。这里，已经去掉了光致抗蚀剂17，在器件10的上表面上形成第一层间介质层(ILD0层)22，并用在源极区19和漏极区20上的开口构图，如图2所示。在本发明中，ILD0层22的一部分留在源极区19的一部分上和吸收区14上。常规光致抗蚀剂和蚀刻技术用来提供在ILD0层22中的开口。
最好，ILD0层22由硅酸盐玻璃层构成。具体的，硅酸盐玻璃层由首先淀积的未掺杂的硅酸盐玻璃(USG)、在USG上淀积的磷硅酸盐玻璃(PSG)和在PSG上淀积的第二层USG，USG/PSG/USG的总厚度在从3000到20000埃的范围内。使用常规化学气相淀积(CVD)技术淀积USG/PSG/USG层。使用PSG层用于积聚硅酸盐玻璃中存在的任何杂质。
仍然参考图2，在器件10的表面形成第一欧姆或金属层，并构图，以提供第一接地屏蔽24、栅极总线25和第一漏极接触26。最好，第一金属层的厚度在从1.0到1.5微米的范围内。第一金属层通常包括铝、铝合金或多层金属化物质，例如钛-钨合金层接着是铝-铜合金层。
例如，包括第一接地屏蔽24、栅极总线25和漏极接触26的第一金属层由铝或铝合金，例如，铝铜钨合金(AlCuW)构成，以提供低电阻率的金属化物质。或者，第一金属层由750到3000埃的钛-钨(TiW)阻挡金属层和在TiW层上的至少1.0微米的铝合金(例如，AlCu)层构成。最好，第一金属层的总厚度在5000到30000埃之间。
最好，常规溅射技术用来形成第一金属层。光致抗蚀剂和蚀刻技术用来限定源极接触或第一接地屏蔽24、栅极总线25和第一漏极接触26。
源极接触或第一接地屏蔽24与源极区19电接触。第一接地屏蔽24覆盖栅极结构15，减小在漏极区20(包括第一漏极接触26和第二漏极接触33，如图3所示和介绍)和栅极结构15之间的寄生电容。在本实施例中，形成第一接地屏蔽24覆盖栅极结构15并在ILD0层22上。但是，可以在ILD0层22的一部分上形成第一接地屏蔽24，并且不延伸到栅极结构15上，仅作为源极接触24。第一接地屏蔽24覆盖栅极结构15并不是实现本发明的益处所必需的，因为将形成第二接地屏蔽31，如下面参考图3所讨论的。在栅极结构15的指状物之间的ILD0层22上形成栅极总线25。每个漏极接触26与漏极区20电接触。
现在参考图3，在ILD0层22、栅极总线25、第一接地屏蔽24和漏极接触26上形成第二层间介质层(ILD1层)29。ILD1层29最好由厚度在0.5到4.0微米范围内的二氧化硅(等离子体增强的CVD(PECVD)二氧化硅是合适的)构成。希望ILD1层29平坦，所以最好在两步中淀积二氧化硅，在两次淀积之间具有平坦化步骤。
仍然参考图3，是用常规光刻和蚀刻技术在ILD1层29中形成接触开口或过孔。在ILD1层29上和在ILD1层29中的接触开口或过孔中形成第二欧姆或金属层，并构图以定义第二接地屏蔽31和第二漏极接触33。最好，第二金属层由铝或铝合金构成，更优选厚度在大约5000到60000埃范围内的AlCuW合金。AlCuW金属化物质对电迁移有关的失效提供增强保护。
形成第二接地屏蔽31覆盖栅极总线25和源极区19，并且电连接到第一接地屏蔽24。第二接地屏蔽31覆盖栅极总线25，从而进一步降低漏-栅极电容。用第一金属层(而不是第二金属层)形成栅极总线25允许在栅极总线25上形成的第二接地屏蔽31进一步降低器件的电容。第二漏极接触33电连接到第一漏极接触26，并且形成键合焊盘区。
现在参考图4，示出了图3的顶部布局图，可以看到如何在栅极结构15的指状物之间形成栅极总线25，并且平行于栅极结构15的指状物延伸。栅极总线25在接触区27周期性地电连接到栅极结构15，以便栅极电阻(Rg)保持足够低，从而不降低器件10的功率增益。
现在重新参考图3，通过在器件10上形成钝化层35最终完成器件10的处理。钝化层35最好由磷硅酸盐玻璃(PSG)和在PSG层上组合形成的PECVD二氧化硅/氮化硅膜构成。随后，使用常规封装技术将器件10封装在塑料封装37中。塑料封装37由注模化合物构成。应当注意，在第二源极接触/第二接地屏蔽31和漏极接触33之间形成塑料封装37的注模化合物。构成塑料封装37的塑料对漏极区20(包括第一漏极接触26和第二漏极接触33)与栅极总线25之间的电容有贡献。
虽然只示出了LDMOS的一部分，但是，应当理解，引入多个上述结构的器件形成LDMOS器件。通常，以交替的源极区19和漏极区20相互交错方式设计LDMOS结构10。栅极结构15和漏极区20的指状物长度可以为300到1000微米。此外，LDMOS器件可以与无源器件(例如，电阻、电容和电感)和其它有源器件(例如，逻辑器件)集成在一起，并且这种器件也在本发明的范围内。
此外，虽然上面介绍了N沟道LDMOS结构，但是根据本发明的结构和方法也支持N和P型掺杂剂变换的P沟道LDMOS结构。
现在，应当理解，提供了在塑料封装中具有较低电容的LDMOS器件的结构和方法，特别有利于高频应用。该结构和方法利用由第一金属层定义的栅极总线25和第一接地屏蔽24以及由覆盖栅极总线25的第二金属层定义的第二接地屏蔽31。第一接地屏蔽24和第二接地屏蔽31起减小栅-漏极电容的作用。本发明的LDMOS在高频应用中提供好的性能，并且比封装在常规金属/陶瓷封装中的LDMOS器件显著降低成本。
由此，提供完全满足上述优点的LDMOS器件的设计和工艺。虽然参考特定说明的实施例介绍和说明了本发明，但是，这些示例性实施例并不是要限定本发明。本领域的技术人员应当认识到，可以不脱离本发明的精神进行改变和修改。因此，落入附带的权利要求书及其等价物的范围内的所有这种改变和修改都包括在本发明中。

Claims (12)

1.一种制造半导体器件的方法，包括以下步骤：
提供半导体本体；
在半导体本体上形成栅极结构；
在半导体本体中形成源极区和漏极区，其中源极区与栅极结构的一侧相邻，漏极区与栅极结构的另一侧相邻；
在栅极结构上和与源极区相邻的半导体本体的一部分上形成第一介质层；
形成电连接到源极区的源极接触；
在与源极区相邻的第一介质层上形成栅极总线；
在栅极总线和源极接触上形成第二介质层；以及
在栅极总线上的第二介质层的一部分上形成金属层，并且金属层电连接到源极接触。
2.根据权利要求1的方法，其中形成第一介质层的步骤包括形成由硅酸盐玻璃层构成的第一介质层。
3.根据权利要求1的方法，其中形成源极接触的步骤还包括源极接触提供第一接地屏蔽，以减小在栅极结构和漏极区之间的电容。
4.根据权利要求1的方法，其中形成源极接触和形成栅极总线的步骤包括由相同的金属化层形成源极接触和栅极总线。
5.根据权利要求1的方法，其中形成金属层的步骤还包括金属层提供第二接地屏蔽，以减小在栅极总线和漏极区之间的电容。
6.根据权利要求1的方法，其中形成源极接触的步骤包括形成第一接地屏蔽，形成金属层的步骤包括形成第二接地屏蔽。
7.根据权利要求1的方法，还包括在塑料封装中封装半导体本体的步骤。
8.一种制造LDMOS器件的方法，包括以下步骤：
提供半导体本体；
在半导体本体上形成栅极结构；
在半导体本体中形成源极区和漏极区，其中源极区与栅极结构的一侧相邻，漏极区与栅极结构的另一侧相邻；
在栅极结构上和与源极区相邻的半导体本体的一部分上形成第一层间介质层；
形成电连接到源极区并覆盖栅极结构的第一接地屏蔽；
在与源极区相邻的第一介质层上形成栅极总线；
在栅极总线和第一接地屏蔽上形成第二层间介质层；以及
在栅极总线上的第二介质层的一部分上形成第二接地屏蔽，并且第二接地屏蔽电连接到第一接地屏蔽上。
9.一种半导体器件，包括：
半导体本体；
在半导体本体上的栅极结构；
在半导体本体中的源极区和漏极区，其中源极区与栅极结构的一侧相邻，漏极区与栅极结构的另一侧相邻；
在栅极结构上和与源极区相邻的半导体本体的一部分上的第一介质层；
电连接到源极区的源极接触；
在与源极区相邻的第一介质层上的栅极总线；
在栅极总线和源极接触上的第二介质层；以及
在栅极总线上的第二介质层的一部分上的金属层，并且金属层电连接到源极接触上。
10.根据权利要求9的器件，还包括塑料封装半导体器件。
11.根据权利要求9的器件，其中源极接触为第一接地屏蔽，第一接地屏蔽减小了栅极结构和漏极区之间的电容。
12.根据权利要求9的器件，其中金属层为第二接地屏蔽，第二接地屏蔽减小了栅极总线和漏极区之间的电容。
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