CN1648871A - 发生中断时按其类型限定性能监视事件收集的方法与装置 - Google Patents
发生中断时按其类型限定性能监视事件收集的方法与装置 Download PDFInfo
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- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
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- G06F11/348—Circuit details, i.e. tracer hardware
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- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
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Abstract
一种方法、装置与计算机指令，用来当在数据处理系统的处理器中发生中断时按照中断类型限定事件。可编程性能监视单元(PMU)用来编程收集与中断类型(包括嵌套中断)相关联的事件的硬件计数器。性能监视单元还可根据中断处理的状态来计数在请求服务中断时发生的事件。在性能监视单元中使用多个性能监视计数器，可以同时计数为性能监视单元所知的事件，例如指令退回、TLB丢失。
Description
技术领域
一般地，本发明涉及一种改进的数据处理系统，具体地讲，涉及一种在数据处理系统中当发生中断时监视处理器性能的方法与系统。更具体地讲，本发明涉及一种方法、装置与计算机指令，用来当发生中断时按中断类型限定(qualify)对监视事件性能的收集。
背景技术
典型的数据处理系统利用处理器来执行一组指令以执行特定任务，例如从主存储器中读取特定字符。然而，随着需要处理器执行的任务数目的增加，对于希望优化系统的工程师来说，处理器对存储器的访问模式的效率以及此类访问的特性成为重要因素。
当前，现有技术包含可以计数数据处理系统内软件可选事件(例如高速缓存丢失、所执行的指令、I/O数据传送请求)的发生次数，以及执行给定进程所需要的时间的机制。一种此类机制为性能监视器。性能监视器进行对选定特性的监视，从而通过确定特定时间的机器状态而有助于系统分析。该分析提供以下信息：当执行指令时如何使用处理器，以及当存储数据时处理器与主存储器的交互作用。另外，性能监视器可以提供处理系统中事件之间所经过的时间量。性能监视器提供工程师可以用来分析系统性能的事件计数。该分析可能引起应用代码改变，例如可能的重新分配分支指令与存储器访问，以进一步优化系统性能。另外，性能监视器可以收集有关处理器如何访问数据处理系统的一级与二级高速缓存、以及主存储器的数据，以发现特定于硬件或软件环境的性能瓶颈。
如上所述的性能监视器不提供以下功能：进一步限定对于特定类型的中断发生的事件。例如当诸如鼠标或者键盘等设备发起中断信号时，发生中断，以通知处理器发生了事件。当处理器接受中断请求时，处理器完成其当前指令，并且将控制传送给中断处理程序(handler)。中断处理程序执行与该中断相关联的中断服务例程。中断也可能由特定机器语言操作代码引起，例如摩托罗拉公司的产品——68000的TRAP。在这种情况下，诸如除以零等未预料软件条件使处理器存储当前状态，存储有关特定中断的标识信息，并且将控制传送给处理该未预料软件条件的中断处理程序。
以下是有益的：具有一种改进的方法、装置、以及计算机指令，用来限定发生的事件的计数，同时根据已经发生的中断类型服务请求中断。
发明内容
本发明提供了一种的方法、装置、以及计算机指令，当在数据处理系统的处理器中发生中断时，其通过按中断类型限定事件，来监视数据处理系统的性能。本发明的性能监视单元被编程来计数基于已经发生的中断类型限定的事件。当性能监视单元检测到特定类型的中断时，性能监视单元收集对该中断类型发生的事件。结果的事件信息以后被呈现给用户以进行性能分析。
附图说明
在权利要求中列出了本发明特有的新颖特征。通过参照附图及以下对示范性实施方式的详细描述将更好地理解本发明自身、优选使用模式及其进一步的目的与优点，其中：
图1为可以实现本发明的数据处理系统的示范性方框图；
图2为根据本发明优选实施方式的处理系统的处理器系统的示范性方框图；
图3为显示根据本发明优选实施方式的、当中断发生时按中断类型计数事件的组件的示范性图示；
图4为显示根据本发明优选实施方式的、性能监视单元与中断单元的组件的示范性图示；
图5为概括显示根据本发明优选实施方式的、当中断发生时基于中断类型限定对事件的计数的示范性过程的流程图。
具体实施方式
本发明的优选实施方式当在数据处理系统上执行程序时监视数据处理系统的性能。在一种实施方式中，对性能监视单元进行编程，以计数事件(例如高速缓存丢失、时钟周期、或者其他在中断的执行与处理过程中发生的事件)，并且通过在其过程中发生事件的中断类型以及(在某些实施方式中)在其过程中发生事件的中断的状态，来限定那些被计数的事件。在本发明的系统与方法中收集的信息可以呈现给软件或用户以进行分析。
在优选实施方式中，本发明实现于计算机系统中。例如，该计算机系统可以是网络的客户端-服务器环境下的客户端或者服务器。现在参照图1，显示了其中可以实现本发明的数据处理系统的示范性方框图。客户端100为计算机的实例，其中可以放置实现本发明的处理的代码或指令。客户端100采用外围组件互连(PCI)局部总线体系结构。虽然所显示的例子采用PCI总线，但是可以使用其他总线体系结构，例如加速图形端口(AGP)与工业标准体系结构(ISA)。处理器102与主存储器104通过PCI桥108连接到PCI局部总线106。PCI桥108还可以包含处理器102的高速缓存和集成的存储器控制器。通过直接组件互连或者通过插入板，可以进行到PCI局部总线106的其他连接。在所示例子中，局域网(LAN)适配器110、小型计算机系统接口SCSI主机总线适配器112、以及扩展总线接口114通过直接组件互连而连接到PCI局部总线106。与此不同，音频适配器116、图形适配器118、以及音频/视频适配器119通过插入扩展槽中的插入板连接到PCI局部总线106。扩展总线接口114提供用于键盘和鼠标适配器120、调制解调器122、以及附加存储器124的连接。SCSI主机总线适配器112提供用于硬盘驱动器126、磁带驱动器128、以及CD-ROM驱动器130的连接。典型的PCI局部总线实现将支持三或四个PCI扩展槽或者插入连接器。
操作系统运行在处理器102上，并且用来协调并提供对于图1的数据处理系统100内各种组件的控制。操作系统可以是在市面上能够购买的操作系统，例如Windows XP，其可从微软公司得到。诸如Java等面向对象的编程系统可以与操作系统联合运行，并且提供从在客户端100上执行的应用程序或者Java程序到操作系统的调用。“Java”为Sun Microsystems公司的商标。操作系统、面向对象的编程系统以及应用程序或者程序的指令位于存储设备上，例如硬盘驱动器126上，并且可以加载到主存储器104内，以由处理器102执行。
本领域技术人员应该理解：图1中的硬件可能根据实现而变化。除图1所示硬件之外，或者替代这些硬件地，可以使用其他内部硬件或外围设备，例如闪存只读存储器(ROM)、等效的非易失存储器、或者光盘驱动器等等。另外，本发明的处理可以应用到多处理器数据处理系统。
例如，客户端100如果可选地配置为网络计算机，则可以不包含SCSI主机总线适配器112、硬盘驱动器126、磁带驱动器128、以及CD-ROM 130。在这种情况下，该计算机，正确地应该称为客户端计算机，包含某种类型的网络通信接口，例如LAN适配器110、调制解调器122等等。作为另一例子，客户端100可以是独立的系统，其被配置为可引导的，而不依赖于某种类型的网络通信接口，而不管客户端100是否包含某种类型的网络通信接口。作为另一例子，客户端100可以是个人数字助理(PDA)，其配备有ROM和/或闪存ROM，以提供非易失存储器，用来存储操作系统文件和/或用户生成的数据。图1中所示的例子以及上述例子并不是用来暗指对体系结构的限制。
本发明的处理由处理器102使用计算机实现的指令来执行，这些指令可能位于存储器中，例如主存储器104、存储器124，或者位于一或多个外围设备126-130中。
转到图2，显示了根据本发明优选实施方式的用来处理信息的处理器系统的示范性方框图。处理器210可以实现为图1中的处理器102。
在优选实施方式中，处理器210为单一的集成电路超标量微处理器。相应地，如下详细所述，处理器210包含各种单元、寄存器、缓冲器、存储器、以及其他部分，所有这些都由集成电路形成。另外，在优选实施方式中，处理器210根据精减指令集计算机(“RISC”)技术运行。如图2所示，系统总线211连接到处理器210的总线接口单元(“BIU”)212。BIU 212控制处理器210与系统总线211之间信息的传送。
BIU 212连接到处理器210的指令高速缓存214与数据高速缓存216。指令高速缓存214输出指令到排序单元218。响应于来自指令高速缓存214的这些指令，排序单元218选择性地输出指令到处理器210的其他执行电路。
除排序单元218之外，在优选实施方式中，处理器210的执行电路还包含多个执行单元，即分支单元220、定点单元A(“FXUA”)222、定点单元B(“FXUB”)224、复杂定点单元(“CFXU”)226、加载/存储单元(“LSU”)228、以及浮点单元(“FPU”)230。FXUA 222、FXUB 224、CFXU 226、以及LSU 228从通用体系寄存器(“GPR”)232以及定点重命名缓冲器234输入其源操作数信息。另外，FXUA 222与FXUB 224从进位位(“CA”)寄存器239输入“进位位”。FXUA 222、FXUB 224、CFXU 226、以及LSU 228输出其运行结果(目的操作数信息)，以在定点重命名缓冲器234中的选定项处存储。另外，CFXU 226从/向专用寄存器处理单元(“SPR单元”)237输入与输出源操作数信息与目的操作数信息。
FPU 230从浮点体系寄存器(“FPR”)236与浮点重命名缓冲器238输入其源操作数信息。FPU 230输出其运行结果(目的操作数信息)，以在浮点重命名缓冲器238中的选定项处存储。
响应于加载指令，LSU 228从数据高速缓存216输入信息，并且将该信息拷贝到重命名缓冲器234与238中的选定项。如果该信息未存储在数据高速缓存216中，则数据高速缓存216从连接到系统总线211的系统存储器260输入该信息(通过BIU 212与系统总线211)。另外，数据高速缓存216能够从数据高速缓存216输出信息到连接到系统总线211的系统存储器260(通过BIU 212与系统总线211)。响应于存储指令，LSU 228从GPR 232与FPR236的选定项输入信息，并且将该信息拷贝到数据高速缓存216。
排序单元218从/向GPR 232与FPR 236输入与输出信息。从排序单元218，分支单元220输入指示处理器210当前状态的指令与信号。响应于这些指令与信号，分支单元220(向排序单元218)输出指示存储由处理器210执行的指令序列的适当存储器地址的信号。响应于来自分支单元220的这些信号，排序单元218从指令高速缓存214输入所指示的指令序列。如果一或多个指令序列未存储在指令高速缓存214中，则指令高速缓存214从连接到系统总线211的系统存储器260输入这些指令(通过BIU 212与系统总线211)。
响应于从指令高速缓存214输入的指令，排序单元218选择性地分发指令到选定的执行单元220、222、224、226、228、以及230。每个执行单元执行特定指令类别的一或多条指令。例如，FXUA 222与FXUB 224对源操作数执行第一类别的定点数学运算，例如加法、减法、与、或、以及异或。CFXU226对源操作数执行第二类别的定点运算，例如定点乘法与除法。FPU 230对源操作数执行浮点运算，例如浮点乘法与除法。
当信息存储在重命名缓冲器234的选定项时，该信息与为其分配选定的重命名缓冲器的指令所指定的存储位置相关联(例如GPR 232中的一个或者进位位(CA)寄存器242)。响应于来自排序单元218的信号，在重命名缓冲器234的选定项处存储的信息被拷贝到GPR 232中其相关联的一个(或者CA寄存器242)。响应于“完成”生成该信息的指令，排序单元218指挥对在重命名缓冲器234选定项处存储的信息的所述拷贝。该拷贝称为“写回”。
当信息存储在重命名缓冲器238的选定项时，该信息与FPR 236中的一个相关联。响应于来自排序单元218的信号，在重命名缓冲器238的选定项处存储的信息被拷贝到FPR 236中其相关联的一个。响应于“完成”生成该信息的指令，排序单元218指挥对在重命名缓冲器238选定项处存储的信息的所述拷贝。
通过在各个执行单元220、222、224、226、228、以及230处同时处理多条指令，处理器210达到高性能。相应地，每条指令被当作一系列阶段处理，每个阶段都可与其他指令的阶段并行执行。这种技术称为“流水线”。根据所示实施方式的一个重要方面，指令一般被处理为六个阶段，即获取、解码、分发、执行、完成、以及写回。
在获取阶段，排序单元218(从指令高速缓存214)选择性地输入来自一或多个存储器地址的一或多条指令，所述存储器地址存储了上面结合分支单元210与排序单元218进一步讨论的指令序列。
在解码阶段，排序单元218解码多达四条所获取的指令。
在分发阶段，在为所分发的指令的结果(目的操作数信息)保留了重命名缓冲器项之后，排序单元218(响应于解码阶段的解码)选择性地分发多达四条已解码的指令到选定的执行单元220、222、224、226、228、以及230中的几个。在分发阶段，操作数信息被提供给对于所分发的指令的选定执行单元。处理器210按其编程序列分发指令。
在执行阶段，执行单元执行其所分发的指令，并且输出其运行结果(目的操作数信息)，以在重命名缓冲器234与重命名缓冲器238中选定项处存储，如上所述。通过这种方式，处理器210能够相对于其编程序列乱序地执行指令。
在完成阶段，排序单元218指示指令为“完成”。处理器210按其编程序列“完成”指令。
在写回阶段，排序单元218指挥从重命名缓冲器234与238分别拷贝信息到GRP 232与FPR 236。排序单元218指挥对在选定的重命名缓冲器处存储的信息的所述拷贝。类似地，在特定指令的写回阶段，响应于特定指令，处理器210更新其体系状态。处理器210按其编程序列处理指令的各个“写回”阶段。优选地，在指定情况下，处理器210合并指令的完成阶段与写回阶段。
在所示实施方式中，每条指令都要求一个机器周期来完成指令处理的每个阶段。然而，某些指令(例如由CFXU 226执行的复杂定点指令)可能要求多于一个周期。因此，响应于完成先前指令所需的时间的变化，在特定指令的执行与完成阶段之间可能发生可变延迟。
在排序单元218内配备有完成缓冲器248，用来跟踪在执行单元内执行的多条指令的完成情况。当指示已经成功地完成一条指令或一组指令时，按照应用程序所指定的先后顺序，完成缓冲器248可用来启动传送这些已完成指令的结果到相关联的通用寄存器。
另外，处理器210还包含性能监视单元240，该单元连接到指令高速缓存214以及处理器210中的其他单元。利用性能监视单元240，可以监视处理器210的运行，在所示实施方式中，性能监视单元240为软件可访问机制，其能够提供描述指令执行资源的利用情况与存储控制的详细信息。虽然在图2中未显示，但是性能监视单元240耦合至处理器210的每个功能单元，以允许监视处理器210运行的所有方面，包含(例如)重建事件之间的关系、标识错误触发、标识性能瓶颈、监视流水线停滞、监视空闲处理器周期、确定分发效率、确定分支效率、确定未对准数据访问的性能损失、标识串行化指令执行的频率、标识被禁止的中断、以及确定性能效率。感兴趣的事件还包括(例如)指令解码的时间、指令的执行、分支事件、高速缓存丢失、以及高速缓存命中。
性能监视单元240包含依赖于实现的数目(例如2-8)的计数器214-242，标记为PMC1与PMC2，其用来计数选定事件的发生次数。性能监视单元240还包含至少一个监视器模式控制寄存器(MMCR)。在该例子中，存在两个控制寄存器，MMCR 243与244，其指定计数器241-242的功能。优选地，计数器241-242与MMCR 243-244实现为可以借助由CFXU 226执行的MFSPR(从SPR移动)与MTSPR(向SPR移动)进行读或写访问的SPR。然而，在一替换实施方式中，计数器241-242与MMCR 243-244简单地可以实现为I/O空间中的地址。在另一替换实施方式中，控制寄存器与计数器可以借助索引寄存器间接地访问。该实施方式实现于英特尔公司的处理器中的IA-64体系结构中。
另外，处理器210还包括中断单元250，其连接到指令高速缓存214。另外，尽管在图2中未显示，但是中断单元250连接到处理器210内其他功能单元。中断单元250可以接收来自其他功能单元的信号，并且启动动作，例如开始错误处理或者陷阱过程。在这些例子中，中断单元250用来生成可能在程序执行过程中发生的例外和中断。另外，对于诸如PMC1 241等每个性能监视计数器，都有相应的中断单元控制寄存器(IUCR)，例如可由中断单元250访问的IUCR2 252。在该例子中，IUCR1 252相应于PMC1 241。IUCR2252相应于PMC2 242。IUCR1 252与IUCR2 254标识哪个中断生成信号，从而PMC1 241与PMC2 242可以计数与该中断相关联的事件。
本发明提供了一种方法、装置、以及计算机指令，用来当在数据处理系统的处理器中发生中断时，通过按中断类型限定事件，监视诸如图1中客户端100等数据处理系统性能。该数据处理系统的处理器可以实现为图2的处理器210。
在优选实施方式中，本发明提供性能监视单元(PMU)，例如图2中的性能监视单元240，其是可以利用诸如MMCR 243与MMCR 244等计数器控制寄存器(CCR)编程的，以计数在中断执行过程中发生的事件。所计数的事件可以由在其过程中发生该事件的中断类型限定。这些事件当前对于性能监视单元是已知的，例如退回的指令、TLB失误、二级高速缓存丢失、或者时钟周期等等。在优选实施方式中，本发明的性能监视单元允许用户通过中断类型限定事件或条件，优选地通过利用性能监视单元的硬件计数器与寄存器。当发出中断信号时，中断信号被用来标识本发明的计数机制是否被编程来在该类型的中断期间计数事件。
可以扩展性能监视单元中的计数器控制寄存器(CCR)以包括中断单元(IU)轨迹字段、中断单元(IU)状态字段、以及中断单元(IU)状态掩码字段。IU轨迹字段允许用户通过使能或禁止轨迹跟踪来控制计数。IU状态字段表示中断处理的当前状态，例如中断开、中断以被拾取、中断以被确认、以及中断关。IU状态掩码字段指示在其期间要发生轨迹跟踪的中断处理的状态。这些字段由性能监视单元使用，以计数在中断的各种状态期间发生的事件，并且按状态分析计数。结果的数据可以由用户或者轨迹应用程序读取，例如从性能监视单元中读取，以在以后进行性能分析，从而更好地优化系统。
另外，利用多个性能监视计数器，性能监视单元可以同时计数多个事件。本发明的机制允许性能监视单元编程每个计数器以计数特定事件。例如，计数器1可以被编程来计数对于中断向量1的高速缓存丢失，计数器2可以被编程来计数对于中断向量2的计数周期等等。本发明的优选实施方式不限制对于计数器的限定。根据用户可用的硬件，计数器可以被编程来计数多个事件。
另外，性能监视单元支持计数嵌套中断的事件。在一个中断激活的同时发生另一中断时，即发生嵌套中断。本发明的性能监视单元使性能监视计数器能够将计数只限制在中断处理的开或关状态。对于工程师研究中断处理自身的效率，该机制可能有用。
接着转到图3，根据本发明的优选实施方式，显示了显示用来当中断发生时按中断类型计数事件的组件的示例图。如图3所示，在优选实施方式中，中央处理单元(CPU)302可以实现为图2中的处理器210。当中断发生时，中央处理单元(CPU)302发送信号给中断单元304，以请求中断单元304生成对于特定中断类型的中断信号。
根据性能监视单元306中性能监视计数器的数目，中断单元304可以包括多个中断单元控制寄存器(IUCR)，其可由中断单元304访问。在IUCR与性能监视计数器之间具有一对一关系。在该例子中，具有两个IUCR，相应于性能监视计数器PMC1 312的IUCR1 308，以及相应于性能监视计数器PMC2 314的IUCR2 310。诸如IUCR1 308的IUCR包含类型字段，该字段指示哪种中断类型生成性能监视计数器信号。IUCR中的类型字段以后由中断单元304检查，以察看其是否为感兴趣的中断类型，即在中断执行过程中是否要计数事件。如果中断类型信号为感兴趣的中断类型，则中断单元304发送轨迹跟踪开/关信号给性能监视单元306，以使能或禁止计数。
另外，如图3所示，性能监视单元306包括依赖于实现的数目的硬件计数器，例如硬件计数器312与314，此处也被称为性能监视计数器。PMC1 312与PMC2 314计数在中断处理的特定状态期间发生的事件。性能监视单元306还包括诸如CCR1 316与CCR2 318等多个计数器控制寄存器(CCR)，其可以实现为图2中的MCCR1 233与MCCR2 234。当CCR1 316与CCR2 318从中断单元304收到使能或禁止在中断处理期间轨迹跟踪某中断类型的事件与状态变化的信号时，通过存储中断的当前状态与待轨迹跟踪的中断的状态，CCR1 316与CCR2 318控制性能监视计数器PMC1 312与PMC2 314的计数，从而当使能轨迹跟踪时，性能监视计数器PMC1 312与PMC2 314可以计数特定中断状态的事件。然后存储结果的轨迹数据，并且可以在以后时间从性能监视计数器312与314中收集结果的轨迹数据。
参照图4，根据本发明的优选实施方式，显示了显示性能监视单元与中断单元的组件的示例图。如图4所示，在优选实施方式中，性能监视单元可包括多个计数器控制寄存器(CCR)，其可以实现为存储器模式寄存器(MMCR)，例如图2中的MMCR1 233与MMCR2 234。计数器控制寄存器控制性能监视计数器的功能。计数器控制寄存器402可以包含3个字段：中断单元(IU)轨迹字段404、中断单元(IU)状态字段406、以及中断单元(IU)状态掩码字段408。在该例子中，IU轨迹字段404为一位字段，由位0表示；IU状态字段406为两位字段，由位1与2表示；IU状态掩码字段408为三位字段，由位3至5表示。
如图4所示，轨迹410为IU轨迹字段404的例子。当该位为0时，性能监视计数器的轨迹跟踪为关或被禁止。当该位为1时，性能监视计数器的轨迹跟踪为开或被使能。轨迹410由轨迹跟踪开/关信号设置，一旦中断单元检查中断单元控制寄存器(IUCR)以确定中断类型是否为感兴趣的，该轨迹跟踪开/关信号由中断单元发出。例如，输入的中断信号可与为计数处理指定的、存储的中断集合比较。
接着，状态416表示IU状态字段406示例。状态416只由性能监视单元读取，并且用来存储中断的当前状态。当中断状态为中断开418时，状态310中的位被设置为01。当中断状态为中断被拾取420时，状态410中的位被设置为10。当中断状态为中断被确认422时，状态410中的位被设置为11。当中断状态为中断关424时，状态410中的位被设置为00。
计数器控制寄存器中的最后的字段为IU状态掩码字段408。状态掩码426表示IU状态掩码字段408的例子。IU状态掩码字段426指示在哪个中断状态期间计数事件。当在其期间计数的状态为中断开428时，状态掩码位426被设置为001。当在其期间计数的状态为中断被拾取430时，状态掩码位426被设置为010。当在其期间计数的状态为中断被确认时，状态掩码位426被设置为100。
最后，在图4中显示了中断单元控制寄存器(IUCR)440。IUCR可以由中断单元访问。IUCR 440包含大小为一字节(8位)的类型字段442。类型字段442表示哪种中断类型将生成至性能监视单元的轨迹跟踪开/关信号。
本发明的优选实施方式可以用来基于在其期间发生事件的中断的类型来计数事件。在IUCR字段记录中断类型，该字段指示在其期间对事件进行监视的中断类型将发生。当中断发生时，中断类型与IUCR中的项比较，并且如果所发生的中断匹配IUCR中的项，则计数在该中断期间发生的事件。向PMU发送信号以打开轨迹跟踪，这使PMU将CCR设置为此时发生的中断的状态。当中断经过其状态时，PMU继续指示中断处于哪种状态，从而可以根据在其期间发生事件的中断状态来分析在该中断期间计数的事件。
转到图5，根据本发明的优选实施方式显示概括当中断发生时基于中断类型限定对事件的计数的示例性处理的概略流程图。如图5所示，当支持软件(例如性能监视软件)与硬件接口以启动中断处理(步骤502)时，开始该处理。然后由支持软件设置性能监视计数器以监视某些事件(步骤504)，例如高速缓存丢失或者时钟周期。支持软件还设置中断单元控制寄存器(IUCR)类型字段，以指示监视哪种中断类型(步骤506)，即在哪些中断类型期间要计数事件。接着，支持软件设置相应于用来计数事件的性能监视计数器的、计数器控制寄存器(CCR)的中断单元(IU)轨迹字段(步骤508)。步骤508使能对事件的轨迹跟踪。
在步骤508设置IU轨迹字段之后一定时间，执行要监视其性能的应用程序的应用程序代码(步骤510)。当在代码执行期间发生中断(步骤512)时，中断单元检查IUCR类型字段(步骤514)。对该中断是否与IUCR类型相同进行判定，IUCR类型为感兴趣的中断类型(步骤516)。如果该中断类型不同于IUCR类型，则该过程返回步骤512，以等待下一中断发生。如果该中断类型与IUCR类型相同，则中断单元发出轨迹跟踪开/关信号，并且将该信号发送给性能监视单元(步骤518)，以开始轨迹跟踪中断事件。一旦收到该信号，性能监视单元就通过设置计数器控制寄存器的状态字段位为01，将计数器控制寄存器的状态字段设置为中断开(步骤520)。
接着，中断状态变为中断被拾取，中断单元进而发出状态变化信号，并且将该信号发送给性能监视单元(步骤522)。随后，性能监视单元通过设置计数器控制寄存器的状态字段位为10，设置计数器控制寄存器的状态字段为中断被拾取(步骤524)。另一中断状态变化使中断单元发出状态变化信号，并且将该信号发送给性能监视单元(步骤526)。类似地，性能监视单元通过设置计数器控制寄存器的状态字段位为11，设置计数器控制寄存器的状态字段为中断被确认(步骤524)。当中断处理程序完成执行中断服务例程时，其向中断单元发送IRET(中断返回)信号(步骤530)。中断单元发出轨迹跟踪开/关信号，并且将该信号发送给性能监视单元，以停止轨迹跟踪中断的事件(步骤532)。(注意：本发明的实施方式可以跨越一或多个中断状态进行轨迹跟踪，如上所述。)最终，性能监视单元接收该信号，并且通过将计数器控制寄存器状态字段位设置为00，而将计数器控制寄存器状态字段设置为中断关(步骤534)。由此，该处理中止。
由此，本发明提供了一种性能监视单元，其允许用户使用一或多个硬件计数器按中断类型限定发生的事件。硬件计数器收集当服务中断请求时发生的事件，以使用户能够监视当处理特定类型中断时的系统性能。通过利用本发明的多个硬件计数器，用户可以限定不同中断类型的不同事件。
性能监视单元还使用户能够根据中断处理的状态限定发生的事件，从而用户可以进一步收集在特定中断状态期间发生的事件。另外，性能监视单元提供以下支持：通过利用与嵌套中断相关联的计数器，使用户能够限定当嵌套中断发生时发生的事件。另外，性能监视单元还可以计数特定中断状态下诸如时钟周期等特定中断类型的条件。
应该注意：虽然已经针对全功能数据处理系统的情况描述了本发明，但是本领域技术人员应该理解本发明的过程能够以指令的计算机可读介质的形式以及各种形式进行分布，并且不管实际用来进行该分布的信号承载介质的特定类型为何，同样适用本发明。计算机可读介质的例子包括可记录类型介质，例如软盘、硬盘驱动器、RAM、CD-ROM、DVD-ROM以及传送类型介质，例如数字与模拟通信链路，使用诸如射频与光波传送等传送形式的有线或无线通信链路。计算机可读介质可以采用编码格式的形式，所述编码格式在特定数据处理系统中实际使用时被解码。
对本发明的描述出于展示与描述目的，而不是穷尽的或者限于所公开形式的本发明。对于本领域技术人员，显然存在许多修改与变化。选择与描述的实施方式以便最好地解释本发明的原理与实际应用，并且使本领域技术人员理解本发明具有适合于所设想的实际应用的各种修改的各种实施方式。
Claims (22)
1.一种用来限定当中断发生时事件的数据处理系统，包含：
性能监视单元；
一或多个位于性能监视单元内的硬件计数器；
其中所述一或多个硬件计数器计数在选定类型的中断期间的事件的发生次数。
2.如权利要求1所述的系统，其中所述一或多个硬件计数器计数在选定类型的中断的状态期间的事件的发生次数。
3.如权利要求2所述的系统，其中所述中断的状态包括：接受信号、启动中断的中断处理程序例程、完成中断处理程序例程、以及中断返回。
4.如权利要求1所述的系统，其中在中断期间计数多种类型的事件。
5.如权利要求1所述的系统，其中所述一或多个硬件计数器根据在其期间发生事件的中断类型来计数事件的发生次数。
6.如权利要求1所述的系统，其中所述事件包含时钟周期与高速缓存丢失。
7.如权利要求1所述的系统，其中第二中断中断第一中断，并且其中所述硬件计数器分离地计数在第一与第二中断期间发生的事件。
8.一种在信息处理系统上执行指令的方法，包含以下步骤：
在该系统的微处理器处，接收启动中断的信号，其中该中断包含多个状态；以及
对于该中断的多个状态中的选定状态，计数至少一个事件。
9.如权利要求8所述的方法，其中所述计数步骤包含对于中断的多个状态的每个状态的至少一个事件。
10.如权利要求8所述的方法，其中所述多个状态包含：接受信号、启动中断的中断处理程序例程、完成中断处理程序例程、以及中断返回。
11.如权利要求8所述的方法，其中所述至少一个事件包含时钟周期与高速缓存丢失。
12.如权利要求8所述的方法，其中所述计数步骤包含：对于中断的相同状态，计数多种类型的事件。
13.如权利要求8所述的方法，其中所述计数步骤由一或多个硬件计数器进行。
14.如权利要求8所述的方法，其中根据在其期间发生事件的中断类型计数事件。
15.如权利要求8所述的方法，其中第一中断由第二中断中断，并且其中硬件计数器分离地计数在第一与第二中断期间发生的事件。
16.一种用于处理指令的计算机可读介质中的计算机程序产品，该计算机程序产品包含：
第一指令，用来在系统的微处理器处，接收启动中断的信号，其中该中断包含多个状态；以及
第二指令，用来为该中断的多个状态中的选定状态，计数至少一个事件。
17.如权利要求16所述的计算机程序产品，其中所述多个状态包含：接受信号、启动中断的中断处理程序例程、完成中断处理程序例程、以及中断返回。
18.如权利要求16所述的计算机程序产品，其中所述至少一个事件包含时钟周期与高速缓存丢失。
19.如权利要求16所述的计算机程序产品，所述第二指令用来对中断的相同状态，计数多种类型的事件。
20.如权利要求16所述的计算机程序产品，其中计数步骤由一或多个硬件计数器进行。
21.如权利要求16所述的计算机程序产品，其中根据在其期间发生事件的中断类型计数事件。
22.如权利要求16所述的计算机程序产品，其中第一中断由第二中断中断，并且其中硬件计数器分离地计数在第一与第二中断期间发生的事件。
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| CN104239183A (zh) * | 2014-09-22 | 2014-12-24 | 北京国双科技有限公司 | 监测系统性能的方法及装置 |
| CN104239183B (zh) * | 2014-09-22 | 2017-10-27 | 北京国双科技有限公司 | 监测系统性能的方法及装置 |
| CN108509255A (zh) * | 2017-02-24 | 2018-09-07 | 龙芯中科技术有限公司 | 硬件中断的处理方法和装置 |
| CN108509255B (zh) * | 2017-02-24 | 2021-01-22 | 龙芯中科技术股份有限公司 | 硬件中断的处理方法和装置 |
| CN111209155A (zh) * | 2018-11-21 | 2020-05-29 | 华夏芯（北京）通用处理器技术有限公司 | 一种便于扩展和配置的性能检测方法 |
| CN111209155B (zh) * | 2018-11-21 | 2022-09-23 | 华夏芯（北京）通用处理器技术有限公司 | 一种便于扩展和配置的性能检测方法 |
| WO2023241478A1 (zh) * | 2022-06-13 | 2023-12-21 | 上海寒武纪信息科技有限公司 | 人工智能加速器流水线性能分析方法及设备 |
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| US20110106994A1 (en) | 2011-05-05 |
| TW200540612A (en) | 2005-12-16 |
| CN100383754C (zh) | 2008-04-23 |
| TWI370968B (en) | 2012-08-21 |
| US8615619B2 (en) | 2013-12-24 |
| US20050154811A1 (en) | 2005-07-14 |
| US7895382B2 (en) | 2011-02-22 |
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