CN1708812B - Improved system for programming a non-volatile memory cell - Google Patents
Improved system for programming a non-volatile memory cell Download PDFInfo
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- CN1708812B CN1708812B CN03825526XA CN03825526A CN1708812B CN 1708812 B CN1708812 B CN 1708812B CN 03825526X A CN03825526X A CN 03825526XA CN 03825526 A CN03825526 A CN 03825526A CN 1708812 B CN1708812 B CN 1708812B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0491—Virtual ground arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
Abstract
An array of dual bit dielectric memory cells comprises a plurality of bit lines. A first bit line forms a source region for each of a plurality of memory cells within a column of memory cells within the array. A second bit line forms a drain region for each of the plurality of memory cells within the column. A channel region of the opposite conductivity is positioned between the first bit line and the second bit line and forms a junction with each. A selected word line is positioned over the channel region and forms a gate over each for a plurality of memory cells within a same row. A plurality of non-selected word lines, are each parallel to the selected word line and each form a gate over one of the plurality of memory cells within the column other than the selected one of the plurality of memory cells. A word line control circuit applies a positive programming voltage to the selected word line while a bit line control circuit simultaneously applies a positive drain voltage to the drain bit line and a positive source voltage to the source bit line, the positive source voltage being less than the positive drain voltage.
Description
Technical field
The present invention relates generally to flash cell unit (flash memory cell device), more particularly, relate to the improvement that during the programming of dual bit dielectric memory cells structure, reduces the pre-charge system of short channel current electric leakage.
Background technology
Known Electrically Erasable Read Only Memory (EEPROM) type floating grid flash memory uses storage unit, it is characterized by and be provided with tunnel oxide (SiO on crystalline silicon substrate
2), at the polysilicon floating gate on the tunnel oxide, in the vertical stack of interlayer dielectric on the floating grid (being generally oxide, nitride, oxide stack form) and the control grid on interlayer dielectric.In substrate for be positioned at below this vertical stack channel region and in the source electrode and the drain diffusion regions of the opposite side of channel region.
Be injected into floating grid setting up non volatile negative charge by guide hot electrons from channel region at floating grid, and this floating grid flash cell of programming.Be accompanied by the high positive voltage of control grid, can reach thermoelectron to the source electrode bias voltage and inject by applying to drain.Grid voltage is reverse with raceway groove, and drain to source electrode bias voltage accelerated electron towards drain electrode.The electronics that quickens obtains the kinetic energy of 5.0 to 6.0 electron-volts (eV), enough crosses the Si-SiO of 3.2Ev between channel region and the tunnel oxide
2Energy barrier.When electronics quickened towards drain electrode, these electronics with lattice collisions were being controlled under the grid electric field effects again towards Si-SiO
2Interface, and obtain enough energy to cross potential barrier.
In case after having programmed, crossed grid electrode of semiconductor and the effect that increases the FET threshold voltage is arranged at the negative charge of floating grid, being characterized as of this FET has source area, drain region, channel region and control grid.During " reading " storage unit, can be by the size of electric current between source electrode and the drain electrode of flowing through in detecting under the expectant control grid voltage, and the programming of detecting storage unit and programming state not.
Developed a kind of dielectric memory cell structures recently.The cut-open view of Fig. 1 shows known dielectric memory cell array 10a to 10f.Oxide skin(coating) 24 and be positioned at the polysilicon control grid utmost point 20 on the crystalline silicon substrate 15 in the insulating tunnel layer 18 that being characterized as of each dielectric memory cell has vertical stack, charge-trapping dielectric layer 22, the insulation.Each polysilicon control grid utmost point 20 can be the part of the polysilicon word line of all storage unit 10a to 10f of extend through, and makes that all control grid 20a to 20f are electric coupling.
Be the channel region 12 that is associated with each storage unit 10 in substrate 15, this channel region 12 is positioned at the below of vertical stack.One of them of a plurality of bitline diffusion region 26a to 26g isolated each channel region 12 and the channel region 12 of adjacency.Bit line diffusions 26 forms the source area and the drain region of each storage unit 10.The ad hoc structure of this silicon channel region 12, tunnel oxide 18, nitride 22, last oxide 24 and the polysilicon control grid utmost point 20 is referred to as the SONOS device usually.
Similar to the floating grid device, SONOS storage unit 10 is injected into for example the charge-trapping dielectric layer 22 of silicon nitride by guide hot electrons from channel region 12 and programmes, and sets up non-volatile negative charge in the electric charge capture layer in being stored in nitride layer 22.Moreover, be accompanied by high positive voltage at control grid 20, can reach the purpose of thermoelectron injection to the source electrode bias voltage by applying to drain.Control grid 20 high voltage channel region 12 is reverse, and drain to source electrode bias voltage accelerated electron towards the drain region.The electronics that quickens obtains the kinetic energy of 5.0 to 6.0 electron-volts (eV), enough crosses the Si-SiO of 3.2eV between channel region 12 and the tunnel oxide 18
2Energy barrier.When electronics quickened towards the drain region, these electronics with lattice collisions were being controlled under the grid electric field effects again towards Si-SiO
2Interface, and have enough energy and cross potential barrier.Because nitride layer stores injected electrons in catching layer (or being dielectric layer), so the electronics of catching remains near in the drain charge storage region of drain region.For example, charge energy is stored in the drain bit storage area 16b of storage unit 10b.Bit line 26b act as source area and bit line 26c act as the drain region.Can apply high voltage to grid 20b and drain region 26c, and source area 26b ground connection.
Similarly, be accompanied by high positive voltage, can apply source electrode, so that thermoelectron is injected near in the source charge storage of source area to drain bias at the control grid.For example, when grid 20b and source area 26b performance high voltage, drain region 26c ground connection can be used to electronics is injected into source bit charge storaging area 14b.
In this way, the SONOS device can be used to store two data, and one source charge storage 14 (being referred to as source bit), and another is drain charge storage region 16 (being referred to as drain bit).
Because the electric charge that in fact is stored in storage area 14 only is increased in the part threshold voltage of channel region 12 of the below of storage area 14, and the electric charge that is stored in storage area 16 only is increased in the part threshold voltage of channel region 12 of the below of storage area 16, the raceway groove in zone that therefore can be by the channel region 12 between detecting storage area 14 and the storage area 16 is reverse, and reads each source bit and drain bit independently.Desire " reading " drain bit, can be with drain region ground connection and with voltage be applied to source area and a little higher voltage be applied to grid 20.In this way, the part of the channel region 12 at close source/channel joint place will can oppositely (enough not come reverse raceway groove because be relevant to grid 20 voltages of source area voltage), and the electric current of the drain/channel joint of flowing through can be used to detect the change by the caused threshold voltage of programming state of drain bit.
Similarly, desire " reading " source bit, can be with source area ground connection and with voltage be applied to the drain region and a little higher voltage be applied to grid 20.In this way, will can be not reverse near the part of the channel region 12 of drain/channel joint, and the electric current at the source/channel joint place that flows through can be used to detect the change by the caused threshold voltage of programming state of source bit.
In general flash array, when a selected storage unit was programmed, the row and column structure can have problems.Each storage unit in row is shared shared source bit line and drain bit line with another storage unit in the row.In this way, if other storage unit in row is when applying when draining to the source electrode bias voltage, electric current leaks between source bit line and drain bit line, then this electric current leaks the size that can reduce this bias voltage, thereby minimizing programmed charges, and so can cause part programming in the non-selected storage unit of sharing same bit lines unplanned, and can reduce program speed, and the consumption that increases program current.When the less memory cell structure of memory array application need, the short-channel effect of less memory cell structure increases the possibility for the punch-through of non-selected storage unit, makes us thus feeling more puzzlement for above-mentioned current leakage problem.
Therefore need a kind of system of improvement of the dual bit dielectric memory cells that is used to programme, this dual bit dielectric memory cells can not be subjected to disadvantageous short channel current leakage.
Summary of the invention
First aspect of the present invention is to provide a kind of dual bit dielectric memory cells array, and this array comprises and can reduce via sharing the programing system of program current electric leakage of the non-selected storage unit of same column with the storage unit of selecting.
This array comprises: i) first bit line of first conductive semiconductor, and it is each formation source area of the interior a plurality of storage unit of array storage unit in the array; Ii) second bit line of first conductive semiconductor, it forms drain region for each of a plurality of storage unit in the row; This second bit line and this first bit line are kept apart by the semiconductor of an opposite conductivities, and this semiconductor forms channel region for each of a plurality of storage unit in the row.
This array further comprises the word line of selecting on the channel region of one of them storage unit that is positioned at the selection that is listed as a plurality of storage unit.The word line of this selection further form in the array with the storage unit of selecting at each grid with a plurality of storage unit of delegation.Each of many non-selected word lines forms grid on one of them of a plurality of non-selected storage unit in row, each of above-mentioned non-selected word line is parallel to the word line of selection.
This array further comprises the array control circuit, and this array control circuit comprises bit line control circuit, Word line control circuit and substrate potential control circuit.During the drain charge trapping region of the storage unit that programming is selected, Word line control circuit can apply a positive program voltage in the word line of selecting.Relevant therewith, bit line control circuit can apply: i) positive drain voltage is to drain bit line; Ii) a positive source voltage is to source bit line, and positive source voltage is less than positive drain voltage.
The positive source voltage size can be 1/10 and positive drain voltage of positive drain voltage 3/10 between.Perhaps can stipulate a narrower range, positive source voltage can be 1/10 and positive drain voltage of positive drain voltage 2/10 between.
This array can further comprise the resistor that is connected between bit line control circuit and the ground connection.In this situation, bit line control circuit can connect source bit line to resistor, so the voltage that this positive source voltage is equal to via resistor increases.
In conjunction with applying positive program voltage in the word line of selecting, Word line control circuit can further provide and be used for applying negative bias and be pressed on non-selected word line.Negative bias can be between-0.1 volt and-2.0 volts.Perhaps can stipulate a narrower range, negative bias can be between-0.5 volt and-1.0 volts.
Apply positive program voltage in the word line of selecting in conjunction with Word line control circuit, the substrate voltage control circuit can provide and be used for applying negative substrate voltage in substrate.Negative substrate voltage can be between-1.0 volts and-2.0 volts.Perhaps can stipulate a narrower range, negative substrate voltage can be between-0.5 volt and-1.0 volts.
Second aspect of the present invention is to provide the method for the charge storaging area of selected dual bit dielectric memory cells in a kind of array that electric charge is programmed into dual bit dielectric memory cells.This array comprises many parallel bit lines, it is formed for the source electrode and the drain electrode of each storage unit, with many parallel wordlines, it is formed for the grid of each storage unit, this method comprises: i) apply positive drain voltage in first bit line, this first bit line forms drain electrode with channel region and engages, and this first bit line is positioned at the right side of channel region; Ii) in conjunction with applying positive drain voltage in first bit line, and apply positive source voltage in second bit line, this second bit line forms source electrode with the channel region of the storage unit of selection and engages, and this positive source voltage is less than this positive drain voltage, and channel region is the right side at second bit line; Iii) combination applies positive drain voltage in this first bit line, and applies positive program voltage in wherein word line of selecting, and wherein word line of this selection is the word line that forms the grid of selected storage unit.
Positive source voltage can be between 1/10 positive drain voltage and 3/10 positive drain voltage.Perhaps can stipulate a narrower range, positive source voltage can be between 1/10 positive drain voltage and 2/10 positive drain voltage.
This method can further be included in and connect a resistor between source bit line and the ground connection.In the case, positive source voltage equals to increase via the voltage of resistor.
This method can further comprise in conjunction with this Word line control circuit and applies positive program voltage in the word line of selecting, and is pressed on non-selected word line and apply negative bias.Negative bias can be between-0.1 volt and-2.0 volts.Perhaps can stipulate a narrower range, negative bias can be between-0.5 volt and-1.0 volts.
This method can further comprise in conjunction with this Word line control circuit and apply positive program voltage in the word line of selecting, and applies negative substrate voltage in substrate.Negative substrate voltage can be between-0.1 volt and-2.0 volts.Perhaps can stipulate a narrower range, negative substrate voltage can be between-0.5 volt and-1.0 volts.
In order to understand the present invention and others of the present invention and further purpose better, can be with reference to following explanation, and engage its accompanying drawing.Protection scope of the present invention is by the claims scope definition.
Description of drawings
Fig. 1 is the cross sectional representation of the known dielectric memory cell array of prior art;
Fig. 2 is the schematic block diagram of dielectric memory cell array according to an embodiment of the invention;
Fig. 3 is the cross sectional representation of the dielectric memory cell array of Fig. 2; And
Fig. 4 is the state machine diagram of the exemplary operations of expression array control circuit.
Embodiment
Describe the present invention in detail referring now to accompanying drawing.These accompanying drawings are not proportionally drawn, and the size of some fine structures shows for clear, and painstakingly draw greatlyyer.
Fig. 2 is an embodiment who shows dual bit dielectric memory cells array 40 with the form of block scheme.Array 40 comprises a plurality of dual bit dielectric memory cells 48, array control circuit 61 and is manufactured in current sensing circuit 66 on the crystal semiconductor substrate.The array configurations of dual bit dielectric memory cells 48 becomes matrix format, has the horizontal line of polysilicon word line 210 to 213 and the vertical row of alternate-bit-line diffusion region 200 to 205, and channel region 50 (see figure 3)s in substrate 42.Each storage unit 48 in row is shared the two identical bit lines that are adjacent to each cell channel zone, and this bit line engages with each memory cell channel regions formation.Each storage unit 48 in delegation be expert in another storage unit share identical word line 210 to 213.
Referring now to the cross-sectional view of row of expression dual bit dielectric memory cells, as Fig. 3 in conjunction with shown in Figure 2, these dual bit dielectric memory cells shared word line 211.Should be appreciated that polysilicon word line 211 is configured to form the control grid 60 of each storage unit 48 in this row.Bitline diffusion region 200 to 206 has opposite semiconductor electric conductivity with each channel region 50, and makes bitline diffusion region 200 to 206 be formed on the source area and the drain region of each storage unit in the row.In the example of NMOS device, channel region 50 is such as the slight for example p N-type semiconductor N of the silicon metal of the hole donors impurity of boron of having implanted, and bitline diffusion region 200 to 206 is such as having implanted for example n N-type semiconductor N of the silicon metal of electron donor's impurity of arsenic.
Above channel region 50 is first insulative barriers or the tunnel layer 54 that can comprise silicon dioxide.The thickness of tunnel layer 54 can be about 50 to the scope of about 150 dusts.Having more, the embodiment of close limit comprises that the thickness of tunnel layer 54 can be about 60 to the scope of about 90 dusts.Even narrower range, the thickness of tunnel layer 54 can be about 70 to the scope of about 80 dusts.
Above tunnel layer 54 is an electric charge capture layer 56, this electric charge capture layer 56 comprises source electrode charge-trapping district or source bit 62, with drain electrode charge-trapping district or drain bit 64, respectively be used for storing expression and do not plan a neutral charge of state or the negative charge that state has been planned in expression.Electric charge capture layer 56 can comprise the nitride with suitable charge-trapping character, and can have the thickness size of 20 to 100 dusts.In exemplifying embodiment, the optional free Si of nitride
2N
4, Si
3N
4And SiOxN
4In the group of being formed.
It on electric charge capture layer 56 upper dielectric layer 58.Upper dielectric layer 58 can be a silicon dioxide, maybe can be to have the material of electric medium constant greater than the electric medium constant of silicon dioxide (for example, high K value material).In a preferred embodiment, high K value material can be to be selected from Al
2O
3, HfSi
xO
y, HfO
2, ZrfO
2And ZrSi
xO
yAmong the group who is formed, and the material of other similar high dielectric constant.If upper dielectric layer 58 is a silicon dioxide, then layer 58 can have the thickness size of 60 to 100 dusts.Perhaps, if above-mentioned dielectric layer 58 is the material of high dielectric constant, then its electric thickness can be the magnitude at 60 dust to 100 dusts, and its actual (real) thickness can be in the scope of about 70 to 130 dusts.Have more the embodiment of close limit and comprise that upper dielectric layer 58 has thickness about 80 to the scope of about 120 dusts, and even narrower range, the thickness of upper dielectric layer 58 is approximately 90 to about 100 dusts.
On this upper dielectric layer 58, be word line 211, form grid 60 on each storage unit in this word line 211 is expert at.In the exemplary embodiment, grid 60 can comprise the polysilicon with thickness 4,000 dust magnitudes.Word line 211 is connected to Word line control circuit 46.
Array control circuit 61 comprise Word line control circuit 46, bit line control circuit 44, substrate voltage control circuit 45, voltage divider 65, to the connection of positive operating power (Vc) 70, to negative operating power (Vc) 71 connection, and to the connection on ground 68.In operation, the operation of array control circuit is optionally to be connected to the voltage that is provided by voltage divider 65 with each word line 210 to 213, each bit line 200 to 206 and substrate 42, or be connected to ground (maybe this word line 210 to 213 or bit line 200 to 206 and all voltage source or ground connection are isolated, thereby when making its current potential only construct mutual electro ultrafiltration just effectively) with other of array 40.Connection is with each the source electrode charge-trapping district 62 in array 40 and each drain electrode charge-trapping district 64 can be wiped free of, optionally programming reaches the mode that optionally reads.The array control circuit is also operated with bit line that connect to select to current sensing circuit 66, and make electric current on the bit line to measure selection, with the source electrode charge-trapping district 62 of the selection of the storage unit of indication in the array storage unit or the programming state in drain electrode charge-trapping district 64, the bit line of this selection is source electrode or drains one of them in this array storage unit.
Current sensing circuit 66 can use known circuit to come electric current on the selected bit line of sensing, and the bit line of this selection is connected to current sensing circuit 66 by bit line control circuit 44.When applicable current potential is connected to applicable word line and bit line by array control circuit 61, when being used for reading the charge-trapping district of selection, the electric current of sensing is represented selected one of them the state of programming in source electrode charge-trapping district 62 or drain electrode charge-trapping district 64, and this will be described in more detail hereinafter.
The array control circuit
In conjunction with Fig. 2 and shown in Figure 3 with reference to Fig. 4, array control circuit 61 operates in three states simply: programming state 76, and wherein electric charge optionally is stored in the source electrode charge-trapping district 62 or the drain electrode charge-trapping district 64 of selected one of them storage unit 48; Reading state 78, wherein charge stored detects from the source electrode charge-trapping district 62 or the drain electrode charge-trapping district 64 of one of them storage unit 48 of selection, is stored in the data in this charge-trapping district originally to regenerate; And erase status 74, wherein promptly before the programming state 76 of programming again, wipe the electric charge in the charge-trapping district 62 and 64 that is stored in one or more storage unit.
Programming state
When at programming state 76, electronics is injected into the charge-trapping district 64 that drains that programme, drain electrode charge-trapping district 64 by using the thermoelectron implantttion technique.Specifically, when applying high voltage when controlling grid 60, array control circuit 61 is connected to various current potentials (for example, by voltage divider 65 power supply and ground connection 68) with bit line 200 to 206, word line 210 to 213 and substrate 42, so that high draining to the source electrode bias voltage to be provided.For example, with reference to one of them storage unit 48 of selecting (for example, the storage unit of selecting 49), can will represent that the bit line 201 of the source area of the storage unit 49 selected is connected to ground 68 by bit line control circuit 44, be connected to from the program voltage of about 5 volts voltage divider 65 with the bit line 202 of the drain region of the storage unit 49 that will represent by bit line control circuit 44 to select, and finish aforementioned work.
Simultaneously, the word line 211 that Word line control circuit 46 will represent to control the selection of grid 60 is connected to from the word line program voltage 220 of the selection of about 10 volts voltage divider 65, and can be (for example with non-selected word line, be not other word line of the word line 211 selected) be connected to little negative bias 221, to prevent by leaking with breakdown current that the storage unit of selecting 49 is shared the non-selected storage unit of identical row.At the voltage of control on the grid 60 that channel region 50 is reverse, and height drains to the source electrode bias voltage and attracts and accelerated electron enters channel region 50 from source area 201 and 202 moves towards the drain region simultaneously.
When electronics quickens towards drain region 52,4.5eV to the 5eV kinetic energy gain of electronics enough overcomes 3.1eV to the 3.5eV energy barrier at channel region 52/ tunnel layer 54 interfaces of the storage unit of selecting 49, will reboot electronics by the caused electric field of high voltage on the control grid 60 of the storage unit of selecting 49 and move towards the drain electrode charge-trapping district 64 of the storage unit of selecting 49.These stride across the electronics in drain electrode charge-trapping district 64 that the interface enters the storage unit 49 of selection and keep catching in the charge storing unit of the selection of catching is caught floor 56b, in order to the usefulness that read afterwards.
Similarly, by thermoelectron being injected the source electrode charge-trapping district 62 that programmes, source electrode charge-trapping district 62.Specifically, when applying high voltage when controlling grid 60, array control circuit 61 is connected to various current potentials (for example, by voltage divider 65 power supply and ground connection 68) with bit line 200 to 206, word line 210 to 213 and substrate 42, so that provide high source electrode to drain bias.For example, again with reference to the storage unit of selecting 49, can will represent that the bit line 202 of the drain region of the storage unit 49 selected is connected to ground 68 by bit line control circuit 44, be connected to from the program voltage of about 5 volts voltage divider 65 with the bit line 201 of the source area of the storage unit 49 that will represent to select, and finish this work.Similarly, the word line 211 that Word line control circuit 46 will represent to control the selection of grid 60 is connected to from the word line program voltage of the selection of about 10 volts voltage divider 65, and can be (for example with non-selected word line, be not other word line of the word line 211 selected) be connected to little negative bias, to prevent by leaking with breakdown current that the storage unit of selecting 49 is shared the non-selected storage unit of identical row.At the voltage of control on the grid 60 that the channel region 50 of the storage unit 49 selected is reverse, this moment, high source attracted and accelerated electron 202 enters channel region towards source area 201 from the drain region to drain bias.
Moreover, when electronics quickens towards source area 201,4.5eV to the 5eV kinetic energy gain of electronics enough overcomes 3.1eV to the 3.5eV energy barrier at channel region 50/ tunnel layer 54 interfaces of the storage unit of selecting 49, will reboot electronics by the caused electric field of high voltage on the control grid 60 and move towards the source electrode charge-trapping district 62 of the storage unit of selecting 49.
As discussed above, if other the non-selected storage unit in row (for example, share the storage unit of same bit lines 201 and 202) leakage current during programming, then leakage current can reduce the magnitude of program bias and reduce the accuracy of program bias magnitude, cause the unexpected part programming of non-select storage unit, so reduce program speed, and increased program current.
Three embodiment at this expression programing system.Each embodiment provides minimizing by leaking with electric current that the storage unit of selecting 49 is shared the non-selected storage unit 48 of identical row.Though these three embodiment are the relevant drain charge storage region 64 (among Fig. 3) that are used for programming, should be appreciated that can be by the reference of exchange to source bit line and drain bit line, this same system source charge storage 62 that can be used to programme.
First embodiment applies little positive source electrode program bias to source bit line during being illustrated in programming.Specifically, refer again to the storage unit 49 of selection, bit line control circuit 44 will represent that the bit line 201 of the source area of the storage unit 49 selected is connected to the little positive source electrode program bias of coming from voltage divider, and will represent that the bit line 202 of drain region of the storage unit 49 of selection is connected to from the program voltage of about 5 volts voltage divider 65.Substrate 42 is connected to ground 68.Simultaneously, the word line 211 that Word line control circuit 46 will represent to control the selection of grid 60 is connected to from the word line program voltage of the selection of about 10 volts voltage divider 65, and non-selected word line (for example, not being other word line of the word line 211 selected) is connected to little negative bias.
Little positive source electrode program bias is less than the program voltage that is connected to the drain region.Specifically, positive source electrode program bias can be applied to the drain region program voltage 1/10 to 2/10 between.
Simply with reference to Fig. 2, as this bit line control circuit 44 source area is connected to from the substituting of the little positive program bias of voltage divider 65, this bit line control circuit 44 can comprise resistor, this resistor is connected between ground connection 68 and the bit line 201 of representing source area.So, when program current was flowed through between source area 201 and the ground connection 68, resistor was operating as a voltage divider, and the positive potential with source area 201 is equal to the voltage of crossing over resistor to be increased.
Substrate control circuit 45 applied little substrate program bias to substrate 42 during second embodiment was illustrated in programming.Specifically, again with reference to the storage unit of selecting 49, bit line control circuit 44 will represent that the bit line 201 of the source area of the storage unit 49 selected is connected to ground 68 and will represent that the bit line 202 of drain region of the storage unit 49 of selection is connected to from the program voltage of about 5 volts voltage divider 65.Simultaneously, substrate control circuit 45 is connected to little substrate program bias with substrate 42.The word line 211 that Word line control circuit 46 will represent to control the selection of grid 60 is connected to from the word line program voltage of the selection of about 10 volts voltage divider 65, and non-selected word line (for example, not being other word line of the word line 211 of selection) can be connected to little negative bias.
Little substrate program bias can be the negative voltage between-0.1 volt and-2.0 volts.For narrower range, little substrate program bias can be between-0.5 volt and-1.0 volts.
The 3rd embodiment represents that first embodiment and second embodiment's is comprehensive, and make: substrate control circuit 45 applies little substrate program bias to substrate 42 and bit line control circuit 44 and will represent that during programming the bit line 201 of the source area of the storage unit 49 selected is connected to the little positive source electrode program bias of coming from voltage divider during programming.This substrate program bias and little positive source electrode program bias can be in the scope about first embodiment and second embodiment discussion.Moreover, can use above-mentioned resistor circuit to apply positive source electrode program bias.
Erase status
When at erase status 74, the array control circuit can be connected to applicable current potential with applicable bit line 200 to 206 and word line 72, and make can maybe will be from the electrons tunnel of electric charge capture layer 56 to grid 60 or to substrate by the hot hole implantttion technique, and wipes the source electrode charge-trapping district 62 and the drain electrode charge-trapping district 64 of a plurality of storage unit.These two kinds of technology are known technology.
Reading state
When at reading state 78, the existence of detecting trapped electrons (for example, negative charge is represented programming state) in source electrode charge-trapping district of selecting 62 or drain electrode charge-trapping district 64.The trapped electrons of known existence in source electrode charge-trapping district 62 or drain electrode charge-trapping district 64 has influenced the stored charge in the channel region 50 below these charge-trapping districts.In this case, the trapped electrons of the existence in source electrode charge-trapping district 62 or the drain electrode charge-trapping district 64 has influenced the threshold voltage of field-effect transistor (FET), and being characterized as of this field-effect transistor have control grid 60, act as the bitline diffusion region 200 to 206 of source area and act as the bitline diffusion region 200 to 206 of drain region.Therefore, the every of double places memory cell 48 can be " read ", or more particularly, the existence of the electronics of storage in each source electrode charge-trapping district 62 and the drain electrode charge-trapping district 64 can be detected by operation FET.
Especially, can be by applying positive voltage to controlling grid 60 and less positive voltage to the bit line 202 that act as the drain region, and the bit line 201 that will act as source area is connected to ground 68, and the existence of detecting stored electrons in source electrode charge-trapping district 62.Measure electric current at the bit line 201 that act as source area or at the bit line 202 that act as the drain region then.If in source electrode charge-trapping district 62, the electronics of catching is arranged, and supposition have suitable voltage and threshold value can be used for measuring (with supposition not from leaking with the electric current of the storage unit of selecting 49 with the storage unit 48 of the adjacency in the delegation, with supposition not from the storage unit 49 same row of selecting in the electric current of storage unit 48 leak), then do not measure measurable electric current at the bit line 202 that comprises the drain region.Otherwise, if source electrode charge-trapping district 62 is that electric neutrality (electronics of for example, not catching) then has measurable electric current to flow to the bit line that act as the drain region.Similarly, available identical method detecting be stored in the existence of the electronics in the drain electrode charge-trapping district 64 and only acting in opposition be the bit line of source area and the bit line that act as the drain region.
Known recognizing, can influence the correctness that reads from sharing the electric current leakage that the non-selected storage unit of same row comes with the storage unit of selecting, therefore array control circuit 61 can apply the bit line that is biased in non-selected word line and/or forms the source area of row, to prevent this leakage.
Word line control circuit 46 according to the present invention now will be discussed apply the exemplary operations that is biased in the storage unit that reads selection.With reference to Fig. 3, when the source electrode charge-trapping district 62 of the storage unit 49 that reads selection, Word line control circuit 46 is connected to the word line of selecting 211 and just reads voltage from 10 volts of sizes of voltage divider 65, and (for example with non-selected word line, all word lines except selected word line) be connected to the bias voltage that reads, leak by the breakdown current of sharing the storage unit of same row with the storage unit of selecting so that prevent from voltage divider 65.Reading bias voltage can be negative voltage.Specifically, reading bias voltage can be-0.1 volt to-2.0 volts negative voltage; Or narrower range, as-0.1 volt to-0.5 volt negative voltage; Or narrower range, as-0.1 volt to-0.2 volt negative voltage.
Then, be used to apply voltage to the exemplary operation of bit line with discussing with the bit line control circuit 44 of the storage unit that reads selection according to of the present invention.With reference to Fig. 2, during the source electrode charge-trapping district of the storage unit of for example selecting when the storage unit that reads selection 49, bit line control circuit 44 will represent that the bit line 201 of the source area of the storage unit 49 selected is connected to from the source voltage of voltage divider 65, and the bit line 202 that will represent the drain region of the storage unit 49 selected be connected to from the positive drain voltage of voltage divider 65 be connected to current sensing circuit 66.This drain voltage can be less than or equal to the voltage that reads of the word line that is applied to selection.This source voltage can ground connection maybe can be the little positive voltage between 0.0 volt to 1.0 volts, so that reduce by leaking with breakdown current that the storage unit of selecting 49 is shared the non-selected storage unit 48 of identical row.
The leakage current that the storage unit of known vicinity from the row identical with the storage unit of selecting is come can influence correct reading, bit line control circuit 44 can recharge next bit lines that is designated as number 203 on drain bit line the right with little positive voltage, to prevent this leakage.
Perhaps, when only being influenced by the face that connects with each channel region 50 of opposite side of bit line 203, bit line control circuit 44 can be isolated bit line 203 and be made its current potential to float, and next bit lines (being called bit line 204) on bit line 203 the right can be connected to from the precharge voltage of voltage divider 65, make control grid 60 is neutral bias voltages and is positive bias about this source bit line.Can imagine various other combinations of floating bitline and pre-charge bit line, so that reduce electric current leakage by the storage unit of the row shared identical with the storage unit of selecting.
In sum, be used for programming the method in charge-trapping district of dual bit dielectric memory cells of the present invention owing to reduced by leaking with electric current that the storage unit of selecting is shared other storage unit of identical row, so can use less program current, thereby quicker and more accurate programming is provided.Though the present invention has done to show and explanation that clearly, those skilled in the art can make some equivalent substitutions and modifications to it after reading and understanding this instructions about some preferred embodiment.For example, though shown memory cell array is the general plane structure that is formed on the silicon substrate, but should recognize that teaching of the present invention can be applicable to that plane, fin-shaped form and other can be fit to be formed at dielectric memory cell structures on the semiconductor substrate, this semiconductor substrate for example can comprise: buik silicon semiconductor substrate, silicon-on-insulator semiconductor substrate, silicon on sapphire (SOS) semiconductor substrate and be known in the art be formed at semiconductor substrate on other material.The present invention will comprise all these equivalent substitutions and modifications, and only be subjected to the restriction of following claim scope.
Claims (10)
1. the array of a dual bit dielectric memory cells, this array comprises:
First bit line of first conductive semiconductor, this first bit line are formed in this array each source area of a plurality of storage unit in the array storage unit;
Second bit line of first conductive semiconductor, this second bit line is formed for each drain region of this a plurality of storage unit in these row, this second bit line and this first bit line are separated with the semiconductor with opposite conductivities, and the semiconductor of this opposite conductivities is formed for each channel region of a plurality of storage unit in these row;
The word line of selecting, it is positioned on the channel region of storage unit of one of them selection of a plurality of storage unit of these row, and further is formed for each grid of a plurality of storage unit in the row with selected storage unit identical array;
Many non-selected word lines, each bar is parallel to the word line of selection, and each bar one of them of a plurality of storage unit in row is not to be formation one grid above one of them storage unit of having selected of these a plurality of storage unit;
Word line control circuit, it is used for:
Apply a positive program voltage to the word line of selecting;
Bit line control circuit is used for applying the word line of this positive program voltage to this selection in conjunction with this Word line control circuit, and applies:
Positive drain voltage is to this drain bit line; And
Positive source voltage is to this source bit line, and this positive source voltage is less than this positive drain voltage.
2. the array of dual bit dielectric memory cells according to claim 1 further comprises:
Resistor, it is connected between this bit line control circuit and the ground connection; And
Wherein this bit line control circuit will connect this source bit line and be connected to this resistor, and this positive source voltage equals the voltage that increases via this resistor thus.
3. the array of dual bit dielectric memory cells according to claim 1, wherein this Word line control circuit further provides and is used for:
Apply positive program voltage in the word line of selecting in conjunction with this Word line control circuit, be pressed on non-selected word line and apply negative bias.
4. the array of dual bit dielectric memory cells according to claim 3, wherein this negative bias is between-0.1 volt to-2.0 volts.
5. the array of dual bit dielectric memory cells according to claim 4, wherein this negative bias is between-0.5 volt to-1.0 volts.
6. the array of dual bit dielectric memory cells according to claim 1 further comprises the substrate voltage control circuit, is used for applying positive program voltage in the word line of selecting in conjunction with this Word line control circuit, and applies negative substrate voltage in substrate.
7. the array of dual bit dielectric memory cells according to claim 6 wherein should be born substrate voltage between-0.1 volt to-2.0 volts.
8. the array of dual bit dielectric memory cells according to claim 7 wherein should be born substrate voltage between-0.5 volt to-1.0 volts.
9. the array of dual bit dielectric memory cells according to claim 1, wherein this positive source voltage is between 1/10 positive drain voltage and 3/10 positive drain voltage.
10. the array of dual bit dielectric memory cells according to claim 9, wherein this positive source voltage is between 1/10 positive drain voltage and 2/10 positive drain voltage.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/307,667 US6795342B1 (en) | 2002-12-02 | 2002-12-02 | System for programming a non-volatile memory cell |
| US10/307,667 | 2002-12-02 | ||
| PCT/US2003/023085 WO2004051667A1 (en) | 2002-12-02 | 2003-07-24 | Improved system for programming a non-volatile memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1708812A CN1708812A (en) | 2005-12-14 |
| CN1708812B true CN1708812B (en) | 2011-11-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN03825526XA Expired - Fee Related CN1708812B (en) | 2002-12-02 | 2003-07-24 | Improved system for programming a non-volatile memory cell |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US6795342B1 (en) |
| EP (1) | EP1568043B1 (en) |
| JP (1) | JP4252536B2 (en) |
| KR (1) | KR100957830B1 (en) |
| CN (1) | CN1708812B (en) |
| AU (1) | AU2003273222A1 (en) |
| DE (1) | DE60317930T2 (en) |
| TW (1) | TWI320182B (en) |
| WO (1) | WO2004051667A1 (en) |
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| US7133317B2 (en) * | 2004-11-19 | 2006-11-07 | Macronix International Co., Ltd. | Method and apparatus for programming nonvolatile memory |
| US7269067B2 (en) * | 2005-07-06 | 2007-09-11 | Spansion Llc | Programming a memory device |
| US20070166971A1 (en) * | 2006-01-17 | 2007-07-19 | Atmel Corporation | Manufacturing of silicon structures smaller than optical resolution limits |
| US20070166903A1 (en) * | 2006-01-17 | 2007-07-19 | Bohumil Lojek | Semiconductor structures formed by stepperless manufacturing |
| US7630253B2 (en) * | 2006-04-05 | 2009-12-08 | Spansion Llc | Flash memory programming and verification with reduced leakage current |
| US7394702B2 (en) * | 2006-04-05 | 2008-07-01 | Spansion Llc | Methods for erasing and programming memory devices |
| US7606076B2 (en) * | 2007-04-05 | 2009-10-20 | Sandisk Corporation | Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise |
| US20080247253A1 (en) * | 2007-04-05 | 2008-10-09 | Hao Thai Nguyen | Non-volatile storage with temperature compensation for bit line during sense operations |
| KR100932368B1 (en) * | 2007-11-21 | 2009-12-16 | 주식회사 하이닉스반도체 | How flash memory devices work |
| JP2009157975A (en) * | 2007-12-25 | 2009-07-16 | Spansion Llc | Semiconductor device and control method thereof |
| US7672175B2 (en) * | 2008-01-11 | 2010-03-02 | Qualcomm Incorporated | System and method of selectively applying negative voltage to wordlines during memory device read operation |
| US7787294B2 (en) * | 2008-02-14 | 2010-08-31 | Macronix International Co., Ltd. | Operating method of memory |
| US7719902B2 (en) * | 2008-05-23 | 2010-05-18 | Sandisk Corporation | Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage |
| US8383443B2 (en) | 2010-05-14 | 2013-02-26 | International Business Machines Corporation | Non-uniform gate dielectric charge for pixel sensor cells and methods of manufacturing |
| KR20130104270A (en) * | 2012-03-13 | 2013-09-25 | 삼성전자주식회사 | Split gate type nonvolatile memory device and semiconductor device with embedded split gate type nonvolatile memory device |
| US20140233339A1 (en) * | 2013-02-18 | 2014-08-21 | Spansion Llc. | Apparatus and method to reduce bit line disturbs |
| US9582349B1 (en) * | 2014-08-20 | 2017-02-28 | Altera Corporation | Methods and apparatus for detecting memory bit corruption on an integrated circuit |
| CN111968691B (en) * | 2020-08-23 | 2022-10-28 | 南京优存科技有限公司 | Programming method and device for memory array |
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- 2003-07-24 AU AU2003273222A patent/AU2003273222A1/en not_active Abandoned
- 2003-07-24 WO PCT/US2003/023085 patent/WO2004051667A1/en active IP Right Grant
- 2003-07-24 DE DE60317930T patent/DE60317930T2/en not_active Expired - Lifetime
- 2003-07-24 CN CN03825526XA patent/CN1708812B/en not_active Expired - Fee Related
- 2003-07-24 EP EP03755728A patent/EP1568043B1/en not_active Expired - Fee Related
- 2003-07-24 KR KR1020057009919A patent/KR100957830B1/en not_active IP Right Cessation
- 2003-09-03 TW TW092124292A patent/TWI320182B/en not_active IP Right Cessation
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Also Published As
| Publication number | Publication date |
|---|---|
| KR100957830B1 (en) | 2010-05-13 |
| AU2003273222A1 (en) | 2004-06-23 |
| JP2006508490A (en) | 2006-03-09 |
| WO2004051667A1 (en) | 2004-06-17 |
| CN1708812A (en) | 2005-12-14 |
| EP1568043B1 (en) | 2007-12-05 |
| TWI320182B (en) | 2010-02-01 |
| EP1568043A1 (en) | 2005-08-31 |
| TW200414208A (en) | 2004-08-01 |
| JP4252536B2 (en) | 2009-04-08 |
| KR20050085268A (en) | 2005-08-29 |
| DE60317930D1 (en) | 2008-01-17 |
| US6795342B1 (en) | 2004-09-21 |
| DE60317930T2 (en) | 2008-11-13 |
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