CN1716554A - 一种p型mosfet的结构及其制作方法 - Google Patents

一种p型mosfet的结构及其制作方法 Download PDF

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CN1716554A
CN1716554A CNA2005100789757A CN200510078975A CN1716554A CN 1716554 A CN1716554 A CN 1716554A CN A2005100789757 A CNA2005100789757 A CN A2005100789757A CN 200510078975 A CN200510078975 A CN 200510078975A CN 1716554 A CN1716554 A CN 1716554A
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朱慧珑
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明通过下述方法形成了p型MOSFET：用绝缘体覆盖栅并在侧壁之外沉积含锗层，然后通过退火或氧化使锗扩散到硅上绝缘体层或体硅中以形成渐变掩埋硅－锗源－漏和/或扩展(geSiGe－SDE)。对于SOI器件来说，geSiGe－SDE可以达到掩埋绝缘体以使SOI器件的沟道中的压力最大化，这对于超薄SOI器件来说是有利的。渐变锗分布提供了优化应力以提高器件性能的方法。geSiGe－SDE在PMOSFET的沟道中在水平方向(平行于栅电介质表面)上产生压应力，在垂直方向(垂直于栅电介质表面)上产生张应力，从而形成提高PMOSFET性能的结构。

Description

一种P型MOSFET的结构及其制作方法
技术领域
本发明一般涉及半导体制作和集成电路制造领域。更特定地，本发明涉及具有应变硅以获得高性能的互补金属氧化物半导体(CMOS)场效应晶体管(FET)及其制作方法。
背景技术
由于通过持续的比例缩放来改善金属氧化物半导体场效应晶体管(MOSFET)的性能已经变得日益困难，提高MOSFET性能而又无需比例缩放的方法变得重要起来。因此，在当代CMOS技术中，对于用于FET沟道的应变材料的使用有着重大的兴趣和工作。
在一种方法中，利用硅-锗合金(SiGe)来形成表面沟道应变Si/驰豫SiGe n型MOSFET(NMOSFET或NFET)。在该方法中，在非常薄的外延Si层中引入双轴张应变。张应变减小了电子有效质量，提高了电子迁移率。
在p型MOSFET(PMOSFET或PFET)情形中，为了有效提高空穴迁移率，锗(Ge)的浓度必须大于大约30％。
这一方法具有下列缺点：
1)应变硅生长在驰豫SiGe上，因此难以控制器件漏电。
2)为了提高性能所要的超过30％锗浓度的要求进一步提高了缺陷密度。
3)SiGe中杂质——例如砷和磷——的高扩散性使得难以形成浅p-n结。对于亚微米或深亚微米MOSFET来说，要缩小器件尺寸，就需要浅的结。
因此，需要一种制作电路的方法，这样的电路具有应变硅的好处而又没有先有技术的低产率特性。
发明内容
本发明涉及形成PMOSFET的方法，此PMOSFET在其沟道上具有压应力，从而提高空穴迁移率。
本发明的一个特征在于通过在硅晶格中将成为源和漏的区域中引入锗而在集成电路的选定区域中引入了压应力。
本发明的一个特征在于使用具有渐变掺锗源/漏和/或扩展用以产生由SiGe外延层提供的应变的PMOSFET。由于渐变锗分布在SiGe和Si之间不具有明晰的界面(位错产生处)，不容易产生位错。这能够减小位错导致的器件漏电。渐变锗分布还给出了优化应力以提高器件性能的方法。本发明的另一特征在于锗在SOI层中的完全或部分穿透以在SOI层中形成SiGe区域。
本发明的另一特征在于在退火驱动的扩散和/或氧化过程驱动的扩散之间进行选择。
附图说明
图1示出用本发明某一方案形成的结构。SOI PMOSFET结构，其中渐变SiGe源/漏(SD)延伸至掩埋绝缘层。
图2示出用本发明第二方案形成的结构。SOI PMOSFET结构，其中渐变SiGe SD没有延伸至掩埋绝缘层。
图3示出用本发明第三方案形成的结构。体PMOSFET结构，具有渐变SiGe SD。
图4示出形成图1的结构的最初步骤。
图5示出对栅堆叠进行构图。
图6示出形成外延掺杂层。
图7示出将锗扩散进硅SOI层中之后的结构。
图8示出的结构是图7所示结构的一个替代。
图9示出图8的步骤之后的步骤。
具体实施方式
图1以剖面图示出形成在硅晶片10的某一部分中的简化场效应晶体管100，该晶体管具有掩埋绝缘层20和硅或半导体(或SOI层)器件层30。晶体管的栅110和侧壁105位于限定主体30侧向范围的栅氧化物103之上。源和漏40由SOI层30的在前一步骤中已掺了锗的部分形成。锗向下扩散到绝缘层30并向内扩散到栅之下的沟道的中间。这在SOI层中在水平方向(平行于SOI表面)上引入了压应力，并在器件中心在垂直方向(垂直于SOI表面)上引入了张应力。这些部分完成了场效应晶体管，示例性地，具有形成用于p型场效应晶体管(PMOSFET)的沟道的n型主体。
示出PFET作为例子。典型地，在当前的技术中，电路会用到CMOS技术，包括NMOSFET和PMOSFET。
示例性地，晶片为市场上可以买到的SIMOX(氧注入隔离)工艺制作的晶片。也可以使用其它制作晶片的方法。
回头看图1，在栅两侧的源和漏40具有锗的渐变，在顶部具有最大值，往下到BOX(掩埋氧化物)层20有量级上的减小。这是由锗从上层SiGe或锗向硅SOI层扩散而导致的。也可以进行锗的注入，但是这对于大多数应用来说是不能令人满意的，因为这需要太长的时间来注入所需的剂量。另外，典型剂量的锗注入将会导致重大的难以消除的晶体损伤。
利用外延步骤来进行SiGe层的沉积的一个好处在于外延沉积是选择性的，只在裸露的硅上沉积SiGe。这减少了清除的总量，而这样的清除对于在器件上所有地方(例如栅、隔离和SD)沉积SiGe或Ge的情形来说是必要的。
扩散工艺可以进行足够长的时间以相当均匀地分布锗浓度，或者可以在时间上进行限制从而从SOI层顶部到底部具有显著的浓度渐变。
硅晶格中锗的存在会在图中从左往右延伸的源和漏中产生压应力。这一应力反过来在SOI中在水平方向(平行于SOI表面)上产生压应力以及在器件100的沟道中在垂直方向(垂直于SOI表面)上产生张应力。
SOI中水平方向上的压应力和器件沟道中垂直方向上的张应力都会提高空穴迁移率从而提高PMOSFET性能。
优选地，锗的浓度从顶部到底部渐变——即，从时间上限制扩散从而锗不会均匀地分布于层30中，尤其是不会蔓延到器件的沟道区域中。浓度在顶部具有最大值并下降到某一杂质深度，这一深度小于SOI层的厚度。这一渐变相对于陡峭的分布来说在晶体结构中产生更少的位错。
现在参看图4，示出用于本发明实施例的起始材料，其中衬底承载BOX 20，之上是SOI层30。
在当代技术中，层30的厚度可以在5-100nm范围内。这么薄的层很难用传统方法来进行工艺，本发明的一个有益方面就在于薄SOI层不再是一个问题。
对于PMOSFET，通常用硼来对SD区进行掺杂，而用砷来对沟道区进行掺杂。硼在SiGe中扩散得比在Si中慢。砷在Si中扩散得比在SiGe中慢。所得的结构有助于形成PMOSFET的浅SD和扩展p-n结以及陡峭的卤素分布。
在图4中，已经在层30的表面上生长了名义厚度0.5-2nm的栅氧化物层103。也可以使用其它栅绝缘层，例如氮化物，氧氮化物或高k材料。
在氧化物层30上沉积了多晶硅(poly)栅层110，其上是氮化物硬掩模层107。
图5示出沉积、曝光以及固化光刻胶层108，然后刻蚀要用于要形成的FET中的栅堆叠之后的结果。作为示例，使用了反应离子刻蚀(RIE)，因为其方向性。传统的刻蚀材料在需要将各种材料完全刻蚀，停在SOI层30顶表面上时才使用。
图6示出形成例如大约10nm厚的氮化物薄等角层，然后刻蚀氮化物水平部分之后的结果。刻蚀氧化物水平部分后剩下在随后的工艺过程中保护栅堆叠侧面并限定栅氧化物103之下的晶体管主体和要遵循的锗扩散之间的位移距离。层117在栅110顶部的部分是层107在腐蚀水平氮化物表面步骤之后剩余的部分。
还进行了选择外延生长工艺，在裸露的硅表面上生长外延材料130。
外延层130的锗浓度优选地大于大约30％，其厚度正好使足够多的锗可以扩散进SOI层30。例如，外延层130的厚度为大约15-30nm。
图7示出在1000C进行退火10分钟的结果，退火形成所需的锗从掺杂层130到SOI层30的扩散，在层30顶部具有最大锗浓度值，在底部下降到一个较低值。将会选择退火的温度和时间以形成所需的锗梯度；在此情形中，一直到层30的底表面都具有显著的锗浓度，形成SD40’。
在硅SOI层的晶体结构中加入锗将在图1的源和漏40的材料中引入压应变。压应变反过来会在SOI中水平方向上施加压应力并在器件100的沟道中垂直方向上施加张应力。
在技术中众所周知的，工艺中传统上随后的步骤——例如进行卤素注入，扩展注入，隔离形成，S/D注入以及金属化——都涉及号称“完成晶体管”的目的。这一方法可以与一次性隔离方法结合来制作高性能MOSFET。也就是，去除氮化物隔离，如果需要再进行多晶栅的重新氧化，卤素和扩展离子注入，隔离形成，然后是SD离子注入和SD退火。
总起来说，该工艺就是：
开始于硅SOI晶片；
生长栅氧化物(或等效物)；
沉积多晶栅层(或对于金属栅器件来说沉积金属)；
沉积氮化物掩模层；
沉积并构图光刻胶，RIE氮化物，多晶硅(对于金属栅来说为RIE金属)和氧化物；
形成薄的氮化物隔离(～10-30nm)；
在裸露的硅上选择外延SiGe(或锗)；
高温退火，使锗扩散到Si器件层中，使锗浓度沿垂直和水平方向渐变，但是优选地锗分布不进入到沟道区中；
完成晶体管，包括
卤素注入，扩展注入，隔离形成，S/D注入，RTA，金属化。
图8示出本发明第二方案中的一个步骤，在该方案中，直到图6且包括图6的步骤都一样。由这一替代方法做出的结构与图1相同。图8示出在SiGe层130顶表面上生长氧化物层135。在这一实施例中，氧化物耗尽了整个SiGe层，将其变成氧化物135。由于SiGe中氧化作用的雪犁效应，SiGe中的Ge原子被驱赶到SOI层中。氧化方法比单独的退火更能有效地将Ge驱赶到Si中。然而，氧化方法会产生缺陷，导致器件的漏电。而且在SiGe的拐角处也不容易控制氧化过程。
在热氧化过程中，所需的热驱赶锗进入SOI层30，在此情形中，从各个路径向下到BOX层20并形成渐变SiGe SD 40’。
图9示出通过湿法刻蚀剥离氧化物135的结果，留下用于后续工艺的清洁表面。
图9的结构也可用上面结合图7所讨论的相同传统完成步骤来完成。
图2示出本发明的一个替代方案，其中源和漏40仅部分扩展到SOI层，留下SOI层30的一部分作为下层硅35。栅的结构与图1和2中相同。
图2的结构具有这样的优点：锗集中在SOI层30的顶部，从而应力也集中在该处。对于表面沟道晶体管来说，应力向下出现在SOI层中没有任何实质好处，而扩散到较浅的深度所需的时间更短。
图1所示的结构对于超薄SOI器件来说尤其重要，因为极难控制SD区的向下腐蚀不会达到BOX。然而，(传统的掩埋SiGe SD方法)要求在SD区中剩下Si以便在SD区中外延生长SiGe。当应变SiGe的厚度超过给定Ge组分的临界厚度时会产生不受欢迎的失配位错。这限制了在具有大厚度的应变SiGe中高Ge组分的使用。可以在图1和图2之间改变结构以优化沟道中的应力。例如，高Ge组分加薄的渐变SiGe SD，或低Ge组分加厚的渐变SiGe SD。
上面所讨论的两种方法都可以用来形成这一结构，其中控制锗向SOI层中的扩散使其在整个层被锗填满之前就停止。
在形成图2所示结构时，必须限制接受到的热量，以便限制锗扩散的垂直扩展。
图3示出本发明的另一替代方案，其中晶片为体硅晶片，从而源和漏40只是部分扩展到体硅中，留下一部分下层硅10。形成图3的结构的另一方法是腐蚀SD区中的Si，然后选择外延SiGe(如先有技术所提出的)。然后退火在SD区中形成渐变SiGe。这一方法的优点在于外延界面远离沟道，在沟道中产生更强的应力。因此，这可以减小外延界面处的缺陷导致的漏电。
体和SOI晶片相比的优点和缺点在技术领域中已是众所周知的，无需在此重复。要选择体或SOI晶片，集成电路设计者必须进行折衷。
本发明的这一方案还使用了扩散的退火或氧化方法。
虽然就单个优选实施方案描述了本发明，但是熟练的技术人员将会认可本发明能够在下述权利要求的精神和领域内以各种方案来实施。

Claims (25)

1.形成PMOSFET的方法，包含下列步骤：
提供SOI晶片，它具有掩埋绝缘层和在所述掩埋绝缘层之上的SOI层；
在所述SOI层之上形成一层栅绝缘体；
在所述SOI层之上形成晶体管栅，所述栅之下有沟道；
在所述栅的第一和第二侧面形成绝缘体侧壁；
在所述SOI层上邻近所述绝缘体侧壁处外延形成含有掺杂剂的掺杂层；
使所述掺杂剂从所述掺杂层扩散到所述SOI层中，从而在所述沟道平行于SOI表面的水平方向上产生压应力并在垂直于所述SOI表面的垂直方向上产生张应力；以及
完成所述PMOSFET。
2.根据权利要求1的方法，其中所述扩散步骤通过高温退火来实现。
3.根据权利要求1的方法，其中所述扩散步骤持续进行直到所述锗到达所述SOI层的底表面。
4.根据权利要求1的方法，其中所述扩散步骤在所述锗到达所述SOI层底表面之前停止。
5.根据权利要求1的方法，其中所述掺杂层为SiGe。
6.根据权利要求3的方法，其中所述掺杂剂层为具有大于原子数20％的锗浓度的SiGe。
7.根据权利要求1的方法，进一步包含在所述掺杂层上生长一层热氧化物，从而使所述掺杂层中的所述掺杂剂扩散到所述SOI层中。
8.根据权利要求7的方法，进一步包含在所述扩散所述掺杂剂的步骤之后去除所述热氧化物的步骤。
9.根据权利要求7的方法，所述扩散步骤持续进行直到所述锗到达所述SOI层的底表面。
10.根据权利要求7的方法，其中所述扩散步骤在所述锗到达所述SOI层底表面之前停止。
11.根据权利要求7的方法，其中所述掺杂层为SiGe。
12.根据权利要求11的方法，其中所述掺杂层为具有大于原子数20％的锗浓度的SiGe。
13.形成PMOSFET的方法，包含下列步骤：
提供体硅晶片；
在所述体硅之上形成一层栅绝缘体；
在所述体硅之上形成晶体管栅，所述栅之下有沟道；
在所述栅的第一和第二侧面形成绝缘体侧壁；
在所述体硅上邻近所述绝缘体侧壁处外延形成含有锗或杂质的掺杂层；
使所述锗从所述掺杂层扩散到所述体硅中，从而在所述沟道中的水平方向(平行于SOI表面)上产生压应力并在垂直方向(垂直于SOI表面)上产生张应力；以及
完成所述PMOSFET。
14.根据权利要求13的方法，其中所述扩散步骤通过高温退火来实现。
15.根据权利要求13的方法，其中所述掺杂层为SiGe。
16.根据权利要求13的方法，其中所述掺杂剂层为具有大于原子数20％的锗浓度的SiGe。
17.根据权利要求13的方法，进一步包含在所述掺杂剂层上生长一层热氧化物，从而使所述掺杂剂扩散到所述体硅中。
18.根据权利要求17的方法，进一步包含在所述扩散所述掺杂剂的步骤之后去除所述热氧化物的步骤。
19.根据权利要求17的方法，其中所述掺杂剂层为SiGe。
20.根据权利要求19的方法，其中所述掺杂剂层为具有大于原子数20％的锗浓度的SiGe。
21.集成电路，含有至少一个PMOSFET，该PMOSFET形成在具有掩埋绝缘体层和所述掩埋绝缘体层之上的SOI层的SOI晶片中，所述至少一个PMOSFET在所述SOI层之上具有栅绝缘体；在所述SOI层之上的晶体管栅在所述栅之下具有沟道，在所述沟道中，所述沟道在平行于SOI表面的水平方向上具有压应力，在垂直于SOI表面的垂直方向上具有张应力；其中所述SOI层具有在所述水平方向上产生所述压应力的掺杂剂的渐变浓度，所述掺杂剂的所述浓度在所述SOI层的上表面处具有最大值。
22.根据权利要求21的集成电路，其中掺杂剂的所述渐变浓度扩展到一个小于所述SOI层厚度的掺杂剂深度。
23.根据权利要求22的集成电路，其中所述SOI层为硅，所述掺杂剂为锗。
24.根据权利要求22的集成电路，其中所述渐变浓度通过高温退火来形成。
25.根据权利要求22的集成电路，其中所述渐变浓度通过热氧化沉积在所述SOI层之上的沉积的掺杂剂层来形成。
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