CN1763970A - 薄型绝缘半导体之绝缘间隙壁 - Google Patents
薄型绝缘半导体之绝缘间隙壁 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
一种半导体元件,包括半导体平台,位于介电层之上;栅极堆栈,形成于半导体平台之上;以及绝缘间隙壁,环绕半导体平台而形成以及填满位于半导体平台边缘之底切区域。
Description
技术领域
本发明涉及一种微电子元件,且特别涉及一种具有薄型绝缘半导体结构的微电子元件。
背景技术
当用薄型绝缘半导体(Semiconductor On Insulator,SOI)制造半导体微电子元件时,在图案化栅极堆栈时的蚀刻和清洗工艺会在埋入式绝缘层形成底切。在后续的硅化金属工艺中,硅化金属残留会形成在底切区域而造成和相邻通道区的漏电。
发明内容
为解决公知的薄型绝缘半导体技术产生的漏电的问题,本发明公开一种半导体元件,包含半导体平台,位于介电层之上;栅极堆栈,位于半导体平台之上;绝缘间隙壁,围绕半导体平台和填满位于该半导体平台边缘的底切区域。
本发明还公开一种半导体元件,包含半导体平台,位于介电层之上;栅介电层,形成于半导体平台之上;栅电极,形成于栅介电层之上;源极和漏极,围绕半导体平台和填满位于半导体平台边缘的底切区域。
本发明公开一种半导体元件的制造方法,包含形成半导体平台于介电层之上;形成绝缘间隙壁,围绕半导体平台和填满位于半导体平台边缘的底切区域;形成栅极堆栈于该半导体平台之上。
本发明还公开一种半导体元件的制造方法,包含形成半导体平台于介电层之上;形成栅极堆栈于半导体平台之上;形成源极和漏极,围绕半导体平台和填满位于半导体平台边缘的底切区域。
根据本发明所公开的半导体元件及其制造方法,绝缘间隙壁可保护绝缘层以避免在图案化栅极堆栈时的蚀刻和清洗工艺在埋入式绝缘层形成底切,在后续的硅化金属工艺中也不会造成和相邻通道区的漏电。
附图说明
本发明上述及其它特征可通过以下的实施例及相关的附图来做进一步的了解。必须强调的是,根据业界标准实务,各种结构并非依尺寸绘示。事实上,为了讨论上的清楚,各种结构的尺寸大小可任意增减。
图1是一实施例形成薄型绝缘半导体之方法之简化流程图;
图2至图7a和7b是一例示实施例形成薄型绝缘半导体的剖面示意图;
图8是另一实施例形成薄型绝缘半导体之方法之简化流程图;
图9至图11a和11b是一例示实施例形成薄型绝缘半导体的剖面示意图;
图12a和12b是一薄型绝缘半导体元件例示实施例的剖面示意图;以及
图13是另一实施例形成薄型绝缘半导体之方法之简化流程图。元件标记简单说明
100、100a、100b、100c、100d、400a、400b:半导体元件
110、410:基底
120、420:介电层
125:底切
135:半导体层
140:氧化硅层
150:氮化硅层
130、430:半导体平台
160、165:绝缘间隙壁
170、470:栅极堆栈
172、472:栅介电层
174、474:栅电极
176、476:栅间隙壁
200、300、500:方法
210、212、214、216、218、310、312、314、316、510、512、514、
516、518:步骤
460、464:源极
462、466:漏极
具体实施方式
下述的讨论提供相当多的实施例或例子,以在不同实施例中置入不同特征。下述元件及安排之特别例子可用来简化公开。因此,仅数个例子当不应被视为限制。另外,在公开中不同的例子会使用相同的标记和文字。重复使用标记和文字仅为了简化和清晰的目的,而非规定了在不同实施例与/或讨论轮廓间的关系。
图1是方法200形成薄型绝缘半导体元件之简化流程图。而图2至图7a和7b是形成半导体元件100流程之剖面示意图。
方法200由步骤210开始,先提供如图2所示之半导体基底110、介电层120形成于基底110之上,以及半导体层135形成于介电层120之上。
半导体元件100具有SOI结构,SOI结构具有介电层120介于半导体基底110及半导体层135之间。基底110和半导体层135分别可以为硅、砷化镓、氮化镓、应变硅、硅化锗、碳化硅、碳化物、钻石与/或其它物质。半导体基底110可以包括磊晶层。在本实施例中半导体层135的厚度自约5纳米至约200纳米。半导体层135较佳的厚度范围为介于约5纳米至约30纳米之间。介电层120可以包括氧化硅、氮化硅、氮氧化硅与/或其它材质。介电层120的厚度自约10纳米至约100纳米,较佳的厚度范围为介于约10纳米至约30纳米之间。
介电层120和半导体层135可通过各种SOI技术来形成。例如,介电层120可通过注氧分隔(SIMOX)工艺形成于半导体基底内。SIMOX技术是通过在硅基底植入高浓度的氧离子,以使氧离子的浓度高峰位于基底的硅表面之下。在离子植入之后,将晶片进行高温退火(约摄氏1150度至1400度)形成化学量上为二氧化硅的连续表面层。因此介电层120(又称埋入氧化物或BOX)电分隔半导体层135和半导体基底110。
方法200进行到步骤212,图案化半导体层135形成半导体平台(或岛)130。如图3所示,以例如化学气相沉积(CVD)、热氧化、原子沉积(ALD)、物理气相沉积(PVD)与/或其它工艺技术在半导体层135上形成氧化硅层140和氮化硅层150。以适当的工艺,例如光刻和蚀刻工艺图案化氧化硅层140和氮化硅层150。如图4a和图4b所示,实施蚀刻工艺将氧化硅层140和氮化硅层150的图案转移到半导体层135上而形成半导体平台130。接着以湿式或其它适当的技术移除氧化硅层140和氮化硅层150。在硅蚀刻与/或氧化硅层/氮化硅层移除之后后续清洁工艺。在图案化半导体层135的蚀刻工艺与/或清洁工艺中位于半导体层135下方之埋入式介电层120亦会被部分移除而在半导体平台130的边缘形成如图4b所示之底切或孔洞125。图4a图则表示其它实施例在相对位置无底切的情形。
方法200进行到步骤214,形成绝缘间隙壁如图5a和图5b所示,绝缘间隙壁160(图5a)或165(图5b)形成于半导体平台130的边缘。绝缘间隙壁165填满平台130边缘的底切区域。绝缘间隙壁160或165的材质可以包括氧化硅、氮化硅、氮氧化硅、其它材质或其任意组合所组成之族群。绝缘间隙壁160或165是用来保护半导体层130的边缘避免形成导体特征,例如在硅化金属工艺时硅化金属残留在底切区域。如这样非预期的导体特征会造成和相邻通道区的漏电或短路。
在一实施例中,以CVD、热氧化、ALD、PVD或其它适当的工艺来形成氧化硅层。接着以CVD、热氧化、ALD、PVD或其它适当的工艺来形成氮化硅层。形成复层介电材质层后再蚀刻移除部分以形成绝缘间隙壁,使用的工艺包括干式蚀刻。
方法200进行到步骤216,栅极堆栈170形成于基底110上。栅极堆栈170包括栅介电层172和栅电极174。如图6a和图6b所示,栅介电层172可以包括氧化硅、氮氧化硅、高介电材质、其它材质或其任意组合所组成之族群。高介电材质包括氮化钽、氮化钛、五氧化二钽、氧化铪、氧化锆、氮氧化硅铪、硅化铪、氮化硅铪、氧化铝铪、硅化镍与/或其它合适的材质。栅介电层172的厚度介于约5埃至约20埃之间。栅介电层具有复层结构例如一层氧化硅层和一层高介电材质层。栅电极174可包括多晶硅、金属、金属硅化物或其它导体材质。栅电极174可具有复层结构例如一层多晶硅层和一层金属硅化物。金属硅化物可包括一种或多种金属,例如钛、钽、钨、钴、镍、铝、铜与/或其它金属。
栅极堆栈170的形成是先形成介电层和导体层,再图案化两者以形成栅介电层172和栅电极174。介电层以CVD、ALD、PVD或其它适当的工艺来形成。导体层以CVD、ALD、PVD、电镀或其它适当的工艺来形成。
方法200进行到步骤218,如图7a和图7b所示形成栅间隙壁176于栅极堆栈170的两侧边。栅间隙壁176包括介电材质,例如氮化硅、氮氧化硅、与/或氧化硅,例如栅间隙壁176可使用CVD、ALD、PVD或其它适当的工艺来沉积介电材质,然后接着用各向异性回蚀来形成。
图8是表示另一实施例形成绝缘半导体元件之简化流程图。方法300由步骤310开始,先提供基底110,具有介电层,形成于基底与半导体层之间。在下一步骤312,形成半导体平台特征。步骤310和312均和图2、3、4所示之方法200的步骤210和212实质上相似。同样地,图4b中在介电层120形成底切125也相似。在另一实施例中,如同图4a一般,未形成底切。
如图9a和图9b所示,方法300进行步骤314来形成栅极堆栈170于基底110之上。步骤314和方法200之步骤216在材质、工艺和结构上均实质上相似。例如栅极堆栈170的形成是先形成介电层和导体层,以光刻和蚀刻工艺移除部分介电层和导体层以图案化两者以形成栅介电层172和栅电极174。
如图10a和图10b所示,方法300进行步骤316形成栅间隙壁176于栅极堆栈170的两侧边。步骤316和方法200之步骤218在材质、工艺和结构上均实质上相似。例如形成氮化硅与/或氧化硅,然后接着用各向异性回蚀来形成间隙壁176。
如图11a和图11b所示,绝缘间隙壁160(165)可在形成栅间隙壁176的步骤316同时形成,也可以在下一步骤形成,当然也可以部分在步骤316形成,部分在下一步骤形成。例如,先形成氧化硅层和氮化硅层以及各向异性回蚀以形成栅间隙壁176。这个工艺也可以用来在半导体平台130的边缘形成绝缘间隙壁160(165)并填满位于平台130边缘的底切区域125。接着在下一步骤,另一介电层,包括氧化硅与/或氮化硅可被形成且被回蚀以在绝缘间隙壁160(165)上增加一介电层。
综上观之,半导体元件100还可包括硅化金属层,形成于栅电极及源/漏极之上,硅化金属层是通过沉积金属、退火及移除未反应之金属所制成。半导体元件100还包括通过各种掺杂工艺,例如离子植入所形成的掺杂通道区、源极和漏极于半导体平台130之上。例如,在形成栅极堆栈后的和形成栅间隙壁后的具有不同掺杂剂量和离子能量的离子植入用来形成源/漏极。半导体平台130可以是P型掺杂区域或N型掺杂区域或者是两者的混合。N型掺杂区域用来形成P型金属氧化物半导体场效晶体管(PMOSFET或PMOS)的通道区或是N型金属氧化物半导体场效晶体管(NMOSFET或NMOS)的源/漏极区以及可以包括磷、砷与/或其它材质。P型掺杂区域用来形成N型金属氧化物半导体场效晶体管(NMOSFET或NMOS)的通道区或是P型金属氧化物半导体场效晶体管(PMOSFET或PMOS)的源/漏极区以及可以包括硼、氟化硼、铟与/或其它材质。在杂质植入之后,可接续进行扩散、退火与/或电性活化工艺。
半导体薄型绝缘半导体元件,例如具有绝缘间隙壁之半导体元件100可以延伸和配合其它使用半导体平台的集成电路上。半导体元件100可配合其它集成电路,包括电可编程只读存贮器(EPROM)阵列、电可擦除可编程只读存贮器(EEPROM)阵列、静态随机存取存贮器(SRAM)阵列、动态随机存取存贮器(DRAM)阵列、单电子晶体管(SET)、高压晶体管,例如横向扩散金属氧化物半导体(LDMOS)和垂直扩散金属氧化物半导体(VDMOS),与/或其它微电子元件(在此之后均简称为微电子元件)。
图12a和图12b是表示另一实施例之绝缘半导体元件的剖面示意图。如下所述之绝缘半导体元件及一例示的制造方法如图13所示之简化流程图500所示。半导体元件400a(400b)包括基底410、介电层420,形成于基底410之上;和半导体平台(或岛)430位于介电层420之上;如同图7a的半导体元件100a(或图7b之100b)的基底110、介电层120和半导体平台130,其材质、结构和制造方法均相似。在具有适当的掺杂轮廓和浓度后,半导体平台430可做为通道区之用,但不包括源/漏极,这和半导体平台130不同,因为后者包括源/漏极。如图12b所示,介电层420还包括了底切,底切形成于在半导体平台430的边缘处。
半导体基底410、介电层420和半导体层在方法500的步骤510形成。在步骤520时半导体层被图案化形成半导体平台430。步骤510和512和方法200之步骤210和212及方法300的步骤310和312实质上相似。在一实施例中,如图12b所示,会在介电层420形成底切。在另一实施例中,如图12a所示,不会在介电层420形成底切。
半导体元件400a(或400b)可包括栅极堆栈470,栅极堆栈470包括栅介电层472和栅电极474,实质上与栅极堆栈170相似。在步骤514,栅极堆栈470形成于半导体平台430之上,这实质上和方法300的步骤314在材质、结构和制造方法均相似。例如栅极堆栈470的形成是先形成介电层和导体层,以光刻和蚀刻工艺移除部分介电层和导体层。
元件400还包括栅间隙壁476,实质上和半导体元件100a(100b)的栅间隙壁176相似。在步骤516,栅间隙壁476形成于栅极堆栈470的两侧,实质上和方法300的步骤316有相似的材质和工艺。例如形成氮化硅与/或氧化硅然后接着用各向异性回蚀来形成间隙壁476。
更进一步,半导体元件400可包括如图12a所示之源极460和漏极462(在图12b中则为源极464和漏极466)。源极和漏极围绕半导体平台430,以及可延伸于半导体平台430之上以部分或实质上覆盖半导体平台430的表面,因此,每一源/漏极靠近栅间隙壁或与之接触。源极和漏极保护半导体平台430的边缘。在半导体元件400b中,源极和漏极延伸并实质上填满位于半导体平台430边缘的底切区域。源极和漏极可以包括硅、锗化硅、碳化硅或其它半导体材质。形成源/漏极的半导体材质可以和形成半导体平台的半导体材质不同。例如,半导体平台430可以包括硅而源/漏极可以包括锗化硅。相对地,半导体平台430可以包括锗化硅而源/漏极可以包括硅。在另一实施例中,当半导体平台为硅材质时,NMOS和PMOS中之一种可以具有锗化硅的源/漏极而另一种可以具有碳化硅的源/漏极。相对地,当NMOS和PMOS源/漏极的材质为硅时,半导体平台相对NMOS和PMOS中之一种可以为锗化硅而相对另一种可以为碳化硅。在另一实施例中,半导体平台和源/漏极区域的半导体材质异于半导体基底410或其底部具有应变结构以增进元件的效能。源极和漏极亦可以是以制造工艺,例如磊晶成长(SEG)或其它适当工艺所形成之单晶结构。半导体薄型绝缘半导体元件400可以延伸和配合其它使用半导体平台的集成电路上。
虽然本发明已以数个较佳实施例公开如上,然其并非用以限定本发明,任何所属技术领域的技术人员,在不脱离本发明之精神和范围内,当可作各种之更动与改进,因此本发明之保护范围当视权利要求所界定者为准。据此,所有的变化、取代与改变均为权利要求所定义之本发明公开之范围所涵盖。
Claims (15)
1.一种半导体元件,其特征是包含:
半导体平台,位于一介电层之上;
栅极堆栈,位于该半导体平台之上;以及
绝缘间隙壁,围绕该半导体平台和填满位于该半导体平台边缘的底切区域。
2.根据权利要求1所述之半导体元件,其特征是该半导体平台还包括源极、漏极和通道区。
3.根据权利要求1所述之半导体元件,其特征是还包括栅间隙壁,位于该栅极堆栈的两侧。
4.根据权利要求1所述之半导体元件,其特征是该栅极堆栈包括栅介电层与栅电极,位于该栅介电层之上。
5.根据权利要求4所述之半导体元件,其特征是该栅介电的材质选自于氧化硅和高介电材质所组成之族群。
6.根据权利要求4所述之半导体元件,其特征是该栅电极的材质选自于多晶硅、多晶锗、金属和金属硅化物所组成之族群。
7.根据权利要求2所述之半导体元件,其特征是该半导体平台的材质选自于硅、锗和碳所组成之族群。
8.一种半导体元件,其特征是包含:
半导体平台,位于一介电层之上;
栅介电层,形成于该半导体平台之上;
栅电极,形成于该栅介电层之上;以及
源极和漏极,围绕该半导体平台和填满位于该半导体平台边缘的底切区域。
9.根据权利要求8所述之半导体元件,其特征是该源极和该漏极延伸覆盖该半导体平台。
10.根据权利要求8所述之半导体元件,其特征是该源极和该漏极的材质选自于由硅、锗和碳所组成之族群。
11.根据权利要求8所述之半导体元件,其特征是半导体平台的材质选自于由硅、锗和碳所组成之族群。
12.根据权利要求8所述之半导体元件,其特征是该半导体平台的厚度自5纳米至200纳米。
13.根据权利要求8所述之半导体元件,其特征是该栅介电的材质选自于氧化硅和高介电材质所组成之族群。
14.根据权利要求8所述之半导体元件,其特征是该栅电极的材质选自于多晶硅、多晶锗、金属和金属硅化物所组成之族群。
15.根据权利要求8所述之半导体元件,其特征是还包括栅间隙壁,形成于栅介电层和栅电极的侧壁。
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US7091071B2 (en) * | 2005-01-03 | 2006-08-15 | Freescale Semiconductor, Inc. | Semiconductor fabrication process including recessed source/drain regions in an SOI wafer |
-
2004
- 2004-10-20 US US10/969,374 patent/US7358571B2/en active Active
-
2005
- 2005-05-06 TW TW094114743A patent/TWI286344B/zh not_active IP Right Cessation
- 2005-05-18 CN CNA2005100707649A patent/CN1763970A/zh active Pending
-
2008
- 2008-02-25 US US12/036,616 patent/US8084305B2/en not_active Expired - Fee Related
- 2008-03-01 US US12/040,877 patent/US7582934B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103579348A (zh) * | 2012-08-10 | 2014-02-12 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
CN103579348B (zh) * | 2012-08-10 | 2018-02-09 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
TWI745335B (zh) * | 2016-01-22 | 2021-11-11 | 日商庄田德古透隆股份有限公司 | 端面塗佈裝置 |
Also Published As
Publication number | Publication date |
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US7582934B2 (en) | 2009-09-01 |
TWI286344B (en) | 2007-09-01 |
US20060081928A1 (en) | 2006-04-20 |
US20080142888A1 (en) | 2008-06-19 |
US8084305B2 (en) | 2011-12-27 |
US7358571B2 (en) | 2008-04-15 |
US20080145982A1 (en) | 2008-06-19 |
TW200614338A (en) | 2006-05-01 |
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