CN1770476A - 薄膜晶体管及其制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010409 thin film Substances 0.000 title claims abstract description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000010408 film Substances 0.000 claims abstract description 47
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 53
- 230000004888 barrier function Effects 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 46
- 229910052594 sapphire Inorganic materials 0.000 claims description 43
- 239000010980 sapphire Substances 0.000 claims description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 238000002425 crystallisation Methods 0.000 claims description 16
- 230000008025 crystallization Effects 0.000 claims description 16
- 239000002019 doping agent Substances 0.000 claims description 9
- 238000000348 solid-phase epitaxy Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 230000005855 radiation Effects 0.000 abstract 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- -1 silicon ion Chemical class 0.000 description 1
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
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Abstract
提供了一种薄膜晶体管(TFT)和一种制造所述薄膜晶体管的方法。所述TFT包括:透明衬底;覆盖所述透明衬底的预定区域的绝缘层;在所述绝缘层上形成的、包括源极区、漏极区和沟道区的单晶硅层;以及在所述单晶硅层的沟道区上依次形成的栅极绝缘膜和栅电极。所述TFT能够通过快速热辐射高速地稳定运行。并且能够使TFT的尺寸显著降低。
Description
技术领域
本发明涉及半导体器件及其制造方法,尤其涉及薄膜晶体管(TFT)及其制造方法。
背景技术
在LCD或OLED等平板显示器中用作开关器件的TFT的沟道是由非晶硅或多晶硅形成的。
在由非晶硅形成TFT的沟道区时,能够提高均匀性,但是由于载流子迁移率低,难以实现高速工作。在由多晶硅形成TFT的沟道区时,与通过非晶硅形成沟道区的情况相比,可能增大载流子迁移率,但是,由于晶粒尺寸的限制难以降低总尺寸。
可以在玻璃衬底或蓝宝石衬底上形成TFT。在前一种情况中,难以像在硅LSI中一样实现特性均匀性。在后一种情况下,由于在TFT的沟道区上施加了压应力,因此,难以获得与在未施加压应力或张应力的系统当中相同的载流子迁移率。
发明内容
本发明提供了一种能够高速运行,并显著按比例缩小的TFT。
本发明还提供了一种制造TFT的方法。
根据本发明的一方面,提供了一种薄膜晶体管,其包括:透明衬底;覆盖了所述透明衬底的预定区域的绝缘层;在所述绝缘层上形成的,包括源极区、漏极区和沟道区的单晶硅层;以及在单晶硅层的沟道区上依次形成的栅极绝缘膜和栅电极。
可以去除透明衬底的预定区域的预定厚度,并且,可以采用绝缘层填充去除的部分。
可以在透明衬底的预定区域上形成所述绝缘层。
所述透明衬底可以是以(1102)面为上表面的蓝宝石衬底。
根据本发明的另一方面,提供了一种制造薄膜晶体管的方法,所述方法包括:在透明衬底上形成覆盖透明衬底的预定区域的绝缘层;在所述绝缘层上形成单晶硅层;在单晶硅层的预定区域上依次形成栅极绝缘层和栅电极;以及,向围绕所述栅电极的单晶硅层中注入掺杂剂。
所述绝缘层的形成可以进一步包括:在透明衬底的预定区域上形成沟槽;以及采用绝缘层填充所述沟槽。
所述单晶硅层的形成可以进一步包括:在围绕所述绝缘层的蓝宝石衬底上形成单晶硅层,在所述绝缘层和单晶硅层上形成非晶硅层;使在绝缘层上形成的非晶硅层结晶成单晶硅层;以及,去除围绕绝缘层的单晶硅层。
使形成于绝缘层上的非晶硅层结晶为单晶硅层可以进一步包括下述步骤:(2a1)使在单晶硅层的形成过程中形成的单晶硅层上的非晶硅结晶为单晶硅层;和步骤(2a2)向在步骤2a1中形成的单晶硅层和在绝缘层上形成的非晶硅层上照射激光。
可以通过垂直固相外延工艺,使在步骤2a1中形成于单晶硅层上的非晶硅层结晶为单晶硅层。
在绝缘层上形成单晶硅层可以进一步包括:在围绕绝缘层的蓝宝石衬底上形成与所述绝缘层具有相同高度的单晶硅层;在所述绝缘层和单晶硅层上形成非晶硅层;使在绝缘层上形成的非晶硅层结晶成单晶硅层;以及,去除围绕绝缘层的单晶硅层。
使形成于绝缘层上的非晶硅层结晶为单晶硅层可以进一步包括下述步骤:(2a1)使在单晶硅层的形成过程中形成的单晶硅层上的非晶硅层结晶为单晶硅层;以及(2a2)向在步骤2a1中形成的单晶硅层和在绝缘层上形成的非晶硅层上照射激光。
可以通过垂直固相外延工艺,使在步骤2a1中形成于单晶硅层上的非晶硅层结晶为单晶硅层。可以将温度维持在600-900℃的范围内。
所述绝缘层可以由氧化硅膜和氮化物膜之一构成。
可以使所形成的非晶硅层具有这样的厚度,即所形成的单晶硅层的厚度为100nm或更小。
透明衬底可以是以(1102)面为上表面的蓝宝石衬底,其适合生长单晶硅。
可以在500-750℃的范围内,优选在550℃的温度下形成非晶硅层。
附图说明
通过参照附图,对本发明的示范性实施例予以详细说明,本发明的上述特征和优势会变得更加明显,附图中:
图1和图2是说明根据本发明的第一和第二实施例的TFT的横截面图;
图3到图12是说明如图1所示的TFT的制造方法的横截面图;以及
图13到图20是说明如图2所示的TFT的制造方法的横截面图。
具体实施方式
现在,将参照说明本发明示范性实施例的附图,对本发明进行更加全面地说明。在附图中,为了清晰起见,夸大了层和区域的厚度。
现在,将对根据本发明实施例的TFT予以说明。图1是说明根据本发明的第一实施例的TFT的横截面图。
参照图1,在SOI衬底S1上形成根据本发明实施例的TFT,在所述的SOI衬底S1中包括蓝宝石衬底10和氧化硅膜12。可以采用其他能够实现相同功能的透明衬底替代蓝宝石衬底,也可以采用其他绝缘膜,例如氮化硅(SiN)膜替代氧化硅膜12。如图1所示,可以在去除了一部分蓝宝石衬底10的位置上提供所述氧化硅膜12,或者,如图2所示,在蓝宝石衬底10的预定区域提供所述氧化硅膜12。在SOI衬底S1上提供单晶硅层20a。单晶硅层20a包括第一至第三区域20a1、20a2和20a3。第一区域20a1可以是其中注入了n型或p型掺杂剂的源极区,第三区域20a3可以是其中注入了n型或p型掺杂剂的漏极区,插入到第一和第三区域20a1和20a3之间的第二区域20a2可以是沟道区。在第二区域20a2上依次形成栅极绝缘膜26和栅电极28。
图2是说明根据本发明第二实施例的TFT的横截面图,其中,在蓝宝石衬底10的预定区域上形成氧化硅膜12,但其他元件的配置与图1所示相同。
现在将参照图3至图12对图1所示的TFT的制造方法予以说明。
参照图3,通过在蓝宝石衬底10的预定区域上形成掩模M界定用于生长单晶硅层的区域。可以采用其他能够实现相同功能的透明衬底替代蓝宝石衬底10。掩模M可以是光敏膜图案。接下来,对其上形成了掩模M的蓝宝石衬底10的上表面进行蚀刻。通过蚀刻去除蓝宝石衬底10的预定部分,但是覆盖了掩模M的蓝宝石衬底10的预定部分不受蚀刻影响。因此,在经过蚀刻之后,在覆盖了掩模M的部分和未覆盖掩模M的部分之间形成了对应于蓝宝石衬底10的去除厚度的台阶差异。
接下来,在从蓝宝石衬底10上去除了掩模M之后,如图4所示,在蓝宝石衬底10的整个表面上形成氧化硅(SiO2)膜12。之后,对氧化硅(SiO2)膜12的整个表面抛光。可以采用化学机械抛光设备进行抛光。抛光处理优选持续到暴露蓝宝石衬底10为止。可以采用其他能够实现相同功能的绝缘膜,例如氮化硅(SiN)膜,替代氧化硅(SiO2)膜12。如图5所示,抛光的结果是,通过以氧化硅(SiO2)膜12填充蓝宝石衬底10的较低部分使所得到的产品的表面平面化。
在所得到的如图5所示的产品上实施选择外延工艺。可以采用超高真空CVD设备实施选择外延工艺。由于在氧化硅(SiO2)中不存在与氧发生反应的多余的硅,因此,通过选择外延工艺在氧化硅(SiO2)膜12上不会形成单晶硅层。因此,如图6所示,通过选择外延工艺仅在形成了掩模M的蓝宝石衬底10的预定区域上有选择地形成了单晶硅层14。
接下来,参照图7,在所得到的图6所示的产品上,通过选择外延工艺生长覆盖由选择外延工艺生长的单晶硅层14和氧化硅(SiO2)膜12的非晶硅层15。可以形成具有预定厚度的非晶硅层15,例如大于50nm。为了说明方便,将非晶硅层15划分为覆盖单晶硅层14的第一部分15a和覆盖氧化硅(SiO2)膜12的第二部分15b。在第一和第二部分15a和15b之间形成由单晶硅层14的厚度引起的台阶差异。在500-750℃的温度范围内,优选在550℃的温度下,采用低压CVD方法形成非晶硅层15。但是,可以采用其他CVD方法或除了CVD方法以外的其他淀积方法形成非晶硅层15。
另一方面,按照上述方法形成的非晶硅层15中可能局部出现多晶硅。存在于非晶硅层15中的多晶硅可能阻断非晶硅层15的结晶过程。因此,优选去除存在于非晶硅层15中的多晶硅。为了去除所述多晶硅,在非晶硅层15的整个表面上进行硅掺杂I2。通过离子掺杂I2去除局部存在于非晶硅层15中的多晶硅,这样,就可以保持整个非晶硅层15的均匀的非晶态了。
接下来,在所得到的图7所示的产品上实施垂直固相外延工艺。可以在600-900℃的温度范围内实施垂直固相外延工艺。通过垂直固相外延工艺使在单晶硅层14上形成的非晶硅层15的第一部分15a结晶。结果,如图8所示,在蓝宝石衬底10未形成氧化硅(SiO2)膜12的区域上形成了厚度大于图7所示的单晶硅层14的单晶硅层18。
接下来,参照图8,采用XeCl或KrF源发出的准分子激光EL照射单晶硅层18的整个表面和非晶硅层15的第二部分15b。
在准分子激光EL的照射过程中,在非晶硅层15的第二部分15b上实施横向结晶。第二部分15b的单晶化结晶由单晶硅层18的边界向右侧推进。结果,如图9所示,在氧化硅(SiO2)膜12的整个表面上覆盖了单晶硅层20。在形成于蓝宝石衬底10上的一部分单晶硅层20和覆盖氧化硅(SiO2)层膜12的整个表面的一部分单晶硅层20之间出现了台阶差异22。台阶差异22是由图6所示的单晶硅层14的厚度引起的。由于形成TFT的后续处理过程中将除去形成于蓝宝石衬底10上的单晶硅层20,因此可以不考虑台阶差异22的存在。
更具体地说,通过光刻工艺去除单晶硅层20,在氧化硅(SiO2)膜12的预定区域上形成的那部分单晶硅层20除外。结果,如图10所示,在氧化硅(SiO2)膜12的预定部分上形成单晶硅岛20a。
接下来,参照图11,将单晶硅岛20a划分为第一至第三区域20a1、20a2和20a3。此时,优选在第一和第三区域20a1和20a3之间布置第二区域20a2。第一和第三区域20a1和20a3之一为源极区,另一个区域为漏极区。为了便于说明,第一区域20a1为源极区,第三区域20a3为漏极区。第二区域20a2为沟道区。如果所要形成的TFT为p型TFT,那么向第一和第三区域20a1和20a3中注入p型掺杂剂,如果所要形成的TFT为n型TFT,那么向第一和第三区域20a1和20a3中注入n型掺杂剂。
在将单晶硅岛20a划分为第一至第三区域20a1、20a2和20a3之后,如图12所示,在第二区域20a2上依次形成栅极绝缘膜26和栅电极28。之后,向第一和第三区域20a1和20a3中注入如上所述的掺杂剂。采取这种方式,在由氧化硅(SiO2)膜12和蓝宝石衬底10构成的SOI衬底S1上形成了采用单晶硅作为沟道的TFT T1。由于TFT T1采用了单晶硅作为沟道,因此,在TFT T1上施加了张应力,这与传统技术不同。因此,就TFT T1而言,由于和传统SOS器件相比,载流子迁移率显著增大,例如,当TFT T1为n型TFT T1时,电子迁移率显著增大,因此可能实现器件的高速运行。
现在,将对根据第二实施例的TFT的制造方法予以说明。
参照图13,在蓝宝石衬底10的上表面上形成氧化硅(SiO2)膜12。在氧化硅(SiO2)膜12的预定区域上形成掩模M1。掩模M1界定了用于在蓝宝石衬底10的上表面上形成单晶硅层的区域。掩模M1可以是光敏图案。在形成掩模M1之后,对氧化硅(SiO2)膜12的整个表面进行蚀刻。一直进行蚀刻直到露出蓝宝石衬底10的上表面为止。通过蚀刻去除在蓝宝石衬底10上形成的氧化硅(SiO2)膜12,由掩模M1覆盖的部分除外。因此,通过蚀刻暴露了除掩模M1覆盖的部分以外的蓝宝石衬底10的上表面。参照图14,通过蚀刻去除掩模M1,由氧化硅(SiO2)膜12覆盖一部分蓝宝石衬底10,露出蓝宝石衬底10的其余部分。
在所得到的、如图14所示的产品上进行选择性外延工艺。所实施的外延工艺可以和获得图12所示的TFT所采用的选择性外延工艺相同。优选持续实施所述选择外延工艺,直到所生长的单晶硅层30的厚度等于在蓝宝石衬底10的上表面暴露的氧化硅(SiO2)膜12的厚度。
接下来,如图16所示,在单晶硅层30和氧化硅(SiO2)膜12上形成非晶硅层32。可以在与如图1所示的条件相同的条件下形成非晶硅层32。出于与图1所示的相同的原因,在非晶硅层32上进行硅离子掺杂I2。之后,针对离子掺杂I2后的产品实施固相外延工艺。通过固相外延工艺垂直生长单晶硅层30。结果,在单晶硅层30上形成的非晶硅层32结晶,并且,如图17所示,单晶硅层30变成了高度与氧化硅(SiO2)膜12上形成的非晶硅层32相同的单晶硅层34。
参照图17,采用准分子激光EL照射单晶硅层34和非晶硅层32的整个表面。采用准分子激光EL照射的目的与图1所示的目的相同。通过准分子激光EL的照射实现单晶硅层34的横向生长。所述的单晶硅层34的生长优选持续到在氧化硅(SiO2)膜12上形成的所有非晶硅层均实现单晶化为止。在完成所述的横向生长之后,如图18所示,在蓝宝石衬底10上形成了覆盖氧化硅(SiO2)膜12的整个上表面的单晶硅层36。
接下来,参照图19,通过对单晶硅层36构图形成单晶硅图案36a(下文简称单晶硅岛36a)。可以采用传统的光刻工艺形成单晶硅岛36a。
参照图20,将单晶硅岛36a划分为第一至第三区域36a1、36a2和36a3。第一至第三区域36a1、36a2和36a3分别相应于图1所示的第一至第三区域20a1、20a2和20a3。因此,将省略与第一至第三区域36a1、36a2和36a3相关的描述。
接下来,在第二区域36a2上依次形成栅极绝缘膜38和栅电极40。将导电掺杂剂,例如n型或p型掺杂剂注入到第一和第三区域36a1和36a3中。采取这种方式,在蓝宝石衬底10的预定区域上形成了具有源极区、漏极区和由氧化硅(SiO2)膜12上的单晶硅层构成的沟道区的TFT。
尽管已经参照实施例对本发明进行了详细展示和说明,但是应当理解,本发明不只限于上述实施例。例如,本领域技术人员可以形成与图1和图2中所示的TFT具有不同结构的TFT,其中,沟道区由位于蓝宝石衬底10的氧化硅(SiO2)膜12上的单晶硅层构成。因此,应当由权利要求的技术精神界定本发明的范围。
如上所述,在透明SOI衬底上,即,在透明蓝宝石衬底的预定区域上形成的氧化硅(SiO2)膜上,形成根据本发明的TFT。因此,可以在同一衬底上形成根据本发明的TFT、逻辑器件、存储器件和需要透明衬底的平板显示器。这表示可以在包括蓝宝石衬底的SOI衬底上构建包括FPD的系统,所述的SOI衬底相当于玻璃上系统(SOG)。而且,在本发明中,由于TFT沟道是由单晶硅层构成的,因此在TFT的沟道上施加的是张应力。因此,由于提高了载流子迁移率,使得高速运行成为了可能。此外,在其上形成了根据本发明的TFT的蓝宝石衬底10具有比硅体衬底更为优良的热导率。因此,根据本发明的TFT能够更为稳定地运行。而且,由于TFT形成于以均匀厚度生长的单晶硅层上,因此能够在衬底上均匀地形成根据本发明的TFT。因此,TFT的集成密度比传统TFT更高。
Claims (17)
1.一种薄膜晶体管,其包括:
透明衬底;
覆盖所述透明衬底的预定区域的绝缘层;
在所述绝缘层上形成的、包括源极区、漏极区和沟道区的单晶硅层;以及
在所述单晶硅层的沟道区上依次形成的栅极绝缘膜和栅电极。
2.如权利要求1所述的薄膜晶体管,其中,去除透明衬底的预定区域的预定厚度,并且,采用绝缘层填充去除的部分。
3.如权利要求1所述的薄膜晶体管,其中,所述绝缘层形成于所述透明衬底的预定区域上。
4.如权利要求1所述的薄膜晶体管,其中,所述绝缘层为氧化硅膜和氮化硅膜之一。
5.如权利要求1所述的薄膜晶体管,其中,所述透明衬底为以(1102)面为上表面的蓝宝石衬底。
6.一种制造薄膜晶体管的方法,所述方法包括:
在透明衬底上形成覆盖透明衬底的预定区域的绝缘层;
在所述绝缘层上形成单晶硅层;
在单晶硅层的预定区域上依次形成栅极绝缘层和栅电极;以及
向围绕所述栅电极的单晶硅层中注入掺杂剂。
7.如权利要求6所述的方法,其中,所述绝缘层的形成包括:
在所述透明衬底的预定区域上形成沟槽;以及
采用绝缘层填充所述沟槽。
8.如权利要求6所述的方法,其中,在所述绝缘层的形成过程中,在所述透明衬底的预定区域上形成绝缘层。
9.如权利要求7所述的方法,其中,所述单晶硅层的形成进一步包括:
在所述蓝宝石衬底上围绕所述绝缘层形成单晶硅层;
在所述绝缘层和单晶硅层上形成非晶硅层;
使在所述绝缘层上形成的非晶硅层结晶成单晶硅层;以及
去除围绕所述绝缘层的单晶硅层。
10.如权利要求9所述的方法,其中,使形成于所述绝缘层上的非晶硅层结晶为单晶硅层进一步包括下述步骤:
2a1、使在所述单晶硅层的形成过程中形成的单晶硅层上的非晶硅层结晶为单晶硅层;以及
2a2、向在步骤2a1中形成的所述单晶硅层和在所述绝缘层上形成的所述非晶硅层上照射激光。
11.如权利要求10所述的方法,其中,通过垂直固相外延工艺,使在步骤2a1中形成于所述单晶硅层上的所述非晶硅层结晶为单晶硅层。
12.如权利要求6所述的方法,其中,所述绝缘层由氧化硅膜和氮化硅膜之一形成。
13.如权利要求9所述的方法,其中,所述非晶硅层形成至一定厚度,使得在非晶硅层的结晶过程中形成的单晶硅层的厚度为100nm或更小。
14.如权利要求6所述的方法,其中,所述透明衬底为以(1102)面为上表面的蓝宝石衬底。
15.如权利要求8所述的方法,其中,在所述绝缘层上形成单晶硅层进一步包括:
在所述蓝宝石衬底上围绕所述绝缘层形成与所述绝缘层具有相同高度的单晶硅层;
在所述绝缘层和单晶硅层上形成非晶硅层;
使在所述绝缘层上形成的非晶硅层结晶成单晶硅层;以及
去除围绕所述绝缘层的单晶硅层。
16.如权利要求15所述的方法,其中,使形成于所述绝缘层上的非晶硅层结晶为单晶硅层进一步包括下述步骤:
2a1、使在所述单晶硅层的形成过程中形成的单晶硅层上的非晶硅层结晶为单晶硅层;以及
2a2、向在步骤2a1中形成的所述单晶硅层和在所述绝缘层上形成的非晶硅层上照射激光。
17.如权利要求16所述的方法,其中,通过垂直固相外延工艺,使在步骤2a1中形成于所述单晶硅层上的非晶硅层结晶为单晶硅层。
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-
2004
- 2004-10-13 KR KR1020040081760A patent/KR100682893B1/ko active IP Right Grant
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2005
- 2005-10-13 CN CNA2005101140077A patent/CN1770476A/zh active Pending
- 2005-10-13 JP JP2005299175A patent/JP2006114913A/ja active Pending
- 2005-10-13 US US11/248,620 patent/US7511381B2/en active Active
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CN102540539A (zh) * | 2012-02-22 | 2012-07-04 | 信利半导体有限公司 | 一种广视角液晶显示器 |
Also Published As
Publication number | Publication date |
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US20060094212A1 (en) | 2006-05-04 |
KR100682893B1 (ko) | 2007-02-15 |
JP2006114913A (ja) | 2006-04-27 |
US8021936B2 (en) | 2011-09-20 |
KR20060032792A (ko) | 2006-04-18 |
US20090191673A1 (en) | 2009-07-30 |
US7511381B2 (en) | 2009-03-31 |
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