CN1815628B - Method and circuit for configuring programmable device - Google Patents
Method and circuit for configuring programmable device Download PDFInfo
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- CN1815628B CN1815628B CN2005101287616A CN200510128761A CN1815628B CN 1815628 B CN1815628 B CN 1815628B CN 2005101287616 A CN2005101287616 A CN 2005101287616A CN 200510128761 A CN200510128761 A CN 200510128761A CN 1815628 B CN1815628 B CN 1815628B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17732—Macroblocks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17758—Structural details of configuration resources for speeding up configuration or reconfiguration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17768—Structural details of configuration resources for security
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17772—Structural details of configuration resources for powering on or off
Abstract
Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.
Description
Background of invention
The invention provides the technology that is used for going up combination volatibility and Nonvolatile programmable logic, especially provide to be used to provide to have by the part of non-FPGA (Field Programmable Gate Array) of carrying memory configurations and carry the IC technology of another part of the FPGA (Field Programmable Gate Array) of non-volatile memory configuration by sheet at integrated circuit (IC).
Configuration data comprises the bigger field programmable gate array (FPGA) that sheet carries the volatile memory piece and when powering up, need dispose suitable time quantum usually, because will be loaded on the chip from external memory chip.For example, external memory chip can be serial ROM (SROM).
Less complex programmable logic device (CPLD) such as the MAX of Altera series CPLD comprises the nonvolatile memory that sheet carries.Configuration data is deposited in the nonvolatile memory that this sheet carries.When powering up, the nonvolatile memory that can carry from sheet apace is written into FPGA (Field Programmable Gate Array) with configuration data.Non-volatile CPLD is actually momentary connection when powering up, and does not need the exterior arrangement data.But making the big FPGA with all nonvolatile memories is also can limit procedure selecting of forbidding aspect area.
Many bigger volatibility FPGA have the CPLD of following and power up and layoutprocedure with cooperation.CPLD also can be before being sent to FPGA encrypted configuration data, intercepted and duplicated to prevent this configuration data.But this technology is complicated more, because it makes that bigger FPGA becomes three device solves schemes that comprise FPGA, SROM and CPLD.U.S. Pat 7190190 discloses a kind of programmable logic device that has non-volatile user memory in the chip.
Therefore, technology disposes field programmable gate array to expect to provide faster.Also expect during the user is provided at layoutprocedure, suitably to guarantee the method for their designs.
Summary of the invention
The invention provides the technology that is used for volatibility and Nonvolatile programmable logical groups are incorporated into an integrated circuit (IC).IC of the present invention is divided into two parts.Part IC comprises first programmable logic block, and it is carried the bit configuration of storing in the non-volatile memory block by sheet.Another part IC comprises second programmable logic block that carries the bit configuration of storing in the storage arrangement by non-.
The sub-fraction of the logic in configurable volatibility part is in the time, and the logic in the non-volatile part of IC can be configured and complete functionalization.Logic in the non-volatile part is enough soon and have enough independence configurable, with the configuration in the volatibility part that helps IC.Nonvolatile memory also can provide safety feature to user's design, such as encryption and decryption.
Consider the following detailed description and accompanying drawing, other purpose of the present invention, characteristics and advantage will become apparent, and wherein identical label is represented like in institute's drawings attached.
Description of drawings
Fig. 1 shows according to carrying the programmable logic block of non-volatile memory configuration and by non-IC that carries the programmable logic block of memory configurations comprising by sheet of first embodiment of the invention.
Fig. 2 shows the IC shown in Figure 1 that sheet carries non-volatile memory block that has according to second embodiment of the invention, and this sheet carries the configuration data that non-volatile memory block is enough to store user and manufacturer.
Fig. 3 A shows according to having to the HIP piece of third embodiment of the invention (HIP) piece of the hard intelligence power (intellectual property) on the FPGA (Field Programmable Gate Array) IC of programmable register group of program capability is provided.
Fig. 3 B shows according to the HIP piece able to programme that comprises Fig. 3 A of fourth embodiment of the invention with by non-IC that carries the programmable logic block of memory configurations.
Fig. 4 is the simplified block diagram of the programmable logic device that can use with technology of the present invention.
Fig. 5 is the block diagram that can realize the electronic system of the embodiment of the invention.
Embodiment
Fig. 1 shows the part 100 according to the programming logic integrated circuit (IC) of first embodiment of the invention design.Part 100 comprises the Nonvolatile programmable logical block 110 and the volatibility programmable logic block 130 of FPGA (Field Programmable Gate Array).Nonvolatile programmable logical block 110 and volatibility programmable logic block 130 all comprise Programmable Logic Device.For example, Programmable Logic Device can be based on lookup table or based on the logical block of product item (product term).The framework of the programmable logic array in the programmable logic block 110 and 130 can be identical or different. Programmable logic block 110 and 130 also can comprise storer.Storer in the programmable logic block 110 and 130 for example can be the volatile memory such as sram cell.
FPGA (Field Programmable Gate Array) in the programmable logic block 110 is configured by the configuration bit of storage in the nonvolatile memory 112.Configuration bit can deposit nonvolatile memory 112 in by manufacturer or user.Power-on-reset (POR) configuration block 111 is conveyed into storer in the programmable logic block 110 with configuration bit from nonvolatile memory 112.
FPGA (Field Programmable Gate Array) in the programmable logic block 130 is by the configuration bit configuration of storing in the external memory.External memory devices for example can be flash memory device or serial ROM (SROM) storage arrangement.Configuration bit can be written into configuration (ISC) piece 131 programmable logic block 130 and the system by multiplexer 118 from I/O port one 03.
Suitable setup time when as mentioned above, many big FPGA need to power up.On the other hand, little non-volatile CPLD be actually momentary connection when powering up and do not need the exterior arrangement data.But, need too many die area to place enough sheets and carry nonvolatile memory on big FPGA, to dispose the Programmable Logic Device of all FPGA.
The present invention solves these problems by two programmable logic blocks (110 and 130) are provided.During switching on by load the configuration datas FPGA (Field Programmable Gate Array) the configurating programmable logical block 110 fast from non-volatile memory block 112.Programmable logic block 110 preferably comprises enough FPGA (Field Programmable Gate Array) some critical function to need during execution powers up the stage before configurating programmable logical block 130 to carry out.By the configuration data that loads from external source configurating programmable logical block 130 more lentamente.
According to an embodiment, the most FPGA (Field Programmable Gate Array) on the IC reside in the volatibility programmable logic block 130.Among this embodiment, non-volatile memory block 112 only needs enough big, so that be the FPGA (Field Programmable Gate Array) store configuration data in the programmable logic block 110.If programmable logic block 110 is less relatively, then the size of non-volatile memory block 112 can be less relatively.This requirement makes the die area influence of the non-volatile memory block 112 on the IC minimum.For example, programmable logic block 130 can power up all FPGA functions of back execution.
If non-volatile memory block 112 sizes are littler, may with regard to deployable more realizations.For example, the state-of-the-art EEPROM of big non-volatile memory block needs or the FLASH technology that are used for whole FPGA.The little non-volatile memory block 112 that only is provided for the configuration data of fraction FPGA can be used the memory technology that melts (polyfuse) arrays and magnetic resistance ROM such as more.
The specific example of programmable logic block 110 executable functions is discussed now.Before configuration and full functionality FPGA, need control system to reset and minimum detectable signal.Big FPGA plays central role in its system.If FPGA drives minimum detectable signal, resets or bus, then it will be before configuration can not be effectively or drive signal correctly.Inertia between energising and the configuration can stop system suitably to be switched on.In order to address these problems, programmable logic block 110 can be during switching on the Control Critical signal.
Before configuration FPGA and afterwards, also may command configuration and order reset for programmable logic block 110.Programmable logic block 110 can directly drive volatibility FPGA block reset under the situation of not using exterior I O signal.
As another example, programmable logic block 110 can be used for protecting the configuration data that sends to programmable logic block 130.Programmable logic block 110 can protectively read as CPLD, and can have the internal by-pass of configuration (ISC) piece 131 in the arrival system.Programmable logic block 110 can be carried out the inaccessible additional data encrypt/decrypt of outside lead.
For example, the logic in the programmable logic block 110 can be configured when energising, carries out decrypt scheme with the cryptographic algorithm based on storage in the non-volatile memory block 112.Subsequently, the configuration data that is used for programmable logic block 130 is written into programmable logic block 110 and decrypted by I/O port one 03.Subsequently, the configuration data of deciphering is written into programmable logic block 130 (for example, direct or process multiplexer 118) from programmable logic block 110.
When the configuration data that is used for FPGA not when the SROM of special use loads, it loads from standard FLASH device or processor bus usually.Before configuration FPGA, effective some logic when arbitrary solution all needs to switch on.This logic sorts and data is sent to FPGA configuration lead-in wire (ISC port) from non-volatile source of data.This logic is benefited from the realization of FPGA inside, because it can hold the Nonvolatile memory devices of the relative broad range that comprises processor and the FPGA configuration mode of relative broad range.
With reference to figure 1, the part 100 of IC comprises six regional 101-106.Among six regional 101-106 each all comprises on-reset circuit (POR1-POR6) separately.The on-reset circuit monitoring is from the supply voltage of one or more power rails (or power net).On-reset circuit produces output signal, and when its indication reaches predetermined level from the supply voltage of power source-responsive rail.When the specific region of predetermined power source voltage level indication IC can begin to work safely.For example, on-reset circuit POR1 produces an output signal, and when its indication supply voltage is increased to the minimum voltage level of circuit to come into operation that is suitable in the zone 101 after energising.
But circuit region separated into two parts shown in Figure 1.First comprises regional 101-104.Zone 101-104 is associated with non-volatile memory block 112 and programmable logic block 110.Zone 105-106 is associated with programmable logic block 130.
111 controls of POR configuration block and monitoring on-reset circuit POR1-POR6.As long as on-reset circuit POR1-POR4 indication supply voltage has reached the level accepted among the regional 101-104, POR configuration block 111 just is sent to Nonvolatile programmable logical block 110 with configuration data stored in the non-volatile memory block 112.
Therefore, as long as the power supply among the regional 101-104 has reached predetermined level, POR1-POR4 is disposed with regard to allowing the FPGA (Field Programmable Gate Array) in the programmable logic block 110, and switches on without waiting area 105-106.The configuration of this embodiment programmable logic block 110 during energising provides addition speed.
In case on-reset circuit POR5-POR6 indication power supply has reached the level accepted among the regional 105-106, then configuration data can be written into programmable logic block 130 through multiplexer 118 and ISC piece 131 from external source in the system.The selection input of the FPGA (Field Programmable Gate Array) may command multiplexer 118 in POR configuration block 111 or the programmable logic block 110.
In FPGA embodiment shown in Figure 1, configuration (ISC) I/O port and Nonvolatile programmable logical block 110 and volatibility programmable logic block 130 interfaces in the system in the zone 103.
Perhaps, the ISC data can be written into Nonvolatile programmable logical block 110, are written into programmable logic block 130 subsequently.The ISC configuration data can directly be loaded into programmable logic block 130 from programmable logic block 110 or through multiplexer 118 and ISC piece 131, shown in the arrow among Fig. 1.Before it was written into programmable logic block 130, the FPGA (Field Programmable Gate Array) in the programmable logic block 110 can be encrypted the ISC configuration data, with protection client's circuit design.
When removing electricity, non-volatile memory block 112 is not lost its data pattern.For example, non-volatile memory block 112 can be used for keeping FPGA configuration file and volatibility FPGA redundant information.Non-volatile memory block 112 can realize by many modes.For example, non-volatile memory block 112 can be the metal fuse storer with disposable programmable memory unit.Other example of non-volatile memory block 112 comprises programmable anti-molten array, metal or many mask-programmables array, flash array, eeprom memory array, LASER programmable fuse array, magnetoresistive memory array (MRAM) and ferroelectric memory array (FeRAM).The reduced size of non-volatile memory block 112 has increased its density possibility.
ISC port in JTAG I/O test port in the non-volatile memory block 112 accessible region territories 102 or the zone 103 is programmed.If the I/O port is not controlled programmable logic block 110, the ISC I/O port that Nonvolatile programmable logical block 110 is gone back in the accessible region territory 103 is programmed.But subclass and some universal internal routing interconnect line than smaller subset, all ISC IO, internal reset and clock bus of Nonvolatile programmable logical block 110 access universal I.
IO and configuration and ISC source multiplexer 121 and 122 that POR configuration block 111 is gone back in the control area 104.POR configuration block 111 can will be written into the I/O memory bank of zone in 104 from the configuration data of non-volatile memory block 112 by multiplexer 122, with the IO port in the configuring area 104.In addition, if POR configuration block 111 allows, volatibility ISC piece 131 can reconfigure POR4IO piece 104.
Fig. 2 illustrates the second embodiment of the present invention.According to this embodiment, can deposit two set of configuration data in non-volatile memory block 112.First set of configuration data is a bootmode, and it is programmed so that for all clients provide FPGA standard feature, such as ASSP by manufacturer.The advantage of this embodiment is to allow FPGA manufacturer to change Product Definition in time by the simple change that the output manufacturing test is flowed.
In case the user has defined an application, then the user can be with additional configurations data write non-volatile memory piece 112.For example, the user can deposit non-volatile memory block 112 by diagnosis pattern operation FPGA in the configuration data of testing various signals with being used for.
In OTP type nonvolatile memory, in non-volatile memory block 112, need two subregions.A subregion is used to store the default Boot Configuration Data of manufacturer, and a subregion is used to store user's configuration data, to satisfy user's special requirement better.The subregion that is used for non-volatile memory block 112 has been shown among Fig. 2.If detect valid data in user partition, then configuration logic can be skipped boot configuration.
In the embodiment of Fig. 2, non-volatile memory block 112 has enough storeies, so that it can store two set of configuration data that are used for programmable logic block 110.According to other embodiments of the invention, non-volatile memory block 112 can be stored two set of configuration data that surpass that are used for programmable logic block 110.But the N haplotype data of non-volatile memory block 112 in non-volatile memory block 112 storage maps 1 among Fig. 2, wherein N is the quantity of the required set of configuration data of configurating programmable logical block 110.
Fig. 3 A shows another embodiment of the present invention.Many programming logic integrated circuits now all have hard intelligence power (HIP) piece.The HIP piece is by the part of hardwire with the special IC (ASIC) of execution predetermined function.When a large amount of clients needed identical function, manufacturer added the HIP piece to FPGA (Field Programmable Gate Array) IC.When carrying out specific function, ASIC is more effective than FPGA usually.But the dirigibility of ASIC can not show a candle to FPGA, because they can only be carried out by the hard wired function of mask set.
Usually, FPGA client has similar (but the non-unanimity) requirement to the particular type circuit function.In these examples, expectation provides the HIP piece of some built-in program capability to FPGA.Embodiment shown in Fig. 3 A provides built-in program capability in the HIP piece with the form of programmable register group, and this will be in following detailed description.The programmable register group has promoted the dirigibility of HIP piece.
Fig. 3 A shows the block diagram of the initialized registers group of CRAM in the HIP piece 301 on the FPGA (Field Programmable Gate Array) IC.The block diagram of Fig. 3 A shows the user model configuration interface 320 that can be reconfigured during user model, be used for the FPGA initialized configuration RAM of configuration (CRAM) 312, and the programmable register group 330 that mode initialization is outputed to IP logic 335.
During energising, defaultization writes logic 322, so that multiplexer 325 is by being set at CRAM_n_Config ' 1 ' and Write_En is set at ' 1 ' selects CRAM interface 312.During FPGA configuration cycle, loading programmable IC CRAM bit.When entering user model, programmable I C core is asserted (assert) User_Mode signal, and clock signal begins to switch (toggle).Can in writing logic 322, realize based on the synchronous self clock circuit that the User_Mode signal is asserted, be sampled into programmable register group 330 as default settings to guarantee the CRAM value.
Writing logic 322 can come switching multiplexing device 325 by CRAM_n_Config being set at ' 0 ', to select user model configuration interface 320.During the user model, by being written into programmable register group 330 by user model configuration interface 320 from the data of user's pattern configurations controller 310, the output valve of programmable register group 330 can change by (the bus protocol scheme) write cycle.User model Configuration Control Unit 310 (shown in fpga core 302) is implemented as the programmable logic block according to the configuration data configuration set usually.Programmable register group 330 is embodied as the register of memory mapped usually.
The embodiment of Fig. 3 A has several advantages.For example, this embodiment provides better test to cover to the connection from CRAM to the registers group.Only compare with wherein correct CRAM setting, because the structural property of test has also reduced the test duration by the conventional IP functional test scheme of operation IP functional test vector verification.But, it seems that from the viewpoint of die area cost this embodiment is not suitable for very large registers group.
According to another embodiment of the present invention, HIP piece 301 able to programme can replace the programmable logic block 110 among Fig. 1 or Fig. 2.Fig. 3 B shows this embodiment.Fig. 3 B allows HIP piece 301 work able to programme irrelevant with volatibility programmable logic block 310.
Fig. 3 B also only maximizes the ability of the momentary connection of HIP piece 301 with a small amount of programming.Because the HIP piece 301 among Fig. 3 B only needs to be stored in a small amount of configuration data in the non-volatile memory block 112, so can realize depositing non-volatile memory block 112 with the storer of many types (for example, many molten, magnetic resistance ROM etc.).
The embodiment of Fig. 3 B illustrates HIP piece 301 able to programme not to be needed consistent with 130 framework.HIP piece 301 able to programme and 130 framework only need to have the program capability of par.Also expectation (but inessential), HIP piece 301 able to programme need obviously be less than the configuration bit of programmable logic block 130.The area of HIP piece 301 able to programme and complicacy usually needn't be littler.
Fig. 4 is the simplification part block diagram of an example that can comprise the PLD400 of each side of the present invention.Though mainly in the environment of PLD and FPGA, the present invention is discussed, should understands the programmable integrated circuit that the present invention can be applicable to many types.PLD400 is other example that can realize the programmable integrated circuit of technology of the present invention.PLD400 comprises the two-dimensional array of programmable logic array piece (or LAB) 402, and they are interconnected by the network of the row and column interconnection of variation length and speed.Logical block (or LE) that LAB402 comprises a plurality of (for example, 10).
LE provides the programmable logic block of the effective realization that is used for user-defined logic function.PLD has many logical blocks, and they can be configured to realize various combinations and order function.Logical block has the programmable interconnect structure of leading to.Programmable interconnect structure can be programmed, with the logical block in the almost any desired configuration of interconnection.
PLD400 also comprises the distributed storage structure, and it comprises the RAM piece that spreads all over the variable-size that array provides.For example, this RAM piece comprises 512 bit blocks 404,4K piece 406 and the piece 408 of 512K bit RAM is provided.These memory blocks also can comprise shift register and fifo buffer.
PLD400 also comprises digital signal processing (DSP) piece 410, and it for example can realize having the multiplier of the characteristics of adding deduct.Be arranged near the I/O element (IOE) in device periphery 412 in this embodiment and support many single-ended and difference I/O standards.Should be understood that describing PLD400 here is only for illustration purpose, and the present invention can realize in many dissimilar PLD, FPGA etc.
Though the PLD of type shown in Figure 4 provides and has realized also helping the required many resources of system-level solution, the present invention wherein PLD is the system of one of several assemblies.Fig. 5 shows the block diagram that wherein can embody exemplary digital of the present invention system 500.Exemplary digital system 500 can be digital computing system, digital information processing system, special number handover network or other disposal system of programming.In addition, this system can be designed for various application, such as telecommunication system, automotive system, control system, consumption electronic product, personal computer, Internet traffic and networking etc.In addition, exemplary digital system 500 can be arranged on the single plate, on a plurality of plate or in a plurality of encapsulation.
Exemplary digital system 500 comprises by one or more bus interconnections processing unit 502, storer 504 and I/O unit 506 together.According to this exemplary embodiment, programmable logic device (PLD) 508 embeds in the processing unit 502.PLD508 can be used for many different purposes in the system of Fig. 5.PLD508 for example can be that the logic of processing unit 502 makes up piece, supports its inside and outside operation.PLD508 is programmed to be implemented in and carries out the necessary logic function of its special role in the system operation.PLD508 can be coupled to storer 504 specially and be coupled to I/O 506 by connecting 512 by connecting 510.
For example, but the logical operation of one or more PLD508 replaced C PU control system.In one embodiment, PLD508 is as reconfigurable processor, and it can be reprogrammed on demand to handle specific calculation task.Perhaps, but programmable logic device 508 self comprises the microprocessor of embedding.Memory cell 504 can be random-access memory (ram), ROM (read-only memory) (ROM), fixing or flexible disk media, PC card flash memory disk storer, tape or any other memory storage, or the combination of these memory storages.
Though described the present invention with reference to its specific embodiments here, comprised the scope of modification, various variation and replacement among the present invention.In some instances, can under the situation of not corresponding other characteristics of use, adopt characteristics of the present invention, and not deviate from described scope of the present invention.Therefore, can carry out particular arrangement or method that many modifications are disclosed to adapt to, and not deviate from essence spirit of the present invention and scope.The present invention is intended to be not limited to the specific embodiments that disclosed, and the present invention will comprise all embodiment and the equivalent that belongs in claims scope.
Claims (23)
1. integrated circuit comprises:
Programmable logic block; And
The programmable hard intelligence power of part piece, it comprises programmable register group and special circuit and is coupled with described programmable logic block, wherein the programmable register group is configured to control the function of the subclass of described special circuit;
Wherein, the logical circuit in the programmable hard intelligence power piece of described part receives configuration data and described configuration data is written into described programmable register group.
2. integrated circuit as claimed in claim 1 is characterized in that, during described integrated circuit energising, described logical circuit is written into described programmable register group with described configuration data from configuration random-access memory.
3. integrated circuit as claimed in claim 1 is characterized in that, described logical circuit is written into described programmable register group from the user model Configuration Control Unit by the user model configuration interface with described configuration data.
4. integrated device electronics comprises:
Nonvolatile memory;
First circuit, it comprises the FPGA (Field Programmable Gate Array) that can be disposed by the data of storing in the described nonvolatile memory; And
Second circuit, wherein when disposing the FPGA (Field Programmable Gate Array) of described first circuit, described first circuit is assisted the configuration of the FPGA (Field Programmable Gate Array) of described second circuit, and the configuration of the FPGA (Field Programmable Gate Array) of wherein said second circuit is used from other data of the external source of described integrated device electronics and finished.
5. integrated device electronics as claimed in claim 4 is characterized in that, described first circuit comprises the programmable hard intelligence power piece of part, and this hard intelligence power piece comprises programmable register group and special circuit.
6. integrated device electronics as claimed in claim 4 is characterized in that, described first circuit is used for by sending described other data to configuration that described second circuit is assisted the FPGA (Field Programmable Gate Array) of described second circuit through described first circuit.
7. integrated device electronics as claimed in claim 4 is characterized in that, also comprises:
The one I/O piece;
First multiplexer, it has first input end, second input terminal that is coupled to described first circuit that is coupled to a described I/O piece, the selection input of being coupled to the lead-out terminal of configuration block in the system and being coupled to described first circuit.
8. integrated device electronics as claimed in claim 7 is characterized in that, also comprises:
The 2nd I/O piece; And
Second multiplexer, second input terminal that has the lead-out terminal that is coupled to described the 2nd I/O piece, first input end that is coupled to described first circuit and be coupled to described second circuit.
9. an integrated circuit comprises
First programmable logic block;
First on-reset circuit, it provides first output signal to described first programmable logic block, can start working to indicate described first programmable logic block;
Second programmable logic block; And
Second on-reset circuit, it provides second output signal to described second programmable logic block, can start working to indicate described second programmable logic block, wherein, described first on-reset circuit separates with described second on-reset circuit, and wherein said first programmable logic block was started working before described second programmable logic block.
10. integrated circuit as claimed in claim 9 is characterized in that, described first programmable logic block can be with being configured than the described second programmable logic block less time.
11. integrated circuit as claimed in claim 9 is characterized in that, described first programmable logic block is less than described second programmable logic block.
12. the method for a collocating integrate circuit equipment comprises:
When the first programmable circuit piece in the described integrated device electronics is in total power, produce first signal;
When the second programmable circuit piece in the described integrated device electronics is in total power, produce secondary signal;
After producing described first signal, dispose the described first programmable circuit piece, the wherein said first programmable circuit piece is configured by the data that the non-volatile memory block in described integrated device electronics receives; And
After producing described secondary signal and disposing the described first programmable circuit piece, dispose the described second programmable circuit piece, the wherein said second programmable circuit piece is configured by the data that the external source from described integrated device electronics receives, and the described first programmable circuit piece is used to dispose the described second programmable circuit piece.
13. the method for a collocating integrate circuit equipment comprises:
Non-volatile memory block from described integrated device electronics is fetched first data;
With described first data first programmable circuit piece in the described integrated device electronics is configured;
Receive second data from the external source of described integrated device electronics; And
The described first programmable circuit piece that use is configured is configured the second programmable circuit piece in the described integrated device electronics with described second data.
14. an integrated circuit comprises:
Programmable circuit; And
Nonvolatile memory, wherein, described nonvolatile memory is stored the configuration data of default bootmode in first, and can be configured in second portion storage user configuration data, wherein, when not detecting valid data in described second portion, described default bootmode is controlled the configuration of described programmable circuit, and wherein when in described second portion, detecting valid data, use described valid data to dispose described programmable circuit.
15. a method of operating integrated circuit comprises:
Determine whether first subregion of the non-volatile memory block in the described integrated circuit has stored effective user data;
When in described first subregion, having stored effective user data, dispose the first programmable circuit piece in the described integrated circuit with this effective user data; And
When not storing effective user data in described first subregion, use the configuration data of the default bootmode in second subregion that is stored in described non-volatile memory block to dispose the described first programmable circuit piece.
16. method as claimed in claim 15 is characterized in that, also comprises:
The first programmable circuit piece that use is disposed disposes the second programmable circuit piece in the described integrated circuit.
17. a method of operating integrated circuit comprises:
In described integrated circuit, deposit the configuration data of the bootmode that standard feature is provided in first subregion of non-volatile memory block in;
Receive user's configuration data from the user;
In described integrated circuit, deposit described user's configuration data in second subregion of non-volatile memory block in; And
Configuration data and described user's configuration data with described bootmode are configured the first programmable circuit piece in the described integrated circuit.
18. method as claimed in claim 17 is characterized in that, also comprises:
The first programmable circuit piece that use is disposed disposes the second programmable circuit piece in the described integrated circuit.
19. an integrated circuit comprises:
FPGA (Field Programmable Gate Array); And
The programmable hard intelligence power piece of part, it comprises programmable register group and special circuit, wherein said programmable register group can be configured to control the function of described special circuit, and wherein, circuit in the described FPGA (Field Programmable Gate Array) is used to receive configuration data and described configuration data is written into described programmable register group, wherein during described integrated circuit energising, described configuration data is written into described programmable register group.
20. integrated circuit as claimed in claim 19 is characterized in that, the circuit in described FPGA (Field Programmable Gate Array) that is used for configuration data is written into described programmable register group comprises the nonvolatile memory that is used for storing described configuration data.
21. integrated circuit as claimed in claim 19 is characterized in that, described configuration data is fetched from the external source of described integrated circuit.
22. integrated circuit as claimed in claim 19, it is characterized in that, the circuit in described FPGA (Field Programmable Gate Array) that is used for configuration data is written into described programmable register group comprises the user model Configuration Control Unit, and this user model Configuration Control Unit transmits described configuration data by the user model configuration interface in the programmable hard intelligence power piece of described part.
23. integrated circuit as claimed in claim 22, it is characterized in that, the circuit in described FPGA (Field Programmable Gate Array) that is used for configuration data is written into described programmable register group also comprises configuration random-access memory, wherein, the programmable circuit of described part also comprises multiplexer, be used between described user model configuration interface and configuration random-access memory, selecting, configuration data is written into described programmable register group.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/003,586 US7242218B2 (en) | 2004-12-02 | 2004-12-02 | Techniques for combining volatile and non-volatile programmable logic on an integrated circuit |
| US11/003,586 | 2004-12-02 |
Publications (2)
| Publication Number | Publication Date |
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| CN1815628A CN1815628A (en) | 2006-08-09 |
| CN1815628B true CN1815628B (en) | 2010-10-27 |
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| US (1) | US7242218B2 (en) |
| EP (1) | EP1667327A3 (en) |
| JP (1) | JP4249745B2 (en) |
| CN (1) | CN1815628B (en) |
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| JP4249745B2 (en) | 2009-04-08 |
| US7242218B2 (en) | 2007-07-10 |
| EP1667327A2 (en) | 2006-06-07 |
| JP2006166430A (en) | 2006-06-22 |
| US20060119384A1 (en) | 2006-06-08 |
| CN1815628A (en) | 2006-08-09 |
| EP1667327A3 (en) | 2010-05-19 |
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