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Numéro de publicationCN1841978 B
Type de publicationOctroi
Numéro de demandeCN 200510063022
Date de publication14 sept. 2011
Date de dépôt1 avr. 2005
Date de priorité1 avr. 2005
Autre référence de publicationCN1841978A
Numéro de publication200510063022.3, CN 1841978 B, CN 1841978B, CN 200510063022, CN-B-1841978, CN1841978 B, CN1841978B, CN200510063022, CN200510063022.3
Inventeurs邓莉, 黄浩
Déposant大唐电信科技股份有限公司
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes:  SIPO, Espacenet
Method and apparatus for realizing multipath signal re-timing
CN 1841978 B
Résumé
The invention discloses a method for achieving multi-path signal re-timing, especially to the re-timing of multi-path E1, T1 or other low speed signal. It uses a high speed clock source to generate a high frequency clock signal as system clock; the system clock generates a plurality of time slots; each time slot comprises a plurality of system clock periods; it separately stores the sampled low speed signal data in RAM and reads the data of all the paths of a time slot, which achieves each path synchronic processing.
Revendications(8)  Langue du texte original : Chinois
1. 一种实现多路信号再定时的方法,应用于SDH系统中多路低速信号的再定时,其特征在于,包括:(1)锁存每一路的数据,并产生每一路的写地址和公共的读地址;所述公共的读地址是指:为所述每一路共用的读地址;(2)由系统时钟产生若干时隙,所述时隙分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙;(3)在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中;(4)在读时隙到来时,将所有路的数据并行读出;其中,所述系统时钟的频率大于MX低速信号频率X (路数+1),M为RAM读数据、改写数据、写入数据所需周期数之和;RAM的宽度等于低速信号的路数,RAM的深度根据系统允许最大、最小缓存时间选取。 A multi-channel signal retiming method, applied to SDH systems in low-speed multi-channel re-timing signal, comprising: (1) each way latched data, and generates a write address and each way read address public; the public address refers to read: For each path shared the read address; (2) a plurality of slots generated by the system clock, the time slot for each channel data into serial write the RAM write and read time slots slot all the way to the data read out in parallel; (3) in each of the write-time slot arrives, the write time slot corresponding to the way data is written to latch RAM (Random Access Memory ); and (4) in the read slot arrives, the data read out in parallel all the road; wherein the frequency of the system clock frequency is greater than the MX-speed signals X (large ones +1), M of RAM to read data, rewritable data write data and the required number of cycles; RAM is equal to the width of the low-speed signal large ones, according to the depth of RAM system allows maximum and minimum cache time selection.
2.如权利要求1所述的实现多路信号再定时的方法,其特征在于,步骤(1)之前还包括:将所述系统时钟的频率设置为大于MX低速信号频率X (路数+1),M为RAM读数据、 改写数据、写入数据所需周期数之和;将RAM的宽度设置为N个低速信号的路数。 2. The multi-channel signal retiming implemented method according to claim 1, characterized in that, further comprising the step (1) prior to: the system clock frequency is set to be greater than MX low frequency signal X (large ones +1 ), M of RAM to read data, overwrite the data, the number of write cycles and data required; the width of the RAM is set to a low-speed signal N large ones.
3 如权利要求1或2所述的实现多路信号再定时的方法,其特征在于,步骤(3)将所述写时隙对应路锁存的数据写入RAM中,具体为:先读出该路写地址对应的RAM存储单元中的数据,再将该路锁存的数据置入该路对应BIT特位,写入该路写地址对应的RAM存储单元中,并将其他路的BIT位数据保持不变。 3, such as multi-channel signal retiming implemented method of claim 1 or claim 2, wherein step (3) the time slot corresponding to the road latched write data is written to RAM, in particular: first read The way to write data corresponding to the address RAM storage unit, and then the way the data latched into the path corresponding to the BIT bit special, written in the way the write address corresponding RAM memory cells, and the other way of BIT bits data remain unchanged.
4.如权利要求1或2所述的实现多路信号再定时的方法,其特征在于,步骤(3)将所述写时隙对应路锁存的数据写入RAM中具体为:先将该路锁存的数据写入RAM中该路写地址对应的存储单元,然后修改该路的写地址。 The multi-channel signal retiming implemented method according to claim 1 or claim 2, characterized in that, in step (3) the time slot corresponding to the write data latch circuit is written in the RAM in particular: The first Road latched data is written to the RAM write address corresponding to the path of the memory cell, and then modify the path of the write address.
5.如权利要求4所述的实现多路信号再定时的方法,其特征在于,所述修改该路的写地址包括将写地址加一或加X,所述X为RAM深度一半。 5. The multi-channel signal retiming implemented method according to claim 4, characterized in that said modifying the write address path including a write address plus one or plus X, wherein X is half the RAM depth.
6.如权利要求1或2所述的实现多路信号再定时的方法,其特征在于,步骤(4)具体为:在读时隙到来时,读取读地址对应的存储单元的N个数据,然后修改所述读地址,所述N为信号路数,所述修改读地址包括将读地址加一。 6. The multiplex signal retiming implemented method according to claim 1 or claim 2, characterized in that, in step (4) specifically: When the arrival of the read time slot, the read address of the read data corresponding to N memory cells, then modify the read address, the N signal large ones, including the modified read address read address plus one.
7. 一种实现多路信号再定时的装置,应用于SDH系统中多路低速信号的再定时,其特征在于,包括:时隙分配单元、锁存单元和控制子单元,其中:锁存单元:锁存每一路的数据,并产生每一路的写地址和公共的读地址;所述公共的读地址是指:为所述每一路共用的读地址;时隙分配单元:由系统时钟产生若干时隙,所述时隙分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙;控制子单元:在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中;在读时隙到来时,将所有路的数据并行读出;其中,所述系统时钟的频率大于MX低速信号频率X (路数+1),M为RAM读数据、改写数据、写入数据所需周期数之和;所述RAM的宽度等于低速信号路数,RAM的深度根据系统允许最大、最小缓存时间选取。 A re-timing means to achieve multi-channel signal, applied to SDH systems in low-speed multi-channel re-timing signal, comprising: slot allocation unit, the latch unit and a control sub-unit, wherein: the latch unit : latched data each way, and generates a write address of each road and public read address; the common read address means: each path to the common read address; slot allocation unit: a number from the system clock generator time slot, the slot is divided into time slots for each channel to write the serial data is written and read RAM slot all the way in the parallel data readout; control sub-unit: Write in each time slot arrives , writing the write time slot corresponding to the road latched data RAM (random access memory); when reading slot arrives, the data read out in parallel all the road; wherein the frequency of the system clock frequency is greater than the MX-speed signals X (large ones +1), M is a read data RAM, rewritable data, write data and the number of cycles required; RAM is equal to the width of the low-speed signal large ones, according to the depth of the RAM system allows the maximum, minimum cache time selected .
8.如权利要求7所述的多路信号再定时的装置,其特征在于,所述RAM的深度为1024BIT、768BIT、512BIT 和256BIT 中的其中之一。 8. claim 7, wherein the multiplex signal retiming means, characterized in that the depth of the RAM is one 1024BIT, 768BIT, 512BIT and the 256BIT.
Description  Langue du texte original : Chinois

实现多路信号再定时的方法及装置 Method and apparatus for multi-channel signal retiming

技术领域 Technical Field

[0001] 本发明涉及通信领域,特别是将多路异步信号处理为多路同步信号的实现方法。 [0001] The present invention relates to the field of communications, in particular, the multi-channel signal processing to multiplex asynchronous implementation of the synchronization signal. 背景技术 Background

[0002] SDH系统(同步数字通信传输系统)广泛应用于现代高速电信网、高速因特网等重要传输体制中,对光纤,微波和卫星通信技术的发展都有重大意义。 [0002] SDH system (synchronous digital communications transmission systems) are widely used in modern high-speed telecommunications networks, high-speed Internet and other important transport system, the development of fiber optic, microwave and satellite communication technology has great significance. 在SDH系统中,数据适配时要经过映射或指针调整,然而在这个调整过程中,会引入数据的抖动和飘移,为了避免和减少这种情况发生时对同步定时带来的影响,需要进行信号定时处理。 In SDH systems, data mapping or adaptation pointer adjustment to go through, but in this adjustment process, will introduce jitter and drift data, in order to prevent and reduce the impact of this happens to bring synchronization timing, the need for signal timing process.

[0003] 请参阅图1,其为一SDH系统的结构示意图。 [0003] Please refer to FIG. 1, which is a structural diagram of an SDH system. 在本地传送网层中,SDH环大多采用多路El、T1或其它低速信号分别连接ADM (分插服用器)和CPE (客户端设备),而CPE往往用输入的数据信号提取同步定时,为了避免SDH指针调整引起的抖动对定时带来的影响, 需要进行再定时,以便获取高质量的同步信号。 In the local transport network layer, SDH ring mostly multiple, El, T1 or other low-speed signals are connected ADM (add-drop administration) and the CPE (customer premises equipment), and CPE often synchronization timing signal extracting input data, in order to to avoid affecting the jitter caused by pointer adjustments SDH timing to bring the need for re-timing in order to obtain high-quality synchronization signal.

[0004] 目前,通常通过缓存方式来实现多路信号再定时功能,由于RAM所占资源少,广泛用于缓存处理。 [0004] Currently, the usual way through the cache to achieve multi-channel signal retiming function, due to the small share of resources RAM, widely used caching. 参阅图2,为实现多路信号再定时方法的基本原理图。 See Figure 2 for the realization of multi-channel signal retiming basic schematic approach. 对每路信号采用一个双口RAM,在一个口将数据写入,在另一个口将数据读出。 For each channel signals using a dual-port RAM, the data is written in a port in another port to read the data. 写入的时钟采用从输入信号中提取出来的时钟,读出时钟采用再定时时钟,数据的写入与读出都在时钟沿上进行。 Write clock is extracted from the input signal out of the clock, read clock re-timing clock use, write and read out data are performed on the clock edge. 每一路信号都配以一个RAM,通过增加RAM的数量来实现多路信号的再定时功能。 Each channel signals are accompanied by a RAM, by increasing the amount of RAM to achieve retiming multiplexed signals. 并且,RAM—般直接采用FPGA芯片内的Block RAM(块存储单元)。 And, RAM- as directly within the FPGA chip Block RAM (memory cell block).

[0005] 上述实现多路信号再定时的方法存在以下缺陷: [0005] The above-mentioned multi-channel signal retiming method has the following drawbacks:

[0006] 第一.片内的时钟资源是有限的,对大多数可编程器件而言,时钟只能在系统资源允许范围内使用,当信号路数增加时,如果直接用信号时钟处理数据的话,往往会因时钟资源不够导致设计无法完成。 [0006] The first clock chip resources are limited, the majority of programmable devices, the clock can only be allowed within the scope of system resources, large ones when the signal increases, if the direct use word processing data clock signal , often due to insufficient resources lead to the design clock can not be completed.

[0007] 第二:每种诸如FPGA的可编程芯片的Block RAM的数量是有限的。 [0007] Second: Each Block RAM such as the number of FPGA programmable chips is limited. 随着需要定时的信号路数量的增多,相应的需要Block RAM的片数就增加。 With the increase in the number of required timing signal path, the corresponding number of pieces required Block RAM is increased. 然而,随着FPGA拥有的资源越多(比如,拥有的Block RAM片数增多),FPGA芯片的价格就越高。 However, with the FPGA has more resources (eg, RAM chip has increased the number of Block), FPGA chip, the higher the price. 即,随着网络的发展, 需要再定时的信号路数量增加,这就需要采用价格高的FPGA,由此导致成本高的缺陷。 That is, with the development of the network, need to increase the number of signal path timing, which requires the use of the high price of FPGA, thereby resulting in a high cost of defects.

[0008] 第三:一个Block RAM只存储一路信号,而每路信号是串行输入的,信号的位宽只有一位,因此一片BlockRAM只使用了Ibit (位)的宽度。 [0008] The third: a Block RAM stores only one signal, and each signal is a serial input signal only one bit wide, so a BlockRAM use only Ibit (bit) width. 请参阅图3,其为Block RAM的存储原理图。 See Figure 3, which is a schematic diagram of Block RAM memory. 每个Block RAM的存储单元都是由确定位数的宽度和确定位数的深度组成。 Each Block RAM memory cell is determined by the width and depth of the composition is determined digit digits. 很显然,一片BlockRAM只使用了Ibit(位)的宽度,造成大量的资源浪费。 Obviously, a BlockRAM use only Ibit (bit) width, causing a lot of waste of resources. 并且,多路信号再定时时需要和路数相应的BlockRAM片数,由此造成更大的资源浪费。 Also, the needs and the appropriate number of large ones BlockRAM-chip multi-channel signal retiming, thereby resulting in greater waste of resources.

发明内容 DISCLOSURE

[0009] 本发明的目的在于提供一种实现多路信号再定时的方法及装置,以解决现有技术中存在实现再定时的成本高且资源浪费严重的技术问题。 [0009] The object of the present invention to provide a method and apparatus for multi-channel signal re-timing of implementation to address the high cost of the prior art to achieve retiming and a waste of resources technical problems.

[0010] 为解决上述问题,本发明公开了一种实现多路信号再定时的方法,包括:[0011] (1)锁存每一路的数据,并产生每一路的写地址和公共的读地址; [0010] To solve the above problems, the present invention discloses a multi-channel signal retiming, comprising: [0011] (1) each way latched data, and generates a write address of each road and public read address ;

[0012] (2)由系统时钟产生若干时隙,所述时隙分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙; [0012] (2) The number of slots generated by the system clock, the time slot is divided into time slots for each channel write data written into the RAM of serial and parallel all the way data is read out of the read time slot;

[0013] (3)在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中; [0013] (3) in each of the write-time slot arrives, the write time slot corresponding to the way data is written to latch RAM (random access memory);

[0014] (4)在读时隙到来时,将所有路的数据并行读出。 [0014] (4) When reading slot arrives, the data read out in parallel all the way.

[0015] 步骤⑴之前还包括: [0015] step further comprises before ⑴:

[0016] 将所述系统时钟的频率设置为大于MX低速信号频率X (路数+1),M为RAM读数据、改写数据、写入数据所需周期数之和; [0016] The system clock frequency is set to be greater than MX low frequency signal X (large ones +1), M is a read data RAM, rewritable data, write data and the desired number of cycles;

[0017] 将RAM的宽度设置为N个低速信号的路数。 [0017] The width of the RAM is set to the large ones N low-speed signals.

[0018] 步骤(3)将所述写时隙对应路锁存的数据写入RAM中,具体为: [0018] Step (3) writing the write time slot corresponding to the road latched data in RAM, in particular:

[0019] 先读出该路写地址对应的RAM存储单元中的数据,再将该路锁存的数据置入该路对应BIT特位,并将其他路的BIT位数据原样存回,一起写入该路写地址对应的RAM存储单元中。 [0019] first reads the path corresponding to the address RAM write data storage unit, and then the way the data latched into the path corresponding to the particular bit BIT and BIT bits of data as it is stored back in the other way, to write together The road into the write address corresponding RAM storage unit.

[0020] 步骤(¾将所述写时隙对应路锁存的数据写入RAM中具体为:先将该路锁存的数据写入RAM中该路写地址对应的存储单元,然后修改该路的写地址。所述修改该路的写地址包括将写地址加一或加X,所述X为缓存器深度一半。 [0020] Step (¾ slot corresponding to the write data into RAM road latched in particular: the first writes the way the data latched in the path RAM write address corresponding to the memory cell, and then modify the way The write address. The modification of the path of the write address includes the write address plus one or plus X, wherein X is half the depth buffer.

[0021] 步骤(4)具体为:在读时隙到来时,读取读地址对应的存储单元的N个数据,然后修改所述读地址,所述N为信号路数,所述修改读地址包括将读地址加一。 [0021] Step (4) In particular: When reading slot arrives, read the N data read address corresponding to the memory cell, and then modifying the read address, the N signal large ones, including the modified read address The read address plus one.

[0022] 本发明还公开了一种实现多路信号再定时的装置,包括:包含RAM(随机存储器) 的可编程逻辑器件和高频时钟源,其中: [0022] The present invention also discloses a multi-channel signal re-timing apparatus, comprising: comprising RAM (Random Access Memory) device and a programmable logic high frequency clock source, wherein:

[0023] 高频时钟源:连接可编程逻辑器件,用以给RAM提供系统时钟; [0023] The high-frequency clock source: Connecting the programmable logic device to provide the system clock to the RAM;

[0024] 可编程逻辑器件:接收每一路输入信号及每一路对应的输入时钟和系统时钟,用以在每个系统时钟周期内将每路数据串行写入RAM,以及每路数据在统一的时钟控制下并行输出。 [0024] The programmable logic device of: receiving an input signal for each channel and each channel corresponding to the input clock and the system clock for each system clock cycle per channel serial data written to RAM, and each channel data in a unified clocked parallel output.

[0025] 所述RAM的宽度等于低速信号路数,所述深度可根据系统允许最大、最小缓存时间选取,所述RAM的深度为10MBIT、768BIT、512BIT和256BIT中的其中之一。 [0025] RAM is equal to the width of the low-speed signal large ones, according to the depth of the system allows the maximum and minimum cache time selection, the depth of the RAM is 10MBIT, one 768BIT, 512BIT and 256BIT in.

[0026] 所述可编程逻辑器件进一步包括:RAM、时隙分配单元、锁存单元和控制子单元,其中: [0026] The programmable logic device further comprising: RAM, slot allocation unit, and a control sub-unit latch unit, wherein:

[0027] 时隙分配单元:由系统时钟产生若干时隙,所述时隙又分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙,并且每个写时钟和读时钟都会触发时隙分配; Have a number of time slots when the system clock, the time slot is divided into time slots for reading and writing data to each channel RAM and a serial write data in parallel all the way to read out: [0027] slot allocating unit gap, and each write clock and read clock will trigger slot allocation;

[0028] 锁存单元:锁存每一路的数据; [0028] The latch unit: data latches each way;

[0029] 控制子单元:在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中;在读时隙到来时,所有路的数据并行读出。 [0029] The control sub-unit: each write time slot arrives, the write time slot corresponding to the way data is written to latch RAM (random access memory); when reading slot arrives, the data read out in parallel all the way .

[0030] 与现有技术相比,本发明具有以下优点: [0030] Compared with the prior art, the invention has the following advantages:

[0031] 首先,本发明采用时分电路的原理在一个系统时钟周期内完成串行写入所有路的数据并且并行读出所有路的数据,只用一个时钟资源即可以实现多路数据同步处理的功能。 [0031] First, the present invention uses the principle of division circuit in one system clock cycle all the way serial write data and parallel data read out all the way, and only one clock resources which can achieve multi-channel data synchronization process function. [0032] 其次,本发明只需占用一个RAM资源即可完成多路信号处理,由此避免采用资源数多的可编程逻辑器件,进而降低成本,同时,也避免了大量存储空间的浪费,即提高了资源的利用率; [0032] Next, the present invention only occupies a RAM resources to complete the multi-channel signal processing, thus avoiding the use of resources in a few more of programmable logic devices, thus reducing costs, while also avoiding a lot of wasted storage space, namely improve the utilization of resources;

[0033] 其次,本发明采用每一路都有一个单独的存储地址,所有路共用一个读地址(从而保证所有路信号同步输出),在某路信号发生读写冲突时,可以采用读地址不变,该写地址发生跳变的设计,由此保证任何一路的滑码不会影响到其它路。 [0033] Next, the present invention uses each channel has a single memory address, all the way to share a read addresses (to ensure that all road signal synchronization output) signals occur when a write conflict, can be used to read the same address The write address transitions of design, thereby ensuring that any slips along the way will not affect the other way.

附图说明 Brief Description

[0034] 图1为一SDH系统的结构示意图; [0034] Figure 1 is a schematic view of the structure of SDH system;

[0035] 图2为实现多路信号再定时方法的基本原理图; [0035] FIG. 2 is a multi-channel signal retiming method basic schematic;

[0036] 图3为Block RAM的存储原理图; [0036] FIG. 3 is a schematic diagram of Block RAM memory;

[0037] 图4为一种实现多路信号再定时的装置的结构示意图; [0037] FIG. 4 is a multiplexed signal retiming means implemented structural diagram;

[0038] 图5为本发明实现多路信号再定时的流程图; [0038] FIG. 5 is a flowchart invention multiplex signal re-timing of realization;

[0039] 图6为本实施例所采用的RAM的存储原理图。 [0039] FIG. 6 is a schematic diagram showing the principle of RAM memory used in the implementation.

具体实施方式 DETAILED DESCRIPTION

[0040] 现有技术中,实现多路信号再定时的方法存在成本高且资源浪费严重的技术问题。 [0040] In the prior art, multi-channel signals and then there is a high cost and waste of resources serious technical problems timing method. 为此,本发明的申请人经过长期的研究发现,可以利用时分电路的原理来实现多路信号再定时功能。 To this end, the applicant of the present invention after long-term study found that using time division circuit operation can be realized multi-channel signal retiming. 其核心在于:利用一个高速时钟源产生一个高频率(其频率高于MX信号频率X (路数+1),M为RAM读数据、改写数据、写入数据所需周期数之和;信号频率为需要定时的低速信号的信号频率)的时钟信号作为系统时钟,由系统时钟产生若干时隙,每个时隙包含若干个系统时钟周期,在不同的时隙内将预先采样到的每一路低速信号数据(一个比特)分别存入RAM中,并在某一时隙将所有路的数据(每路的一个比特)并行读出,由此实现了各路同步处理的功能。 Its core is: the use of a high-speed clock source to generate a high-frequency (the frequency is higher than the MX signal frequency X (large ones +1), M is RAM read data, overwrite the data, the number of write cycles and data required; the signal frequency need timing signal frequency low-speed signal) of the clock signal as the system clock, the system clock is generated by a number of time slots, each containing a number of system clock cycles, in different time slots previously sampled every low-speed signal data (one bit) are stored in RAM, and at a certain time slot data all the way (one bit per channel) is read out in parallel, thereby realizing the functions of the brightest synchronization process. 在本发明中,可以将RAM的宽度设置为N,即低速信号的路数, 这样,RAM的每一行中保存的是N个低速信号每个周期内写入的数据(一个比特),而RAM 的每一列则为某路低速信号顺序写入的的信号序列;读出RAM中一行的数据即为并行读出N路低速信号的一比特数据,从而实现了多路异步信号的同步处理。 In the present invention, it is possible to set the width RAM N, namely low-speed signal large ones, so that each row is stored in the RAM in the N low-speed signals for each cycle for writing data (a bit), and RAM the signal sequence for each column was a low-speed signal sequential writes; and reads a line of data RAM is read out in parallel N-way low-speed signal one-bit data, enabling synchronous processing multiple asynchronous signals.

[0041] 以下结合附图,具体说明本发明。 [0041] The following accompanying drawings, the present invention is specifically described.

[0042] 请参阅图4,其为一种实现多路信号再定时的装置的结构示意图。 [0042] Refer to Figure 4, a schematic diagram of the structure of a multi-channel signal to achieve the re-timing device. 包括:包含RAM(随机存储器)13的可编程逻辑器件11和高频时钟源12,其中: Comprising: containing RAM (Random Access Memory) 13, programmable logic device 11 and the high frequency clock source 12, wherein:

[0043] 高频时钟源12 :连接可编程逻辑器件11,用以给RAM13提供系统时钟。 [0043] high-frequency clock source 12: Connecting the programmable logic device 11 to provide the system clock to RAM13. 高频时钟源12可以为一晶体振荡器,也可以是其他能够产生满足要求的时钟信号产生器。 High frequency clock source 12 may be a crystal oscillator, it may be capable of producing other meets the requirements of a clock signal generator.

[0044] 可编程逻辑器件11 :接收每一路输入信号及每一路对应的输入时钟和系统时钟, 用以在每个系统时钟周期内将每路数据串行写入RAM,以及每路数据在统一的时钟控制下并行输出。 [0044] Programmable Logic Devices 11: receiving each input signal and corresponding input clock for each channel and the system clock for each system clock cycle per channel serial data written to RAM, and each channel data in the consolidated under clock control parallel output.

[0045] 还是请参阅图3,其为RAM的原理示意图。 [0045] or refer to Figure 3, a schematic diagram of the principle of the RAM. 时隙分配的数量要大于或等于路数加一,RAM宽度等于路数即可。 The number of slots allocated is greater than or equal to large ones plus one, RAM width equal to large ones can.

[0046] 所述可编程逻辑器件可以采用FPGA、CPLD等逻辑器件。 [0046] The programmable logic device can use FPGA, CPLD and other logic devices. 这些可编程逻辑器件进一步包括:RAM(若是采用CPLD,则需要片外存储器,可以是FIFO或其它缓存器,因为CPLD内部没有RAM)、时隙分配单元、锁存单元和控制子单元,其中: These programmable logic device further comprises: RAM (if using CPLD, you need to off-chip memory, can be FIFO or other buffer, because no internal CPLD RAM), slot allocation unit, the latch unit and a control sub-unit, wherein:

[0047] 时隙分配单元:用于将系统时钟产生若干时隙,所述时隙包含将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙,其中读时隙只有一个。 [0047] slot allocating unit: for the system clock to produce a number of slots, the slots comprising each channel serial data written into the RAM write and read time slots slot all the way in the parallel data readout, which read only one time slot. 比如,需要进行再定时的信号路的总路数为8,则可以产生9个时隙:8个写时隙和1个读时隙。 For example, the need for re-timing signal path total of 8 large ones, can produce nine slots: eight write time slots and a read time slot. 本发明采用的时隙分配是动态的,由于各路信号来的先后顺序不确定,哪路先来就先给哪路分配时隙,读时隙最后分配。 Slot assignment of the present invention uses a dynamic, due to the uncertain signals from various quarters to the order, which will give way first which way to allocate time slots, read the final distribution of slots.

[0048] 在本发明中,当采样到每个信号时钟沿时,将数据锁存,同时时隙分配单元就为该路分配一写时隙。 [0048] In the present invention, when a signal is sampled every clock edge, the data latches, while slot allocation unit allocates a write time slot for the road. 当有多路信号时钟沿同时来临,可按预定的优先级依次分配。 When there are multiple clock signals coming along at the same time, according to a predetermined priority order allocation.

[0049] 锁存单元:锁存每一路的数据。 [0049] latch unit: data latches each way. 根据每一路的输入时钟信号锁存该路的数据(一个比特)。 According to the input clock signal for each latch data path of the road (a bit). 锁存单元可以采用寄存器。 Latch unit can register.

[0050] 控制子单元:根据时隙分配单元确定的时隙,在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中;在读时隙到来时,将所有路的数据并行读出。 [0050] control sub-unit: according to time slots allocation unit determined in writing each time slot arrives, the write time slot corresponding to the way data is written to latch RAM (random access memory); reading slot arrives, the data read out in parallel all the way.

[0051] 基于上述的装置,具体说明本发明的实现多路信号再定时的方法。 [0051] Based on the above-described apparatus, multi-channel specifying signal retiming method of the present invention. 请参阅图5,其为本发明实现多路信号再定时的流程图。 Refer to Figure 5, a flowchart of multi-channel signal retiming the present invention achieves its. 它包括: Which comprises:

[0052] SllO :锁存每一路的数据,并产生每一路的写地址和公共的读地址; [0052] SllO: latched data each way, and generates a write address of each road and public read address;

[0053] S120:由系统时钟产生若干时隙,所述时隙分为用于将每路数据串行写入RAM的写时隙及将所有路的数据并行读出的读时隙; [0053] S120: generating a plurality of slots by the system clock, the time slot is divided into time slots for each channel write data written into the RAM of serial and parallel all the way data is read out of the read time slot;

[0054] S130 :在每一写时隙到来时,将所述写时隙对应路锁存的数据写入RAM(随机存储器)中; [0054] S130: (random access memory) in each of the write-time slot arrives, the write time slot corresponding to the way data is written to the latch of RAM;

[0055] S140 :在读时隙到来时,将所有路的数据并行读出 [0055] S140: When reading slot arrives, the data read out in parallel all the way

[0056] 在上述方法中,每一路输入信号在寄存器中锁存由系统时钟将每路锁存的一比特数据写入RAM中,并且将所有路的数据并行从RAM中读出,实现各路同步的功能。 [0056] In the above method, each input signal is latched in the register by the system clock to a bit of data per channel latched write RAM, and the data is read out in parallel all the way from the RAM to achieve the brightest synchronization function.

[0057] 以下是例子来具体说明多路信号再定时的流程。 [0057] The following is a specific example to illustrate the multi-channel signal retiming processes.

[0058] 需要进行再定时的信号路的总路数为8,其路数编号分别为1、2、3. . . 8,系统产生9个时隙,并且将序号为1-8的时隙分配给写时隙分别对应1-8路输入信号,序号为9的时隙为读时隙,系统时钟检测到各时钟沿变化时动态分配相应时隙序号。 [0058] The need for re-timing signal path total of 8 large ones, the large ones numbered 1, 2,... 8, the system generates nine slots, and the number of time slots 1-8 Write-time slots allocated to the corresponding input signals 1-8, No. 9 of dynamically allocated time slots corresponding slot number reading slot when the system clock detects changes in each clock edge.

[0059] 在本实施中所采用RAM的宽度为Sbit (请参阅图7)。 [0059] In this embodiment, the width of RAM used Sbit (see Figure 7). 每一列是一路的信号数据。 Each column is a way of signal data. 第一列是第一路数据,第二列是第二路数据...以此类推。 The first column is the first road data, the second column is the second road data ... and so on.

[0060] 一个写时隙到来时,需要将该时隙对应路锁存的数据写入RAM中。 [0060] a write time slot arrives, the time slot corresponding to the required road latched data is written to RAM.

[0061] 当写时隙发生变化时,只需将该路锁存的数据写入该路写地址对应的RAM存储单元中。 [0061] When the write time slot changes, just write the way the way the data latched write address corresponding RAM storage unit. 在每路信号时钟沿变化时修改该路写地址:通常是将该写地址+1。 Modify the way the write address signals at each clock edge change: it is usually the write address +1. 当该写地址接近或远离读地址时可以将该写地址重新设置新地址。 You can re-set the new address to write address when the write address close to or away from the read address.

[0062] 当进行写操作时,可以采用以下步骤,将该写时隙对应路锁存的数据写入RAM中: [0062] When a write operation, you can use the following procedure, the write time slot corresponding to the way data is written to the RAM latch:

[0063] 先读出RAM中该路写地址对应的数据,再将所述数据存入RAM中该路写地址对应的存储单元中的相应BIT位。 [0063] RAM in the first read data corresponding to the write address path, then the data stored in the RAM in the path memory cell corresponding to the write address corresponding BIT bits. 当该路信号时钟沿变化时修改该路的写地址:通常是将该写地址+1。 Modify the road when the road changes along the write address signal clock: usually the write address +1. 当该写地址接近或远离读地址时,可以将该写地址重新设置新地址。 When the write address close to or away from the read address, you can reset the write address new address. 需要指出的是:在一写时隙过程中,正在将该路数据写入RAM某一存储地址中相应BIT位时,RAM中其他路数的比特数据应该保持不变,也就是说,每个时隙只修改该时隙对应路信号的数据。 It should be noted: in the course of a write time slot, is the way data is written to a memory address in RAM when the corresponding BIT bit, RAM bit data in the other large ones should remain unchanged, that is, each modify only the time slot corresponding to the time slot data path signals.

[0064] 在读时隙到来时,读取读地址对应存储单元开始的8个比特数据,在读时钟沿发生变化时修改读地址,通常是将该读地址+1。 [0064] When reading slot arrives, read the read address corresponding to 8-bit data memory unit starts, modify the read address in the read clock edge change, usually the read address +1.

[0065] 每一路的存储写地址、读地址可以存储在可编程逻辑器件的寄存器中。 [0065] each way of storing the write address, read address may be stored in a programmable logic device registers.

[0066] 对整个可编程逻辑器件来说,读写是同时进行的,RAM的读写地址有一个起始距离,通常为RAM深度的一半。 [0066] the entire programmable logic device, the reading and writing are performed simultaneously, RAM read and write addresses having a starting distance, usually half the depth of the RAM. 由于写时钟与读时钟不同时钟源,频率上也有抖动,所以随着时间不断增长,读写地址或是会越来越近,或是会越来越远,直至达到两者距离小到零或是距离大到RAM深度的大小,此时系统会强制把读写置新值,以防止地址冲突,于是就产生了滑码。 Since write clock and read clock different clock source, the frequency jitter, so grow over time, or will be getting closer to read and write addresses, or will it farther and farther, until it reaches the small distance between the two to zero or depth is the distance from large RAM size, then the system will be forced to write the new value is set to prevent address conflicts, thus a slide codes. 为了减少单位时间内滑码次数,或是增大滑码间隔时间可以加大RAM深度,但是RAM 深度变大以后会导致滞后时间增大。 In order to reduce the number of slips per unit of time, or increase the slips interval can increase the RAM depth, but will lead to increased latency RAM larger depth later. 既要保证滑码间隔的时间不能太小,又要保证滞后时间不能太大,因而RAM深度的选择就是滑码时间与延迟矛盾的一个折中。 Necessary to ensure that the time interval of the slide code is not too small, but also to ensure the lag time can not be too large, and thus choose RAM slips depth is a compromise delay time and contradictory. 按照国家标准,El 信号再定时的存储时间至少要125us+18us (其中,125us是存储时间,ISus是滞后时间), 可根据具体的设计做出选择。 According to the national standard, El signal retiming storage time should be at least 125us + 18us (which, 125us storage time, ISus lag time), you can make a choice depending on the design. 由于国家标准很宽泛,只要存储时间大于125us,滞后时间大于18us就可以。 Since national standards are broad, long storage time is longer than 125us, the lag time can be more than 18us. 也就是说存储深度大于256BIT,即El信号的一帧,就可以;由于我们设计时采取读写地址距离为深度一半,所以滞后BIT最少为128BIT,即滞后时间最少是62. 5us。 That memory depth is greater than 256BIT, namely El signal of a frame, you can; As a result of the design of read and write address from the depth of our half, so lag BIT least 128BIT, namely the lag period is at least 62. 5us. 因此,该设计的这两个指标都是符合了国家标准的。 Therefore, the design of these two indicators are in line with national standards. 在这种条件下,发明人的设计提供了1024bit, 768bit,512bit,256bit四种深度选择,用户可以通过寄存器自行选择。 Under these conditions, the inventors design provides 1024bit, 768bit, 512bit, 256bit four depth options, the user can choose via register. 根据经验, 通常而言,深度不大于2048bit。 According to experience, generally, the depth of not more than 2048bit. 由于每路都有一个单独的写地址,在强制拉开读写地址距离的时候,采用写地址更新,而读地址不变的设计,可保证任何一路的滑码不会影响到其他路数据。 Since each channel has a separate write address, read address distance forced opened when the write-address updates and the read address the same design, all the way to ensure that any slips will not affect other road data.

[0067] 对于整个再定时系统而言,相对以前的设计,只使用了一个RAM,而传输路数没有减少。 [0067] For the entire re-timing system, the relative previous design, using only a RAM, and no reduction in the transmission of large ones. 这样节省了FPGA资源,可以使用小容量芯片代替大容量芯片,从而降低了系统成本。 This saves FPGA resources, you can use a small-capacity chip instead of a large capacity chip, thereby reducing system cost.

[0068] 以上公开仅为本发明的几个具体实施例,并本发明并非局限于此,任何本领域的技术人员能思之的变化都应落在本发明的保护范围内。 [0068] disclosed above is only a few specific embodiments of the present invention, and the invention is not limited to, any person skilled in the art can think of changes should fall within the scope of the present invention.

Citations de brevets
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Classifications
Classification internationaleH03M9/00, H04J3/16
Événements juridiques
DateCodeÉvénementDescription
4 oct. 2006C06Publication
6 déc. 2006C10Request of examination as to substance
14 sept. 2011C14Granted