CN1841978B - Method and apparatus for realizing multipath signal re-timing - Google Patents
Method and apparatus for realizing multipath signal re-timing Download PDFInfo
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- CN1841978B CN1841978B CN2005100630223A CN200510063022A CN1841978B CN 1841978 B CN1841978 B CN 1841978B CN 2005100630223 A CN2005100630223 A CN 2005100630223A CN 200510063022 A CN200510063022 A CN 200510063022A CN 1841978 B CN1841978 B CN 1841978B
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Abstract
The invention discloses a method for achieving multi-path signal re-timing, especially to the re-timing of multi-path E1, T1 or other low speed signal. It uses a high speed clock source to generate a high frequency clock signal as system clock; the system clock generates a plurality of time slots; each time slot comprises a plurality of system clock periods; it separately stores the sampled low speed signal data in RAM and reads the data of all the paths of a time slot, which achieves each path synchronic processing.
Description
Technical field
The present invention relates to the communications field, particularly is the implementation method of multichannel synchronizing signal with multi-path asynchronous signal processing.
Background technology
SDH system (synchronous digital communications transmission system) is widely used in the important transmission systems such as Modern High-Speed telecommunications network, high-speed Internet, and to optical fiber, microwave and Evolution of Satellite Communication Techniques all are of great importance.In the SDH system, will be when data are adaptive through mapping or pointer adjustment, however in this adjustment process, can introduce the shake and the drift of data, for fear of the influence that synchronization timing is brought when reducing this situation and take place, need carry out signal timing and handle.
See also Fig. 1, it is the structural representation of a SDH system.Transmit in the stratum reticulare in this locality, the SDH ring adopts multichannel E1, T1 or other low speed signal to connect ADM (divide to insert and take device) and CPE (client device) respectively mostly, and CPE is often with the data signal extraction synchronization timing of importing, the influence that the shake that causes for fear of the adjustment of SDH pointer brings timing, need carry out again regularly, so that obtain high-quality synchronizing signal.
At present, realize multiple signals timing function again by cache way usually,, be widely used in caching process because the shared resource of RAM is few.Consult Fig. 2, for realizing the multiple signals basic principle figure of timing method again.Every road signal is adopted a dual port RAM, data are write, data are read at another mouthful at a mouth.The clock that writes adopts the clock that extracts from input signal, readout clock adopts timer clock again, and writing and read all of data carried out on the clock edge.Each road signal all is equipped with a RAM, realizes the timing function again of multiple signals by the quantity that increases RAM.And, the Block RAM (piece memory cell) in the general direct employing fpga chip of RAM.
There is following defective in the above-mentioned realization multiple signals method of timing again:
Clock resource in the one, sheet is limited, for most of programming devices, clock can only use in the system resource allowed band, when the signal way increases, if directly use the signal clock deal with data, tend to finish because of the clock resource causes design inadequately.
Second: every kind of quantity such as the Block RAM of the programmable chip of FPGA is limited.Along with increasing of needs signal way amount regularly, need the sheet number of Block RAM just to increase accordingly.Yet, the resource that has along with FPGA many more (such as, the Block RAM sheet number that has increases), the price of fpga chip is just high more.That is, along with networks development, need the signal way amount of timing again to increase, this just needs to adopt the high FPGA of price, causes defect of high cost thus.
Three: one Block RAM only stores one road signal, and every road signal is the serial input, and the bit wide of signal has only one, so a slice BlockRAM has only used the width of 1bit (position).See also Fig. 3, it is the storage principle figure of Block RAM.The memory cell of each Block RAM all is made up of the width of determining figure place and the degree of depth of definite figure place.Obviously, a slice BlockRAM has only used the width of 1bit (position), causes a large amount of wastings of resources.And multiple signals need and the corresponding BlockRAM sheet of way number regularly the time again, cause the bigger wasting of resources thus.
Summary of the invention
The object of the present invention is to provide a kind of multiple signals regularly method and device again of realizing, with solve exist in the prior art realization more regularly the cost height and the technical problem of serious waste of resources.
For addressing the above problem, the invention discloses a kind of multiple signals method of timing again that realizes, comprising:
(1) latchs the data on each road, and produce the write address and the public address of reading on each road;
(2) produce some time slots by system clock, described time slot is divided into and is used for every circuit-switched data serial is write writing time slot and reading time slot with what the data parallel on all roads was read of RAM;
(3) when each writes the time slot arrival, the described corresponding road of the time slot latched data of writing is write among the RAM (random asccess memory);
(4) when reading the time slot arrival, the data parallel on all roads is read.
Step (1) also comprises before:
With the frequency configuration of described system clock is greater than M * low speed signal frequency * (way+1), and M is RAM read data, rewrite data, write the required periodicity sum of data;
The width of RAM is set to the way of N low speed signal.
Step (3) writes the described corresponding road of the time slot latched data of writing among the RAM, is specially:
Read the data in the ram memory cell of this road write address correspondence earlier, again this road latched data is inserted the special position of corresponding BIT, this road, and the BIT bit data former state on other roads is deposited back, write together in the ram memory cell of this road write address correspondence.
Step (3) writes the described corresponding road of the time slot latched data of writing among the RAM and is specially: earlier this road latched data is write the memory cell of this road write address correspondence among the RAM, revise the write address on this road then.The write address on this road of described modification comprises write address added one or add X, described X be the buffer degree of depth half.
Step (4) is specially: when reading the time slot arrival, read N data of the memory cell of address correspondence, revise the described address of reading then, described N is the signal way, and described modification is read the address and comprised and will read cyclic address change.
The invention also discloses a kind of multiple signals device of timing again of realizing, comprising: comprise programmable logic device and the high frequency clock source of RAM (random asccess memory), wherein:
High frequency clock source: connect programmable logic device, in order to provide system clock to RAM;
Programmable logic device: receive the input clock and the system clock of each road input signal and each road correspondence, in order in each system clock cycle every circuit-switched data serial being write RAM, and every circuit-switched data is under unified clock control and line output.
The width of described RAM equals the low speed signal way, and the described degree of depth can allow maximum, minimal cache time to choose according to system, and the degree of depth of described RAM is one of them among 1024BIT, 768BIT, 512BIT and the 256BIT.
Described programmable logic device further comprises: RAM, time slot allocating unit, latch units and control sub unit, wherein:
Time slot allocating unit: produce some time slots by system clock, described time slot is divided into again and is used for every circuit-switched data serial is write writing time slot and reading time slot with what the data parallel on all roads was read of RAM, and each is write clock and read clock and all can trigger time slot allocation;
Latch units: the data that latch each road;
Control sub unit: when each writes the time slot arrival, the described corresponding road of the time slot latched data of writing is write among the RAM (random asccess memory); When reading the time slot arrival, the data parallel on all roads is read.
Compared with prior art, the present invention has the following advantages:
At first, the present invention adopts the principle of time division circuit to finish serial in a system clock cycle and writes the data on all roads and the data on all roads of parallel read-out, only promptly can realize the function of multichannel data Synchronous Processing with a clock resource.
Secondly, the present invention only need take a RAM resource can finish the multiple signals processing, avoids adopting number of resources programmable logic device how thus, and then reduces cost, and simultaneously, has also avoided the waste of a large amount of memory spaces, has promptly improved the utilance of resource;
Secondly, the present invention adopts each road that an independent memory address is arranged, address (thereby guaranteeing all road signal Synchronization outputs) is read on shared one of all roads, when certain road signal generation read/write conflict, can adopt that to read the address constant, the design of this write address generation saltus step guarantees that thus any one tunnel slip can not have influence on other road.
Description of drawings
Fig. 1 is the structural representation of a SDH system;
Fig. 2 is for realizing the multiple signals basic principle figure of timing method again;
Fig. 3 is the storage principle figure of Block RAM;
Fig. 4 is a kind of multiple signals structural representation of the device of timing again of realizing;
Fig. 5 realizes the multiple signals flow chart of timing again for the present invention;
Fig. 6 is the storage principle figure of the RAM that present embodiment adopted.
Embodiment
In the prior art, realize multiple signals more regularly method have the technical problem of cost height and serious waste of resources.For this reason, applicant of the present invention finds through long term studies, can utilize the principle of time division circuit to realize multiple signals timing function again.Its core is: (its frequency is higher than M * signal frequency * (way+1), and M is RAM read data, rewrite data, write the required periodicity sum of data to utilize high-speed clock source to produce a high-frequency; Signal frequency is for needing the signal frequency of low speed signal regularly) clock signal as system clock, produce some time slots by system clock, each time slot comprises several system clock cycles, each road low speed signal data (bit) that will sample in advance in different time slots deposit among the RAM respectively, and, realized the function of each road Synchronous Processing thus at data (bit on the every road) parallel read-out of a certain time slot with all roads.In the present invention, width that can RAM is set to N, i.e. the way of low speed signal, like this, what preserve in each row of RAM is the data (bit) that N low speed signal write in each cycle, each of RAM be listed as then write in proper order for certain road low speed signal burst; Read that the data of delegation are a Bit data of parallel read-out N road low speed signal among the RAM, thereby realized the Synchronous Processing of multi-path asynchronous signal.
Below in conjunction with accompanying drawing, specify the present invention.
See also Fig. 4, it is a kind of multiple signals structural representation of the device of timing again of realizing.Comprise: comprise programmable logic device 11 and the high frequency clock source 12 of RAM (random asccess memory) 13, wherein:
High frequency clock source 12: connect programmable logic device 11, in order to provide system clock to RAM13.High frequency clock source 12 can be a crystal oscillator, also can be that other can produce the clock signal generator that meets the demands.
Programmable logic device 11: receive the input clock and the system clock of each road input signal and each road correspondence, in order in each system clock cycle every circuit-switched data serial being write RAM, and every circuit-switched data is under unified clock control and line output.
Still see also Fig. 3, it is the principle schematic of RAM.The quantity of time slot allocation is greater than or equals way and adds one, and the RAM width equals way and gets final product.
Described programmable logic device can adopt logical devices such as FPGA, CPLD.These programmable logic devices further comprise: RAM (if adopt CPLD, then needing chip external memory, can be FIFO or other buffer, because CPLD inside does not have RAM), time slot allocating unit, latch units and control sub unit, wherein:
Time slot allocating unit: be used for system clock is produced some time slots, described time slot comprises every circuit-switched data serial is write writing time slot and reading time slot with what the data parallel on all roads was read of RAM, wherein reads time slot and has only one.Such as, the total way that need carry out again signal road regularly is 8, then can produce 9 time slots: write time slot and 1 for 8 and read time slot.The time slot allocation that the present invention adopts is dynamic, because the sequencing that each road signal comes is uncertain, which road distributes time slot just for earlier first which road, reads time slot and distributes at last.
In the present invention, when sample each signal clock along the time, with data latching, simultaneously time slot allocating unit is just write time slot for this road distribution one., can distribute successively along arriving simultaneously as the multiple signals clock by preset priority.
Latch units: the data that latch each road.Latch the data (bit) on this road according to the input clock signal on each road.Latch units can adopt register.
Control sub unit: the time slot according to time slot allocating unit is determined when each writes the time slot arrival, writes the described corresponding road of the time slot latched data of writing among the RAM (random asccess memory); When reading the time slot arrival, the data parallel on all roads is read.
Based on above-mentioned device, specify the realization multiple signals of the present invention method of timing again.See also Fig. 5, it realizes the multiple signals flow chart of timing again for the present invention.It comprises:
S110: latch the data on each road, and produce the write address and the public address of reading on each road;
S120: produce some time slots by system clock, described time slot is divided into and is used for every circuit-switched data serial is write writing time slot and reading time slot with what the data parallel on all roads was read of RAM;
S130: when each writes the time slot arrival, the described corresponding road of the time slot latched data of writing is write among the RAM (random asccess memory);
S140: when reading the time slot arrival, the data parallel on all roads is read
In said method, each road input signal latchs a Bit data that every road is latched by system clock and writes among the RAM in register, and the data parallel on all roads is read from RAM, realizes the function that each road is synchronous.
Below be that example specifies the multiple signals flow process of timing again.
Need carrying out again, total way on the signal road of timing is 8, its way numbering is respectively 1,2,3...8, system produces 9 time slots, and with sequence number is that the time slot allocation of 1-8 is given and to be write time slot corresponding 1-8 road input signal respectively, sequence number is 9 time slot for reading time slot, and system clock detects each clock dynamic assignment corresponding time slot sequence number when changing.
The width of the RAM that adopts is 8bit (seeing also Fig. 7) in this enforcement.Each row is signal datas of one tunnel.First row are first via data, and secondary series is second circuit-switched data ... by that analogy.
One when writing time slot and arriving, need the corresponding road of this time slot latched data is write among the RAM.
When writing time slot and change, only need this road latched data is write in the ram memory cell of this road write address correspondence.Revise this road write address at every road signal clock when changing: normally with this write address+1.When this write address near or this write address can be reset new address when reading the address.
When carrying out write operation, can adopt following steps, this is write the corresponding road of time slot latched data write among the RAM:
Read the data of this road write address correspondence among the RAM earlier, more described data are deposited in the corresponding BIT position in the memory cell of this road write address correspondence among the RAM.When this road signal clock is revised the write address on this road when changing: normally with this write address+1.When this write address near or when reading the address, this write address can be reset new address.It is to be noted: write in the time slot process one, when this circuit-switched data being write in a certain memory address of RAM corresponding BIT position, the Bit data of other ways should remain unchanged among the RAM, that is to say, each time slot is only revised the data of the corresponding road of this time slot signal.
When reading time slot and arrive, read 8 Bit datas that corresponding stored unit, address begins, revise when changing and read the address reading clock, normally this is read address+1.
The storage write address on each road, read in the register that the address can be stored in programmable logic device.
Concerning whole programmable logic device, read-write is carried out simultaneously, and the read/write address of RAM has an initial distance, is generally half of the RAM degree of depth.Owing to write clock and read clock different clocks source, shake is also arranged on the frequency, so along with the time constantly increases, read/write address or can be more and more nearer, or can be more and more far away, little to zero or apart from big size to the RAM degree of depth until reaching both distances, this moment, system can force new value is put in read-write, to prevent address conflict, so just produced slip.In order to reduce slip number of times in the unit interval, or increasing slip can strengthen the RAM degree of depth blanking time, but the RAM degree of depth becomes and can cause increase lag time after big.Should guarantee that the slip interlude can not be too little, guarantee that again lag time can not be too big, thereby the selection of the RAM degree of depth is exactly a slip time and a compromise that postpones contradiction.According to national standard, the E1 signal is wanted 125us+18us (wherein, 125us is memory time, and 18us is lag time) again the memory time of timing at least, can make a choice according to concrete design.Because national standard is very wide in range, need only memory time greater than 125us, just can greater than 18us lag time.That is to say storage depth greater than 256BIT, promptly a frame of E1 signal just can; Since we take when designing the read/write address distance for the degree of depth half, so hysteresis BIT minimum be 128BIT, promptly lag time minimum be 62.5us.Therefore, two indexs of this of this design have all met national standard.Under this condition, inventor's design provides 1024bit, 768bit, and 512bit, four kinds of degree of depth of 256bit are selected, and the user can select voluntarily by register.Rule of thumb, usually, the degree of depth is not more than 2048bit.Because all there is an independent write address on every road, when forcing to draw back the read/write address distance, adopt write address to upgrade, and read the constant design in address, can guarantee that any one tunnel slip can not have influence on other circuit-switched data.
For whole circuit re-timing system, a RAM has only been used in Yi Qian design relatively, and the transmission way does not reduce.Saved the FPGA resource like this, can use the low capacity chip to replace big capacity chip, thereby reduce system cost.
More than open only is several specific embodiment of the present invention, and the present invention is not limited thereto, any those skilled in the art can think variation all should drop in protection scope of the present invention.
Claims (8)
1. realize the multiple signals method of timing again for one kind, be applied to the timing again of multi-path low speed signal in the SDH system, it is characterized in that, comprising:
(1) latchs the data on each road, and produce the write address and the public address of reading on each road; The described public address of reading is meant: for described each road shared read the address;
(2) produce some time slots by system clock, described time slot is divided into and is used for every circuit-switched data serial is write writing time slot and reading time slot with what the data parallel on all roads was read of RAM;
(3) when each writes the time slot arrival, the described corresponding road of the time slot latched data of writing is write among the RAM (random asccess memory);
(4) when reading the time slot arrival, the data parallel on all roads is read;
Wherein, the frequency of described system clock is greater than M * low speed signal frequency * (way+1), and M is RAM read data, rewrite data, write the required periodicity sum of data; The width of RAM equals the way of low speed signal, and the degree of depth of RAM allows maximum, minimal cache time to choose according to system.
2. realization multiple signals as claimed in claim 1 are the method for timing again, it is characterized in that step (1) also comprises before:
With the frequency configuration of described system clock is greater than M * low speed signal frequency * (way+1), and M is RAM read data, rewrite data, write the required periodicity sum of data;
The width of RAM is set to the way of N low speed signal.
3. realization multiple signals as claimed in claim 1 or 2 are the method for timing again, it is characterized in that, step (3) writes the described corresponding road of the time slot latched data of writing among the RAM, is specially:
Read the data in the ram memory cell of this road write address correspondence earlier, again this road latched data is inserted the special position of corresponding BIT, this road, write in the ram memory cell of this road write address correspondence, and the BIT bit data on other roads is remained unchanged.
4. realization multiple signals as claimed in claim 1 or 2 are regularly method again, it is characterized in that, step (3) will describedly be write time slot correspondence road latched data and write among the RAM and be specially:
Earlier this road latched data is write the memory cell of this road write address correspondence among the RAM, revise the write address on this road then.
5. realization multiple signals as claimed in claim 4 are regularly method again, it is characterized in that, the write address on this road of described modification comprises write address is added one or add X, described X be the RAM degree of depth half.
6. realization multiple signals as claimed in claim 1 or 2 are the method for timing again, it is characterized in that step (4) is specially:
When reading the time slot arrival, read N data of the memory cell of address correspondence, revise the described address of reading then, described N is the signal way, described modification is read the address and is comprised and will read cyclic address change.
7. realize the multiple signals device of timing again for one kind, be applied to the timing again of multi-path low speed signal in the SDH system, it is characterized in that, comprising: time slot allocating unit, latch units and control sub unit, wherein:
Latch units: latch the data on each road, and produce the write address and the public address of reading on each road; The described public address of reading is meant: for described each road shared read the address;
Time slot allocating unit: produce some time slots by system clock, described time slot is divided into and is used for every circuit-switched data serial is write writing time slot and reading time slot with what the data parallel on all roads was read of RAM;
Control sub unit: when each writes the time slot arrival, the described corresponding road of the time slot latched data of writing is write among the RAM (random asccess memory); When reading the time slot arrival, the data parallel on all roads is read;
Wherein, the frequency of described system clock is greater than M * low speed signal frequency * (way+1), and M is RAM read data, rewrite data, write the required periodicity sum of data; The width of described RAM equals the low speed signal way, and the degree of depth of RAM allows maximum, minimal cache time to choose according to system.
8. multiple signals as claimed in claim 7 are the device of timing again, it is characterized in that the degree of depth of described RAM is one of them among 1024BIT, 768BIT, 512BIT and the 256BIT.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101136855B (en) * | 2007-04-10 | 2012-04-18 | 中兴通讯股份有限公司 | Asynchronous clock data transmission device and method |
| CN101217329B (en) * | 2008-01-17 | 2011-05-25 | 中兴通讯股份有限公司 | A branch retiming system applying PDH |
| CN102798582A (en) * | 2012-05-22 | 2012-11-28 | 山东理工大学 | Proportional photon correlator based on digital signal processor (DSP) annular buffer area |
| CN109254941B (en) * | 2017-07-13 | 2020-04-24 | 凌云光技术集团有限责任公司 | FPGA-based serial signal clock synchronization method, serial-to-parallel conversion method and device |
| CN110519667B (en) * | 2019-09-11 | 2021-08-24 | 天津光电通信技术有限公司 | Method for realizing optical signal line crossing |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183867A (en) * | 1995-05-05 | 1998-06-03 | Gpt有限公司 | Retiming arrangement for SDH data transmission system |
| US6539488B1 (en) * | 1999-11-30 | 2003-03-25 | Agere Systems Inc. | System with a plurality of media access control circuits with a shared memory for storing data and synchronizing data from a clock domain to a host clock domain |
| CN1551507A (en) * | 2003-05-09 | 2004-12-01 | �ձ�������ʽ���� | Serial-to-parallel- and parallel-to-serial converter |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183867A (en) * | 1995-05-05 | 1998-06-03 | Gpt有限公司 | Retiming arrangement for SDH data transmission system |
| US6539488B1 (en) * | 1999-11-30 | 2003-03-25 | Agere Systems Inc. | System with a plurality of media access control circuits with a shared memory for storing data and synchronizing data from a clock domain to a host clock domain |
| CN1551507A (en) * | 2003-05-09 | 2004-12-01 | �ձ�������ʽ���� | Serial-to-parallel- and parallel-to-serial converter |
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