CN1866539B - Integrated circuit element and forming method thereof - Google Patents
Integrated circuit element and forming method thereof Download PDFInfo
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- CN1866539B CN1866539B CN200410057339A CN200410057339A CN1866539B CN 1866539 B CN1866539 B CN 1866539B CN 200410057339 A CN200410057339 A CN 200410057339A CN 200410057339 A CN200410057339 A CN 200410057339A CN 1866539 B CN1866539 B CN 1866539B
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Abstract
The invention discloses an integrating circuit element and forming method, which comprises the following parts: dielectric material, metal, second energy gap semiconductor, first energy gap semiconductor, wherein the second energy gap semiconductor touches metal phase through lower energy gap, which is lower than first energy gap substrate under 1.1eV. The dielectric layer with fixing stress is deposited by metal, which supplements metal, second energy gap semiconductor and first energy gap substrate stress. The invention reduces the touching resistance, which improves the efficiency and reliability of integral circuit element.
Description
Technical field
The present invention relates to a kind of semiconductor element, particularly relate to a kind of semiconductor element that uses low gap material.
Background technology
The semiconductor element size of very lagre scale integrated circuit (VLSIC) (VLSI circuit) is more little, and (contact resistance) is important more to the influence that element efficiency caused for contact resistance.Generally speaking, when metal contacts with doped silicon, for example form when contacting with transistorized source electrode, drain region or gate electrode, it will produce Schottky barrier (Schottky barrier) in connecing face, and this Schottky barrier often causes higher contact resistance, and therefore weakens the usefulness of element.Usually, higher contact resistance can reduce the electric current of element, and has therefore limited the usefulness and the speed of element, has increased the heat of element, and has produced other bad results.
A kind of method that reduces contact resistance is the doping that increases the semiconductor region that forms contact, it typically is transistorized source electrode, drain region or gate electrode, although these zones may be doped polycrystalline silicon resistor, capacitor board or some other doped regions.Traditionally, this type of zone usually is made of the zone institute of a doped silicon, for example the silicon or the polysilicon layer of impurity (as arsenic, phosphorus, boron or analogous element).In general, the doping content that increases impurity (impurity) will influence a lot of character of element, comprising reducing contact resistance.Yet silicon has limited the solubility of impurity, therefore, and by increasing the restriction that method that alloy (dopant) concentration reduces contact resistance is subjected to the solubility of impurity in silicon.The doping level of impurity concentration also can produce appreciable impact to component properties, and its influence to contact resistance can't solve by other modes, therefore, the concentration of impurity may influence the usefulness of element, and further restricted passage increases the ability that doping impurity concentration reduces contact resistance.
The method that adopts metal silicide (silicide) to reduce contact resistance is well-known to those skilled in the art.In existing element, on the doped region that will produce contact, form metal silicified layer, and this metal silicified layer the place by will forming contact (contact) at silicon or polysilicon region is (for example usually, source electrode or drain region, gate regions, doped polycrystalline silicon layer) metal silicified layer of deposition (for example, titanium silicide, tungsten silicide, cobalt silicide) forms, also can pass through original position (in-situ) processing procedure with a deposit metal films on above-mentioned silicon or polysilicon region, and in ensuing hot fabrication steps, this metal is formed metal silicide with silicon or polysilicon reaction partly.
When size of component is more and more littler, to the requirement of usefulness when more and more higher, press for and a kind ofly can reduce structure of contact resistance and forming method thereof, particularly to grid length at 90 nanometers or following element.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of integrated circuit component and forming method thereof, make integrated circuit component when minimum size, still have very low contact resistance, the stress that compensation simultaneously causes owing to lattice mismatch, thereby the usefulness and the reliability of raising integrated circuit component.
To achieve these goals, the invention provides a kind of integrated circuit component, comprise: a substrate is made of the semiconductor with first energy gap; A gate dielectric is positioned in this substrate; A gate electrode is positioned on this gate dielectric; Source electrode and drain region are arranged in this gate dielectric substrate on two sides, and this source electrode and drain region have at least one upper section, and this upper section is made of the semiconductor with second energy gap, and this second energy gap is lower than this first energy gap; A metal level, be arranged in this source electrode and drain region at least one upper section above; One first dielectric layer is positioned at this metal level top; One second dielectric layer is positioned at this first dielectric layer top, wherein this first dielectric layer and this second dielectric layer in order to the upper section that compensates this source electrode and drain electrode and this metal level because of stress that lattice mismatch produced; An interlayer dielectric layer is positioned at this second dielectric layer top; And a conductive plugs, this conductive plugs contacts with this metal level, and is arranged in this first dielectric layer, this second dielectric layer and this interlayer dielectric layer.
According to integrated circuit component of the present invention, described first dielectric layer has an intrinsic compression stress or tensile stress.
According to integrated circuit component of the present invention, the material of described substrate comprises one or more the combination in the strained silicon on silicon, germanium, compound semiconductor, silicon-coated insulated body, the relaxed silicon-Germanium.
According to integrated circuit component of the present invention, the extension of the upper section of described source electrode and drain region is dispersed throughout this source electrode and drain region.
According to integrated circuit component of the present invention, the material of described source electrode and drain region upper section comprises silicon and germanium.
According to integrated circuit component of the present invention, the material of described source electrode and drain region upper section also comprises carbon.
According to integrated circuit component of the present invention, wherein the content of germanium is between the 10-50 atomic percent.
According to integrated circuit component of the present invention, the surface, top of described source electrode and drain region has a doping content and is higher than 2 * 10
20Cm
-3Impurity, and this impurity comprises one or more the combination in boron, phosphorus, arsenic, indium, the antimony.
According to integrated circuit component of the present invention, described metal level is a metallic compound.
According to integrated circuit component of the present invention, described metallic compound is a metal silicide.
According to integrated circuit component of the present invention, the composition of described metal silicide comprises a kind of or its combination in nitrogen, the carbon at least.
According to integrated circuit component of the present invention, described metal silicide is a transition metal silicide.
According to integrated circuit component of the present invention, described metallic compound comprises two or more transition metal.
According to integrated circuit component of the present invention, described source electrode and drain region are depressed in the described substrate.
To achieve these goals, the invention provides a kind of method that forms integrated circuit component, comprise the following steps: to form a gate dielectric on a surface of a substrate, wherein, this substrate is made of one first kenel semiconductor; On this gate dielectric, form a gate electrode; Along forming a pair of sept on this gate electrode sidewall relative with this gate dielectric; Epitaxial growth source electrode and drain region on this surface of this substrate that is positioned at these gate dielectric both sides, wherein, at least one surface, top of this source electrode and drain region is made of one second kenel semiconductor, and the semi-conductive energy gap of wherein said second kenel is lower than the semi-conductive energy gap of first kenel that forms described substrate; Metal level of formation above at least one in this source electrode and drain region; On this metal level, form one first dielectric layer; On this first dielectric layer, form one second dielectric layer; On this second dielectric layer, form an interlayer dielectric layer; In this first dielectric layer, this second dielectric layer and this interlayer dielectric layer, form an opening, wherein this first dielectric layer and this second dielectric layer in order to the top that compensates this source electrode and drain electrode surperficial and this metal level because of stress that lattice mismatch produced; And in this opening, form a conductive plugs.
Method according to formation integrated circuit component of the present invention, the method of described source electrode of epitaxial growth and drain electrode comprises the selective epitaxial flop-in method, wherein, the reacting gas of this selective epitaxial flop-in method comprises a kind of or its combination in silicon, germanium, hydrogen, chlorine, nitrogen, helium, phosphorus, boron, the arsenic.
According to the method for formation integrated circuit component of the present invention, described metal level is a metal silicide, forms by the metal silication program.
Method according to formation integrated circuit component of the present invention, the method of described formation metal level also comprises: be higher than about 300 ℃ and pressure in temperature and carry out first tempering step under less than about 10 holders, and gaseous environment comprises hydrogen, nitrogen, helium, neon, argon, xenon or its combination.
According to the method for formation integrated circuit component of the present invention, described first dielectric layer has an intrinsic tensile stress or compression stress.
Integrated circuit component provided by the invention and forming method thereof, adopt dielectric medium/metal/second energy gap semiconductor material/semiconductor-based bottom structure of first energy gap, metal level directly is not connected with substrate, but be connected with the low gap material lower than the energy gap of substrate, reduce Schottky barrier, and then reduced contact resistance.In addition, owing to adopt different deposition processs and material in not, compensated the stress that causes owing to lattice mismatch, thereby improved the usefulness and the reliability of integrated circuit component at suitable layer.
Description of drawings
Fig. 1 is the side sectional view of dielectric medium/metal/second energy gap semiconductor material/semiconductor-based bottom structure of first energy gap.
Fig. 2 a to 2g is the side sectional view of a metal-oxide semiconductor transistor component in each stage of manufacture process.
Fig. 3 is a side sectional view with metal-oxide semiconductor transistor component of composite dielectric layer.
Embodiment
The invention provides a kind of integrated circuit structure with low contact resistance, wherein, second semi-conducting material with low energy gap is arranged between a contacting metal and the substrate, and reduces this semiconductor energy gap and may reduce Schottky barrier.Fig. 1 is the side sectional view of dielectric medium/metal/second energy gap semiconductor material/semiconductor-based bottom structure of first energy gap, and Fig. 2 a to 2g utilizes structure shown in Figure 1 to form the fabrication steps of a complementary metal oxide semiconductors (CMOS) (CMOS) element.In above-mentioned each figure, identical Reference numeral represents to have identical or corresponding feature.
In Fig. 1, substrate 2 is preferably a semiconductor or insulating barrier, and goodly constitute by silicon, silicon chip for example, perhaps (as imbed oxide layer, i.e. buried oxidelayer covers one deck silicon above BOX) at insulating barrier, be insulating layer covered with silicone well-known to those skilled in the art (silicon-on-insulator, SOI) structure.In other embodiments, this substrate 2 also can be made of other semiconductors or insulating material, for example the dielectric medium (dielectric coefficient is greater than 8) of silica, nitrogen oxide (oxynitride), nitride or high-dielectric coefficient.Semiconductor layer 12 is preferably the low semi-conducting material of energy gap that has than the substrate 2 of its below.In preferred embodiment, this second energy gap layer 12 is formed in the substrate 2 by extension, and preferablely has an energy gap that is lower than 1.1eV (eV represent electron-volt), and this energy gap than the 1.12eV of silicon base 2 is low.The above-mentioned second energy gap semiconductor layer 12 is commonly used to reduce the Schottky barrier between metal and substrate, and as mentioned above, lower energy gap can be used for reducing contact resistance usually.
In certain embodiments, lattice mismatch between substrate 2 and semiconductor layer 12 (crystal lattice mismatch) may cause stress (producing compression or stretching stress according to selected material and depositional mode) on the contact-making surface between each material, this stress may spread all over semiconductor layer 12 and the usefulness and the reliability (reliability) of reduction element.To describe in detail in the back, this stress can not compensate by the follow-up layer that applies.
Fig. 1 shows that a metal level 14 is formed on the semiconductor layer 12, this metal level 14 is preferably metallic compound (metal compound) or the alloy (alloy) that contains transition metal, to describe in detail in the back, this metal level 14 also can be the metal silicide that is formed at semiconductor layer 12 surfaces.Because metal 14 directly contacts with semiconductor layer 12, when balance, charge carrier (carrier) flows a short distance and passes through contact-making surface, cause electric charge to increase on the contact-making surface both sides, thereby form a Schottky barrier, and the height of this potential barrier roughly depends on semi-conductive energy gap, and some other factor.Select one to have the semiconductor layer 12 lower, then will be lower than potential barrier when metal 14 directly contacts with substrate 2 between the Schottky barrier between metal 14 and the semiconductor 12 than the energy gap of substrate 2.
On metal 14 deposition dielectric layer 16, its thickness be preferably between 50 to
Be more preferred from substantially between 200 to
Between.Generally speaking, dielectric layer 16 has three main effects.At first, dielectric layer 16 can be used between compensation semiconductor's layer 12 and 14 on metal and semiconductor layer 12 and the substrate 2 because of the stress that lattice mismatch produced, by relaxing stress because of lattice mismatch caused, number of defects between metal 14, semiconductor layer 12 and the substrate 2 is reduced, and then improve the reliability and the usefulness of element.To describe in detail in the back, and can deposit this dielectric layer 16, and make it have remarkable stress characteristics, thereby compensation is arranged in the significant stress that the layer of its below is not comprised greater than 400MPa.
The second, dielectric layer 16 can be used as etching stopping layer (etch stop layer), for the other error that causes because of the mistake etching of the layer of follow-up formation provides permissible range, for example, the interlayer dielectric layer of follow-up formation (inter-level dielectric layer; ILD).Generally speaking, when component size was dwindled, the thickness of metal silicified layer 14 also can dwindle thereupon.For instance, one have the grid size be 0.13 micron metal oxide semiconductor device may only have thickness be 300 to
Metal silicified layer (metal level 14), and for the element of 90 nanometers, 65 nanometers or smaller szie, the thickness of metal silicified layer will be thinner thereupon, and this has increased when forming contact hole (contact window) in follow-up formation interlayer dielectric, the risk that metal silicified layer is removed.Although present etch endpoint detection technology provides the high precision precision, for the metal silicified layer here, still only has very little error permissible range.Dielectric layer 16 can be used as the etching stopping layer of its top interlayer dielectric, and therefore an extra etching permissible range excessively can be provided.Because dielectric layer 16 is positioned between interlayer dielectric 18 (as shown in Figure 2) and the metal silicified layer 14, so etching can be divided into two steps and carries out.At first, etching interlayer dielectric layer 18, and stop at dielectric layer 16.As long as because interlayer dielectric layer 18 is thicker than dielectric layer 16, therefore wanting eating thrown interlayer dielectric layer 18 and accurately stopping at dielectric layer 16 has certain difficulty, but dielectric layer 16 etched removing fully, only be etched to 16 of dielectric layers and do not have too big influence.Then, etching dielectric layer 16 and stop at metal silicified layer 14.Dielectric layer 16 (200 to
) Film Thickness Ratio interlayer dielectric layer 18 thin a lot, so eating thrown dielectric layer 16 and be stopped at thin metal silicified layer 14 than dielectric layer between eating thrown thick-layer 18 (usually greater than
) and stop at thin metal silicified layer 14 and be more prone to.
The 3rd, dielectric layer 16 can be in follow-up fabrication steps helps the stable metal silicide that is positioned at below it in order to stop pollutant, and above-mentioned pollutant may be the oxidation of the metal silicified layer that causes in the process from deposition interlayer dielectric layer 18.More detailed content sees also M.Saito and equals IEDM 99-805 " AdvancedThermally Stable Silicide S/D Electrodes for High-SpeedLogic Circuits with Large-Scale Embedded Ta
2O
5-CapacitorDRAMS " in the explanation done.
Fig. 2 a to 2g is used for illustrating one embodiment of the present of invention.Wherein, structure shown in Figure 1 will be incorporated in the processing procedure that forms metal oxide semiconductor transistor, those skilled in the art will be understood that, processing procedure disclosed herein is applicable to various elements, comprise NMOS and PMOS transistor, cmos element, doped polycrystalline silicon resistor (dopedpolysilicon resistor), integrated capacitance (integrated capacitor) and inductance (inductor), and with the contact zone of silicon block, and other application that comprised here can realize by common experiment. in the embodiment that is set forth, dielectric medium/metal/second can gap semiconductor/first energy gap substrate structure be used to source electrode and drain region with the reduction contact resistance, and this structure also is applicable to gate regions.
What show among Fig. 2 a is to have shallow channel isolation area (shallow trenchisolation; STI) 4 substrate 2.This shallow channel isolation area is preferable by etching shallow trenches in substrate 2 and fill insulant (for example silica) and form.As everyone knows, shallow channel isolation area has blocked transistor or like and has been about to the active region that forms.Substrate 2 can be bulk semiconductor crystal wafer or insulating layer covered with silicone structure, and in other embodiments, substrate 2 can also be the strained silicon on the relaxed silicon germanium layer, and it can comprise silicon, germanium, carbon, compound semiconductor (compound semiconductor) or its combination.
Also comprise a gate dielectric 6 and a gate electrode 8 among Fig. 2 a.As is known to the person skilled in the art, at first in substrate 2, form a gate dielectric, then form a gate electrode layer again, afterwards formation gate electrode 8 and gate dielectric 6 after the not patterned and etching these layers.Gate dielectric 6 can comprise silica, nitrogen oxide, nitride and high-k material, and gate electrode 8 then is preferably polysilicon, although it may be made of the composite construction of a metal or a dielectric layer/metal/semiconductor.This composite construction and gate dielectric can be made of structure shown in Figure 1.
Fig. 2 b shows that a pair of sept (spacer) 10 forms along the sidewall of this gate dielectric 6 with gate electrode 8.As described below, sept 10 will form at follow-up source/drain and be used as the screen cover of aiming at voluntarily (self-aligning mask) in the step.Above-mentioned sept can form by known method, for example, remove the horizontal surface of above-mentioned dielectric medium and stay sept 10 to (anisotropically) etching by non-grade more afterwards comprising substrate 2 dielectric layer of whole regional blanket type deposition with gate electrode 8.Doping is implemented to form part or whole transistor source and drain region in zone in the substrate 2 on gate dielectric 6 or sept 10 each limit.
Shown in Fig. 2 c, semiconductor layer 12 of epitaxial deposition, its thickness about 400 to
It can impose on part or all of transistor source and drain region, and the preferred mode that forms this semiconductor layer 12 to be selective epitaxial grow up.At first form a silicon dioxide layer (not shown) and cover in the substrate, pass through this silicon dioxide layer afterwards and form opening, follow epitaxial growth semiconductor layer 12 again to expose source/drain regions.Semiconductor layer 12 is preferable by molecular beam epitaxy (Molecular Beam Epitaxy, MBE) form, also can utilize other deposition techniques, comprise chemical vapour deposition technique, high vacuum chemical vapour deposition process (Ultra High Vacuum Chemical VaporDeposition, UHVCVD), atomic layer chemical vapor deposition method (Atomic LayerChemical Vapor Deposition, ALCVD) or Metalorganic chemical vapor deposition method (Metal Organic Chemical Vapor Deposition, MOCVD), and deposit, temperature range is preferable between 300 to 950 ℃, better between 450 to 850 ℃, and in forming down less than 100mTorr (mTorr represents millitorr, and 1mTorr approximates 0.133 Pascal) at pressure.At semiconductor layer 12 of substrate institute area exposed epitaxial growth, and form a polycrystalline structure on above-mentioned silicon dioxide layer (not shown), this polycrystalline structure of etching afterwards and silicon dioxide only stay semiconductor layer 12.Semiconductor layer 12 promptly is source electrode and the drain region part that forms metal oxide semiconductor transistor.Generally speaking, be preferably highly doped at semiconductor layer 12 formed source electrodes and drain region (for example greater than 2 * 10
20Cm
-3).
The step of doping semiconductor layer 12 can be finished in the epitaxial growth processing procedure or in the follow-up ion implantation step.In a preferred embodiment, the doping of this semiconductor layer 12 can be carried out synchronously with this epitaxial growth step, finishes to reative cell by import suitable alloy (for example boron, phosphorus, arsenic etc.) and other reacting gass (for example silicon, germanium, hydrogen, chlorine, nitrogen, helium etc.) in the step of epitaxial growth.
Among other embodiment, semiconductor layer 12 can have a hierarchical structure (layeredstructure), and its layer that is positioned at the top can not cover all or partly the bottom layer not.In this embodiment, directly low than the energy gap of substrate 2 with other energy gap of upper layers of Metal Contact.
Shown in Fig. 2 d, metal level 14 is formed on source electrode and the drain region, and preferable being formed on the gate electrode.The thickness of metal level 14 is preferable to be lower than approximately
Metal level 14 can be transition metal or metallic compound, for example titanium, cobalt, tungsten, tantalum etc., or other are by suitable electric conducting materials of chemical vapour deposition technique, physical vaporous deposition or additive method deposition.As mentioned above, between metal level 14 and semiconductor layer 12 formed Schottky barrier directly to contact formed potential barrier than metal level 14 and substrate 2 low.In this manual, layer other 14 can be metal level or metal silicified layer, and according to different embodiment, layer other 14 can be a metal level, also can be by metal level and the formed metal silicide of semiconductor regions effect that is positioned at its below, can also be its combination (for example, be positioned on the metal silicified layer metal level).
In a preferred embodiment, metal level 14 is metal silicides.This metal silicide can include nitrogen or carbon atom, and can comprise 1 to 25at.% germanium, and is preferably and comprises 1 to 5at.% germanium.Metal silicide can adopt the silicide of transition metal, and can comprise more than one transition metal.In a preferred embodiment, at first form metal level 14, by depositing a thin metal layer (for example titanium, cobalt, nickel, tungsten etc.) to an element, and comprise the surface of exposed semiconductor layer 12 and gate electrode 8.Afterwards this element is higher than in temperature and carries out tempering under 300 ℃, and preferable temperature range between 400 to 800 ℃, and under the gaseous environment that comprises one of gases such as hydrogen, nitrogen, helium, neon, argon, xenon or its combination, be lower than about 10 holders at pressure, and be more preferred under the pressure that is lower than about 1 holder, at the above-mentioned metal that deposits and be positioned between the exposed silicon area (being source/drain regions and polysilicon gate conductor 8) below it and form a metal silicide, the metal silicide that is produced is shown in the metal level among Fig. 2 d 14.Although thickness depends on design, the thickness of formed metal silicified layer 14 preferable between 300 to
Between.In another embodiment, metal silicified layer 14 can directly form by plated metal silicide (for example cobalt silicide or nickle silicide), the deposition technique that utilization is known, for example Low Pressure Chemical Vapor Deposition, plasma-assisted chemical vapour deposition method, thermal chemical vapor deposition method, laser ablation method (laser ablation), ion beam sputtering deposition method (ion sputter), electron beam sputtering method (e-beam sputter) directly are formed into it on surface of source electrode, drain region and gate electrode 8.
Shown in Fig. 2 e, then dielectric layer 16 of blanket type deposition on element, the thickness of this dielectric layer 16 be preferably about 50 to
Between.Dielectric layer 16 can form by Low Pressure Chemical Vapor Deposition, also can use other chemical vapour deposition techniques, for example plasma-assisted chemical vapour deposition method (Plasma Enhanced ChemicalVapor Deposition; PECVD) and thermal chemical vapor deposition method (thermalCVD). as mentioned above, select preferable dielectric layer 16 not only to need to consider its dielectric property, also need consider its between semiconductor layer 12 and the metal level 14 and between semiconductor layer 12 and the substrate below it 2 because of the compensation ability of the stress that lattice mismatch produced. lattice mismatch may produce the defective that usefulness is reduced at contact-making surface, and these defectives may be dispersed throughout these affected layers not in.
In above-mentioned preferred embodiment, on a silicon substrate, form the source electrode and the drain region of germanium silicon carbide (SiGeC), and the surface forms a metal silicified layer above this source electrode and drain region, and may on this metal silicified layer, cause a comprehensive stress (for example stretching or compression) between the lattice mismatch of other of each layer, generally approximately between scope 400MPa to 4GPa, but can compensate this stress by material and the depositional mode of selecting dielectric layer 16 at least.In a preferred embodiment, dielectric layer 16 is made of the composite construction of an oxide/nitrogen oxide, at first forms a thickness and is about
The first oxide lower floor, then form a thickness again and be about
Oxynitride layer, wherein, above-mentioned oxide and oxynitride layer are preferable to be formed by the plasma-assisted chemical vapour deposition method that is lower than in temperature under 550 ℃.The element that is to use oxide/nitrogen oxide composite dielectric layer 16 that Fig. 3 shows, wherein, material 24 is nitrogen oxide, material 22 is oxides.
Above-mentioned dielectric layer is the preferable stress that provides probably between 400MPa to 4GPa, and is preferably the scope between 400MPa to 2GPa.Those skilled in the art as can be known, great majority compressions and stretching stress can obtain to compensate by material and the depositional mode that changes dielectric layer 16.For example, can be used to provide the film with stretching stress by the silicon nitride that Low Pressure Chemical Vapor Deposition deposited, same, the silicon nitride layer that is deposited by the plasma-assisted chemical vapour deposition method can be used to provide the film with compression stress.
Shown in Fig. 2 f, interlayer dielectric layer 18, or metal dielectric layer (pre-metaldielectric) or dielectric layer between metal layers (inter-metal dielectric) before well-known to those skilled in the art deposit to the surface of dielectric layer 16 subsequently.This interlayer dielectric layer 18 is preferably utilization such as tetraethyl oxosilane (Tetraethylorthosilicate; TEOS), the silicon dioxide of the techniques of deposition known to chemical vapour deposition technique, plasma-assisted chemical vapour deposition method, Low Pressure Chemical Vapor Deposition or other those skilled in the art.This interlayer dielectric layer 18 is used to provide the isolation between transistor and the metal wire above it.Photoresist (not shown) can above this interlayer dielectric layer 18, form and patterning to be formed up to the contact window of source electrode and drain region and gate electrode.What Fig. 2 g showed is the element of part after etching that interlayer dielectric layer 18 is not covered by photoresistance, thereby opens the contact window that is arranged in interlayer dielectric layer 18.It should be noted that dielectric layer 16 can be as etching stopping layer in the process of etching interlayer dielectric layer 18, thereby protection is positioned at the metal silicified layer 14 of its below.Then, etching is positioned at the part that the dielectric layer 16 of contact window is exposed, and preferable use reactive ion etching (Reactive Ion Etch, RIE).Because dielectric layer 16 is extremely thin for interlayer dielectric layer 18, so the control that the detecting of the control of processing procedure and terminal point need be tighter, be positioned at the metal silicified layer 14 of dielectric layer 16 belows to prevent excessive eating thrown.
What Fig. 2 g showed is when metal plug (plug) the 20 element schematic diagram after the formation in contact window.Metal plug 20 can be made of the material known to tungsten, aluminium, copper or other those skilled in the art, can also be composite construction, for example barrier layer (barrier) or adhesion layer (adhesion layer), and perhaps titanium/titanium nitride or tantalum nitride, or other layers are not.The invention provides a kind of structure of novelty, wherein metal plug 20 contacts with a metal silicified layer 14, and this metal silicified layer 14 contacts with the low gap material 12 that is positioned at its below, and by compensating the dielectric layer 16 of stress, reduce the defective of contact resistance and induced stress, and then improve the usefulness of element.
Though the present invention by the preferred embodiment explanation as above, this preferred embodiment is not in order to limit the present invention.Those skilled in the art without departing from the spirit and scope of the present invention, should have the ability this preferred embodiment is made various changes and replenished, so protection scope of the present invention is as the criterion with the scope of claims.
Being simply described as follows of symbol in the accompanying drawing:
4: shallow trench isolation is from 16: dielectric layer
6: gate dielectric 18: interlayer dielectric
8: gate electrode 20: the metal plug
10: sept 22: oxide
12: the second energy gap layers 24: nitrogen oxide
Claims (19)
1. an integrated circuit component is characterized in that, this integrated circuit component comprises:
A substrate is made of the semiconductor with first energy gap;
A gate dielectric is positioned in this substrate;
A gate electrode is positioned on this gate dielectric;
Source electrode and drain region are arranged in this gate dielectric substrate on two sides, and this source electrode and drain region have at least one upper section, and this upper section is made of the semiconductor with second energy gap, and this second energy gap is lower than this first energy gap;
A metal level, be arranged in this source electrode and drain region at least one upper section above;
One first dielectric layer is positioned at this metal level top;
One second dielectric layer is positioned at this first dielectric layer top, wherein this first dielectric layer and this second dielectric layer in order to the upper section that compensates this source electrode and drain electrode and this metal level because of stress that lattice mismatch produced;
An interlayer dielectric layer is positioned at this second dielectric layer top; And
A conductive plugs, this conductive plugs contacts with this metal level, and is arranged in this first dielectric layer, this second dielectric layer and this interlayer dielectric layer.
2. integrated circuit component according to claim 1 is characterized in that: described first dielectric layer has an intrinsic compression stress or tensile stress.
3. integrated circuit component according to claim 1 is characterized in that: the material of described substrate comprises one or more the combination in the strained silicon on silicon, germanium, compound semiconductor, silicon-coated insulated body, the relaxed silicon-Germanium.
4. integrated circuit component according to claim 1 is characterized in that: the upper section extension of described source electrode and drain region is dispersed throughout described source electrode and drain region.
5. integrated circuit component according to claim 1 is characterized in that: the material of described source electrode and drain region upper section comprises silicon and germanium.
6. integrated circuit component according to claim 5 is characterized in that: the material of described source electrode and drain region upper section also comprises carbon.
7. integrated circuit component according to claim 5 is characterized in that: the content of this germanium is between the 10-50 atomic percent.
8. integrated circuit component according to claim 1 is characterized in that: the surface, top of described source electrode and drain region has a doping content and is higher than 2 * 10
20Cm
-3Impurity, and this impurity comprises one or more the combination in boron, phosphorus, arsenic, indium, the antimony.
9. integrated circuit component according to claim 1 is characterized in that: described metal level is a metallic compound.
10. integrated circuit component according to claim 9 is characterized in that: described metallic compound is a metal silicide.
11. integrated circuit component according to claim 10 is characterized in that: the composition of described metal silicide comprises a kind of or its combination in nitrogen, the carbon at least.
12. integrated circuit component according to claim 10 is characterized in that: described metal silicide is a transition metal silicide.
13. integrated circuit component according to claim 9 is characterized in that: described metallic compound comprises two or more transition metal.
14. integrated circuit component according to claim 1 is characterized in that: described source electrode and drain region are depressed in the described substrate.
15. a method that forms integrated circuit component is characterized in that this method comprises the following steps:
Form a gate dielectric on a surface of a substrate, wherein, this substrate is made of one first kenel semiconductor;
On this gate dielectric, form a gate electrode;
Along forming a pair of sept on this gate electrode sidewall relative with this gate dielectric;
Epitaxial growth source electrode and drain region on this surface of this substrate that is positioned at these gate dielectric both sides, wherein, at least one surface, top of this source electrode and drain region is made of one second kenel semiconductor, and the semi-conductive energy gap of wherein said second kenel is lower than the semi-conductive energy gap of first kenel that forms described substrate;
Metal level of formation above at least one in this source electrode and drain region;
On this metal level, form one first dielectric layer;
On this first dielectric layer, form one second dielectric layer;
On this second dielectric layer, form an interlayer dielectric layer;
In this first dielectric layer, this second dielectric layer and this interlayer dielectric layer, form an opening, wherein this first dielectric layer and this second dielectric layer in order to the top that compensates this source electrode and drain electrode surperficial and this metal level because of stress that lattice mismatch produced; And
In this opening, form a conductive plugs.
16. the method for formation integrated circuit component according to claim 15, it is characterized in that: the method for described source electrode of epitaxial growth and drain electrode comprises the selective epitaxial flop-in method, wherein, the reacting gas of this selective epitaxial flop-in method comprises a kind of or its combination in silicon, germanium, hydrogen, chlorine, nitrogen, helium, phosphorus, boron, the arsenic.
17. the method for formation integrated circuit component according to claim 15 is characterized in that: described metal level is a metal silicide, forms by the metal silication program.
18. the method for formation integrated circuit component according to claim 17 is characterized in that, the method for described formation metal level also comprises:
Be higher than 300 ℃ and pressure in temperature and carry out first tempering step under less than 10 holders, and gaseous environment comprises hydrogen, nitrogen, helium, neon, argon, xenon or its combination.
19. the method for formation integrated circuit component according to claim 15 is characterized in that: described first dielectric layer has an intrinsic tensile stress or compression stress.
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|---|---|---|---|
| CN200410057339A CN1866539B (en) | 2004-08-27 | 2004-08-27 | Integrated circuit element and forming method thereof |
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| CN102437117B (en) * | 2011-08-29 | 2014-04-30 | 上海华力微电子有限公司 | Novel process for integrating silicide and metal foredielectric and forming structure thereof |
| CN104880206B (en) * | 2015-06-09 | 2018-03-06 | 中国科学院深圳先进技术研究院 | Resistance strain gage and resistance strain type sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1123470A (en) * | 1994-09-13 | 1996-05-29 | 株式会社东芝 | Insulated-gate device (IG device) having narrowbandgap-source structure and method of manufacturing the same |
| US6046103A (en) * | 1999-08-02 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Borderless contact process for a salicide devices |
| CN2731721Y (en) * | 2003-08-29 | 2005-10-05 | 台湾积体电路制造股份有限公司 | Integrated circuit component |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1123470A (en) * | 1994-09-13 | 1996-05-29 | 株式会社东芝 | Insulated-gate device (IG device) having narrowbandgap-source structure and method of manufacturing the same |
| US6046103A (en) * | 1999-08-02 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Borderless contact process for a salicide devices |
| CN2731721Y (en) * | 2003-08-29 | 2005-10-05 | 台湾积体电路制造股份有限公司 | Integrated circuit component |
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