CN1875355A - 包括多个存储器集线器模块的多处理器系统和方法 - Google Patents
包括多个存储器集线器模块的多处理器系统和方法 Download PDFInfo
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Abstract
一种基于处理器的电子系统,包括以第一级和第二级形式设置的几个存储器模块。第一级存储器模块是通过几个处理器中的任一处理器直接存取的,并且第二级存储器模块是由处理器通过第一级存储器模块进行存取的。通过改变用于存取第二级存储器模块的第一级存储器模块的数目,来改变处理器和第二级存储器模块之间的数据带宽。每个存储器模块都包括几个连接到存储器集线器的存储装置。存储器集线器包括连接到每个存储装置的存储器控制器,连接到相应处理器或存储器模块的链路接口,以及将任一存储器控制器连接到任一链路接口的交叉开关。
Description
技术领域
本发明涉及计算机系统,并且尤其涉及一种具有能够以多种配置连接到几个存储器集线器模块的几个处理器或其它存储器存取装置的计算机系统。
背景技术
计算机系统使用存储装置如DRAM(动态随机存取存储器)装置来存储处理器所存取的指令和数据。这些存储装置通常作为计算机系统中的系统存储器。在典型计算机系统中,处理器通过处理器总线和存储器控制器与系统存储器进行通信。处理器发布存储器请求,该存储器请求包括诸如读命令的存储器命令、以及指明数据或指令要被读出或写入的位置的地址。存储器控制器利用该命令和地址来产生应用于系统存储器的适当命令信号以及行和列地址。响应于这些命令和地址,数据在系统存储器和处理器之间被传送。存储器控制器常常是系统控制器的一部分,系统控制器也包括用于将处理器总线连接到扩展总线如PCI(外围部件互联)总线的总线桥电路。
虽然存储装置的操作速度已不断增加,但是这种操作速度的增加没有跟上处理器操作速度的增加。结果,处理器与它所连接的存储装置之间的数据带宽大大低于处理器的数据带宽能力。处理器与存储装置之间的数据带宽在很大程度上受处理器和存储装置之间的更低数据带宽的限制。
除处理器与存储装置之间的有限带宽以外,计算机系统的性能也受到增加从存储装置读取数据所需时间的等待时间问题的限制。更具体地说,当存储装置读命令被耦合到存储装置如SDRAM(同步动态随机存取存储器)装置时,只有在几个时钟周期的延迟之后,所读取的数据才从SDRAM装置输出。因此,虽然SDRAM装置能够以高数据速率同步输出猝发数据,但是最初提供数据时的延迟可以大大降低使用这种SDRAM装置的计算机系统的操作速度。
图1示出了一种缓解存储器等待时间问题的方法。如图1所示,计算机系统10包括连接到几个存储器模块20a-f的处理器14,虽然可以使用更少或更多数量的存储器模块20。每个存储器模块20都包括连接到几个存储装置28的存储器集线器24,存储装置28可以是SDRAM装置。在图1中,存储器模块20被显示为通过单向输入总线30和单向输出总线38连接到处理器14以及互连。然而,应该理解,存储器模块20可以通过双向总线(未示出)连接到处理器14以及互连。
在图1中,存储器模块20被显示为以点对点配置方式进行连接,其中每条总线30和38只在两个点之间进行连接。然而,作为选择可以使用其它总线系统。例如,也可以使用如图2A所示的开关总线系统、如图2B所示的共享总线系统或其它某种总线系统。图2A所示的开关总线系统包括连接到开关电路42的处理器40。开关电路42连接到几个存储器模块44a-d、图形处理器46及I/O(输入/输出)设备48。在操作中,开关电路42将处理器40连接到存储器模块44a-d、图形处理器46或I/O设备48中的任何一个。图2B所示的共享总线系统包括通过共享总线系统58连接到几个存储器模块54a-c的处理器50。
上述体系结构的任何一种也可用于将多个处理器连接到多个存储器模块。例如,如图3所示,一对处理器60、62通过各自的双向总线系统64连接到各自的存储器模块组66a-e、68a-e。存储器模块66a-e和68a-e的每一个都包括连接到几个存储装置28的存储器集线器24。
如图1和3所示的存储器集线器结构能够提供远远优于其中处理器直接或通过系统或存储器控制器连接到几个存储装置的体系结构的性能。然而,它们仍然受到几种限制。例如,图1所示的体系结构对于处理器14可以存取存储器模块20a-f的方式不提供高度灵活性。例如,如果总线30-38包括32位数据总线,则即使正在从存储器模块20a-f读出、或者正在向存储器模块20a-f写入较少数量的数据位,所有对存储器模块20a-f的存取也都将是32位双字节形式。
图1和3所示体系结构的灵活性也受其它方面的限制。例如,图3所示的体系结构对于处理器60和62分别可以存取存储器模块66a-e和68a-e的方式不提供高度灵活性。虽然处理器60可以存取存储器模块66a-f的任何一个,并且处理器62可以存取存储器模块68a-e的任何一个,但是处理器60不能存取存储器模块68a-e的任何一个,而且处理器62也不能存取存储器模块66a-e的任何一个。结果,如果处理器60向存储器模块66a-e写入充足的数据,从而达到了存储器模块66a-e的存储容量,则即使存储器模块68a-e中可能有大量未使用容量,处理器60也将不能存储任何更多的数据。
图1和3所示存储器体系结构的另一个限制是处理器14、60和62在存取它们各自的存储器模块20、66和68的过程中所引起的较长等待时间。在通过位于存储器模块和处理器之间的任何存储器模块来存取每个存储器模块的范围内,在通过其间的存储器模块来传送地址、数据和控制信号的过程中可以引起大延迟。进一步,如果存储器模块20、66和68的任何一个变得有缺陷,则必须通过该有缺陷的模块进行存取的存储器模块将变得不可用。
因此,需要这样一种存储器系统体系结构,该存储器系统体系结构具有较强容错(fault-intolerant)能力,提供较短等待时间存储器存取,并允许多处理器对于它们存取基于集线器的存储器模块的方式具有高度灵活性。
发明内容
一种存储器系统包括连接到第一级存储器模块的多个存储器请求器。第一级存储器模块的每一个都包括在数量上和存储器请求器数目相对应的第一组存储器端口。第一级中的每个存储器端口都连接到相应的一个存储器请求器。第一级存储器模块进一步包括第二组存储器端口。该存储器系统还包括第二级存储器模块,第二级存储器模块的每一个都具有通过第二组存储器端口连接到第一级中至少一个存储器模块的至少一个存储器端口。第一和第二级中的每个存储器模块都包括多个存储装置、以及连接到存储装置和第一组及任何第二组存储器端口的存储器集线器。存储器集线器优选地包括:连接到模块中相应存储装置的多个存储器控制器;多个链路接口,每个链路接口都连接到存储器请求器之一或另一模块;以及交叉开关,该交叉开关具有连接到相应链路接口的第一多个开关端口、以及连接到相应存储器控制器的多个存储器端口。该交叉开关用于选择性地将每个链路接口连接到任一存储器控制器。
附图说明
图1是包括几个存储器模块的、基于处理器的常规电子系统的框图,其中每个存储器模块都包括连接到几个存储装置的存储器集线器。
图2A和2B所示为用于将存储器模块连接到多个处理器的各种常规体系结构的框图。
图3是包括连接到相应存储器模块组的多个处理器的、基于处理器的常规电子系统的框图,其中每个存储器模块都包括连接到几个存储装置的存储器集线器。
图4是根据本发明一个实施例的、连接到几个存储器模块的基于处理器的系统的框图。
图5是可用于图4和图6的基于处理器的系统中的存储器模块的框图。
图6是根据本发明另一实施例的、连接到几个存储器模块的基于处理器的系统的框图。
具体实施方式
图4示出了根据本发明一个例子的基于处理器的电子系统100。系统100包括三个处理器104、106、108以及DMA(直接存储器存取)装置110,如图形控制器。DMA装置110和处理器104-108的每一个都包括4个存储器存取端口112、114、116和118。端口112-118优选地包括数据端口以及单独或共享控制和地址端口。然而,应该理解,可以使用其它某种存储器端口配置,如用于接收和发送分组的端口。系统100还包括第一级(130)4个存储器模块132、134、136和138,每个存储器模块都包括第一组4个存储器存取端口142、144、146和148。如下所说明的,存储器模块132-138的每一个都包括连接到8个存储装置的存储器集线器,这8个存储装置优选地为DRAM(动态随机存取存储器)装置,并且更为优选地是SDRAM(同步DRAM)装置。然而,应该理解,在存储器模块132-138的每一个中,可以将更多或更少数量的存储装置连接到存储器集线器。
第一处理器104的存储器存取端口112、114、116和118通过相应总线162、164、166和168分别连接到存储器模块132、134、136和138的每一个的存储器存取端口142。类似地,第二处理器106的存储器存取端口112、114、116和118通过相应总线172、174、176和178分别连接到存储器模块132、134、136和138的每一个的存储器存取端口144,并且第三处理器108的存储器存取端口112、114、116和118通过相应总线182、184、186和188分别连接到存储器模块132、134、136和138的每一个的存储器存取端口146。结果,处理器104-108的任何一个都能够存取存储器模块132-138的任何一个。以类似的方式,DMA装置110的存储器存取端口112、114、116和118通过相应总线192、194、196和198分别连接到存储器模块132、134、136和138的存储器存取端口148。因而,DMA装置108也能够存取存储器模块132、134、136和138的每一个。
存储器模块132、134、136和138的每一个也包括第二组4个存储器存取端口202、204、206和208,这第二组4个存储器存取端口202、204、206和208连接到第二级(210)4个存储器模块212、214、216和218。更具体地说,存储器模块132的存储器存取端口202、204、206和208通过相应总线232、234、236和238分别连接到存储器模块212、214、216和218的相应存储器存取端口222。类似地,存储器模块134的存储器存取端口202、204、206和208通过相应总线242、244、246和248分别连接到存储器模块212、214、216和218的每一个的存储器存取端口224,并且存储器模块136的存储器存取端口202、204、206和208通过相应总线252、254、256和258分别连接到存储器模块212、214、216和218的每一个的存储器存取端口226。最后,存储器模块138的存储器存取端口202、204、206和208通过相应总线262、264、266和268分别连接到存储器模块212、214、216和218的每一个的存储器存取端口228。
和第一级130中的存储器模块132-138一样,第二级210中的存储器模块212-218的每一个都包括连接到8个存储装置的存储器集线器。如以下更详细说明的,第一级130的存储器模块132-138中的每一个存储器集线器都包括能够将存储器存取端口112-118的任何一个连接到存储器存取端口202-208的任何一个的交叉开关(图4中未示出)。同样地,第二级210中的存储器模块212-218的每一个中的存储器集线器都能够将存储器存取端口202-208的任何一个连接到存储器存取端口222-228的任何一个。结果,处理器102-106和DMA装置108的任何一个都能够直接存取存储器模块132-138的任何一个,以及通过存储器模块132-138存取存储器模块212-218的任何一个。与利用图1和3所示类型的存储器体系结构可以得到的等待时间相比,处理器102-106与存储器模块132-138和212-218之间、以及DMA装置108与存储器模块132-138和212-218之间的这种紧密接近性导致了较短的等待时间。
图4所示存储器拓扑结构的另外优点是,通过只改变到存储器模块212-218的互连数量,就能够改变处理器102-106或DMA装置108的任何一个与第二级210中的存储器模块212-218的任何一个之间的数据带宽。例如,如果每一条总线都是16位宽,则处理器106可以只利用一条从处理器106延伸到模块132-138之一的总线、以及一条从模块132-138之一延伸到模块212-218之一的总线,来通过16位数据总线连接到存储器模块212-218的任何一个。处理器106可以通过连接到模块132-138中的两个模块、并通过相应总线从这两个模块132-138的每一个连接到模块212-218之一,经由32位数据总线连接到存储器模块212-218的任何一个。处理器106可以通过连接到模块132-138中的三个模块、并通过相应总线从这三个模块132-138的每一个连接到模块212-218之一,经由48位数据总线连接到存储器模块212-218的任何一个。最后,处理器106可以通过连接到所有4个模块132-138、并通过相应总线从这4个模块132-138的每一个连接到模块212-218之一,经由64位数据总线连接到存储器模块212-218的任何一个。
图5示出了可用于图4的存储器模块132-138、212-218中的存储器集线器300的一个实施例。存储器集线器300包括4个链路接口304a-d,这4个链路接口304a-d连接到相应总线,如图4所示第一组中的总线。类似地,4个附加链路接口308a-d被包括进来,它们也连接到相应总线,如图4所示第二组中的总线。所有链路接口304和308都连接到交叉开关310,交叉开关310可以具有常规或以下开发的结构。如前面参考图4所说明的,交叉开关310能够将链路接口304a-d的任何一个连接到链路接口308a-d的任何一个。链路接口304a-d和308a-d可以是单向或双向接口,并且耦合到或耦合自链路接口304a-d和308a-d的存储器存取的性质可以随意变化,包括常规DRAM地址、控制和数据信号、共享地址和控制信号、以及分组存储器存取信号。
交叉开关310也能够将链路接口304a-d和308a-d的任何一个连接到4个DRAM控制器314a-d,每个DRAM控制器都连接到多个DRAM装置(图5中未示出)。DRAM控制器314a-d可以是常规DRAM控制器或以下开发的某种DRAM控制器结构。当然,DRAM控制器314a-d的特定结构和操作将取决于存储器模块中所使用的DRAM装置的性质。交叉开关310将链路接口304a-d连接到DRAM控制器314a-d,以允许多个存储器存取装置的任何一个向连接到控制器314a-d的DRAM装置写数据、或从中读数据,如以上参考图5所说明的。交叉开关310将链路接口308a-d连接到DRAM控制器314a-d,以允许将任何数据从连接到DRAM控制器314a-d的DRAM装置传送到包括存储器集线器300的其它存储器模块,或者将任何数据从包括存储器集线器300的其它存储器模块传送给连接到DRAM控制器314a-d的DRAM装置。
对于由相应DRAM控制器314a-d服务的每个DRAM装置,存储器集线器300还包括高速缓冲存储器320a-d和写缓冲器324a-d。如本领域所周知的,可以是SRAM(静态随机存取存储器)装置的高速缓冲存储器320a-d的每一个都存储由相应DRAM控制器314a-d服务的DRAM装置中所存储的最近或经常存取数据。如果DRAM装置正忙于为读存储器请求服务,或者有其它读请求被挂起,则写缓冲器324a-d积累针对由DRAM控制器314a-d中相应DRAM控制器服务的DRAM装置的写地址和数据。通过这样积累写存储器请求,可以以流水线方式更有效地处理它们,因为不必引起与交替写和读请求关联的延迟。
如上所述,可以将数据从一个包括存储器集线器300的存储器模块传送到另一个包括存储器集线器300的存储器模块。这些模块间数据传送受DMA(直接存储器存取)引擎330控制,DMA引擎330可以具有常规或以下开发的结构。DMA引擎330也可用于在禁止部分有缺陷存储器模块的操作之前,将数据从多个有缺陷存储器模块传送给正确运行的存储器模块。
存储器集线器300一般将包括除图5所示部件以外的部件。然而,为简洁或清楚起见而省略了这些部件。同样,在某些应用中,可以省略图5所示的部件。例如,如果写/读存取翻转可以接受,则可以省略写缓冲器324a-d。同样,虽然图5所示的存储器集线器300包括2组4个链路接口304a-d和308a-d、以及4个DRAM控制器314a-d,但是链路接口组的数目、每一组中链路接口的数目以及DRAM控制器的数目可以随意变化。
图6示出了基于处理器的电子系统350的替换实施例。系统350包括4个存储器请求器352a-d,如处理器或直接存储器存取装置,存储器请求器352a-d的每一个都通过一般以358表示的总线连接到第一级354的4个存储器模块356a-d。从而,用和图4实施例相同的方式来配置存储器模块356a-d。然而,不是象图4实施例那样将第一级354中的每个存储器模块356连接到第二级存储器模块中的每个存储器模块,而是将存储器模块356a-d每一个都连接到第二级360中的相应一组4个存储器模块。从而,第一存储器模块356a连接到4个存储器模块362a-d,第二存储器模块356b连接到4个存储器模块362e-h,第三存储器模块356c连接到4个存储器模块362i-l,以及第四存储器模块356d连接到4个存储器模块362m-p。图6所示拓扑结构比图4所示拓扑结构的有利之处在于,与使用图4所示拓扑结构的第二级210中的存储器模块相比,第二级360的存储器模块362提供更大的存储容量。然而,图6所示存储器拓扑结构的不利之处在于,它提供较小的带宽和较小的存取第二级360中的存储器模块362的灵活性。
由以上应该理解,虽然在此为说明起见而描述了本发明的特定实施例,但是在不背离本发明精神和范围的情况下可以进行各种更改。例如,虽然处理器104-108和DMA装置110被显示为直接连接到存储器模块132-138,但是应该理解,它们可以通过其它装置如总线桥进行连接。同样,图4和图6分别显示的系统100和350正常将包括除所示部件以外的部件。因此,本发明不受除附加权利要求以外的事物的限制。
Claims (45)
1.一种用于将多个存储器请求器的每一个连接到多个存储装置的每一个的存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
第一多个链路接口;以及
具有第一多个开关端口和多个存储器端口的交叉开关,每个所述开关端口都连接到相应的一个所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将每个所述链路接口连接到任何一个所述存储器控制器。
2.根据权利要求1所述的存储器集线器,进一步包括第二多个链路接口,并且其中所述交叉开关进一步包括第二多个开关端口,该第二多个开关端口的每一个都连接到所述第二多个链路接口中的相应的一个链路接口。
3.根据权利要求1所述的存储器集线器,其中每个所述存储器控制器都包括动态随机存取存储器控制器。
4.根据权利要求1所述的存储器集线器,进一步包括与每个所述存储器控制器相关联的相应的高速缓冲存储器装置,每个所述高速缓冲存储器装置都用于存储通过所述交叉开关的相应的一个存储器端口存取的数据。
5.根据权利要求1所述的存储器集线器,其中每个所述链路接口都包括双向链路接口。
6.根据权利要求1所述的存储器集线器,其中每个所述链路接口都包括一对单向链路,该对单向链路之一包括输入端口,并且该对单向链路的另一个包括输出端口。
7.根据权利要求1所述的存储器集线器,进一步包括与每个所述存储器控制器相关联的相应的写缓冲器,每个所述写缓冲器都用于通过所述交叉开关的相应的一个存储器端口接收写数据和关联的写地址,并存储所述写数据和地址以便随后耦合到相应的一个所述存储器控制器。
8.根据权利要求7所述的存储器集线器,其中每个所述写缓冲器为多个写存储器存取积累写数据和地址,然后在没有任何介入读存储器存取的情况下,顺序地将多个写数据和地址耦合到相应的一个所述存储器控制器。
9.根据权利要求1所述的存储器集线器,进一步包括连接到所述交叉开关和所述存储器控制器的直接存储器存取装置,该直接存储器存取装置用于使所述交叉开关和每个所述存储器控制器执行存储器写和读存取。
10.一种存储器模块,包括:
基板;
由所述基板承载的多个存储装置;以及
由所述基板承载的存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
第一多个链路接口,该第一多个链路接口的每一个用于连接到多个存储器请求器的每一个;以及
具有第一多个开关端口和多个存储器端口的交叉开关,每个所述开关端口都连接到相应的一个所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将每个所述链路接口连接到任何一个所述存储器控制器。
11.根据权利要求10所述的存储器模块,其中所述存储器集线器进一步包括第二多个链路接口,并且其中所述交叉开关进一步包括第二多个开关端口,该第二多个开关端口的每一个都连接到所述第二多个链路接口中的相应的一个链路接口。
12.根据权利要求10所述的存储器模块,其中每个所述存储装置都包括动态随机存取存储器装置。
13.根据权利要求10所述的存储器模块,其中所述存储器集线器进一步包括与每个所述存储器控制器相关联的相应的高速缓冲存储器装置,每个所述高速缓冲存储器装置都用于存储通过所述交叉开关的相应的一个存储器端口存取的数据。
14.根据权利要求10所述的存储器模块,其中所述基板包括半导体基板,并且其中所述存储装置、链路接口、存储器控制器和交叉开关被制造为所述半导体基板上的公共集成电路。
15.根据权利要求10所述的存储器模块,其中所述存储器集线器中的每个链路接口都包括双向链路接口。
16.根据权利要求10所述的存储器模块,其中所述存储器集线器中的每个链路接口都包括一对单向链路,该对单向链路之一包括输入端口,并且该对单向链路的另一个包括输出端口。
17.根据权利要求10所述的存储器模块,其中所述存储器集线器进一步包括与每个所述存储器控制器相关联的相应的写缓冲器,每个所述写缓冲器都用于通过所述交叉开关的相应的一个存储器端口接收写数据和关联的写地址,并存储所述写数据和地址以便随后耦合到相应的一个所述存储器控制器。
18.根据权利要求17所述的存储器模块,其中每个所述写缓冲器为多个写存储器存取积累写数据和地址,然后在没有任何介入读存储器存取的情况下,顺序地将多个写数据和地址耦合到相应的一个所述存储器控制器。
19.根据权利要求10所述的存储器模块,其中所述存储器集线器进一步包括连接到所述交叉开关和所述存储器控制器的直接存储器存取装置,该直接存储器存取装置用于使所述交叉开关和每个所述存储器控制器执行存储器写和读存取。
20.一种存储器系统,包括:
多个存储器请求器;
连接到所述存储器请求器的第一级存储器模块,该第一级中的每个存储器模块都连接到多个所述存储器请求器,每个所述存储器模块包括:
多个存储装置;以及
存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
第一多个链路接口,该第一多个链路接口的每一个都连接到相应的一个所述存储器请求器;以及
具有第一多个开关端口和多个存储器端口的交叉开关,每个所述开关端口都连接到相应的一个所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将每个所述链路接口连接到任何一个所述存储器控制器。
21.根据权利要求20所述的存储器系统,其中所述存储器集线器进一步包括第二多个链路接口,并且其中所述交叉开关进一步包括第二多个开关端口,该第二多个开关端口的每一个都连接到所述第二多个链路接口中的相应的一个链路接口。
22.根据权利要求20所述的存储器系统,其中每个所述存储装置都包括动态随机存取存储器装置。
23.根据权利要求20所述的存储器系统,其中所述存储器集线器进一步包括与每个所述存储器控制器相关联的相应的高速缓冲存储器装置,每个所述高速缓冲存储器装置都用于存储通过所述交叉开关的相应的一个存储器端口存取的数据。
24.根据权利要求20所述的存储器系统,其中基板包括半导体基板,并且其中所述存储装置、链路接口、存储器控制器和交叉开关被制造为所述半导体基板上的公共集成电路。
25.根据权利要求20所述的存储器系统,其中所述存储器集线器中的每个链路接口都包括双向链路接口。
26.根据权利要求20所述的存储器系统,其中所述存储器集线器中的每个所述链路接口都包括一对单向链路,该对单向链路之一包括输入端口,并且该对单向链路的另一个包括输出端口。
27.根据权利要求20所述的存储器系统,其中所述存储器集线器进一步包括与每个所述存储器控制器相关联的相应的写缓冲器,每个所述写缓冲器都用于通过所述交叉开关的相应的一个存储器端口接收写数据和关联的写地址,并存储所述写数据和地址以便随后耦合到相应的一个所述存储器控制器。
28.根据权利要求27所述的存储器系统,其中每个所述写缓冲器为多个写存储器存取积累写数据和地址,然后在没有任何介入读存储器存取的情况下,顺序地将多个写数据和地址耦合到相应的一个所述存储器控制器。
29.根据权利要求20所述的存储器系统,其中所述存储器集线器进一步包括连接到所述交叉开关和所述存储器控制器的直接存储器存取装置,该直接存储器存取装置用于使所述交叉开关和每个所述存储器控制器执行存储器写和读存取。
30.根据权利要求20所述的存储器系统,其中至少一些所述存储器请求器包括处理器。
31.根据权利要求20所述的存储器系统,其中至少一些所述存储器请求器包括直接存储器存取装置。
32.根据权利要求20所述的存储器系统,进一步包括连接到所述第一级的多个存储器模块的第二级存储器模块,该第二级的每个存储器模块都包括:
多个存储装置;以及
存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
第一多个链路接口,该第一多个链路接口的每一个都连接到所述第一级中的相应的一个存储器模块;以及
具有第一多个开关端口和多个存储器端口的交叉开关,每个所述开关端口都连接到相应的一个所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将每个所述链路接口连接到任何一个所述存储器控制器。
33.根据权利要求20所述的存储器系统,进一步包括第二级中的多组存储器模块,该第二级中存储器模块组的数目在数量上对应于所述第一级的存储器模块的数目,所述第二级中的每组存储器模块都连接到所述第一级中的相应的一个存储器模块,所述第二级中的每个存储器模块都包括:
多个存储装置;以及
存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
链路接口,该链路接口连接到所述第二级中相应的一组存储器模块所对应的所述第一级的存储器模块;以及
具有开关端口和多个存储器端口的交叉开关,所述开关端口连接到所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将所述链路接口连接到任何一个所述存储器控制器。
34.根据权利要求20所述的存储器系统,其中所述存储装置、链路接口、存储器控制器和交叉开关被制造为半导体基板上的公共集成电路。
35.一种存储器系统,包括:
多个存储器请求器;
连接到所述存储器请求器的第一级存储器模块,该第一级存储器模块的每一个都包括在数量上和所述存储器请求器的数目相对应的第一组存储器端口,所述第一级中的每个存储器端口都连接到相应的一个所述存储器请求器,所述第一级存储器模块进一步包括第二组存储器端口,所述第一级中的每个存储器模块都包括多个存储装置以及连接到所述存储装置和所述第一及其第二组存储器端口的存储器集线器;
第二级存储器模块,该第二级存储器模块的每一个都包括通过所述第二组存储器端口连接到所述第一级的存储器模块的至少一个存储器端口,所述第二级中的每个存储器模块都包括多个存储装置以及连接到所述存储装置和所述至少一个存储器端口的存储器集线器。
36.根据权利要求35所述的存储器系统,其中所述第二级中的每一个存储器模块都包括在数量上和所述第一级的存储器模块的数目相对应的多个存储器端口,所述第二级的每个存储器模块中的存储器端口都通过所述第二组中的相应的存储器端口连接到所述第一级存储器模块。
37.根据权利要求35所述的存储器系统,其中所述第二级中的多组存储器模块的每一组都连接到所述第一级中的相应的一个存储器模块,所述第一级中的每一个存储器模块都包括连接到所述第二级的相应的一组存储器模块所对应的所述第一级的存储器模块的存储器端口。
38.根据权利要求35所述的存储器系统,其中所述第一级中的每个存储器模块中的存储器集线器都包括交叉开关,所述交叉开关用于将所述第一组存储器端口的任何一个连接到所述第二组存储器端口的任何一个和任何一个所述存储装置。
39.根据权利要求38所述的存储器系统,其中所述交叉开关进一步用于将所述第二组存储器端口的任何一个连接到任何一个所述存储装置。
40.一种用于从多个存储器请求端口存取存储装置的方法,该方法包括:
设置第一级中的第一多个存储器模块,该第一级中的每个存储器模块都包括多个存储装置;
设置第二级中的第二多个存储器模块,该第二级中的每个存储器模块都包括多个存储装置;
从任一所述存储器请求端口存取所述第一级中的每个存储器模块;以及
通过所述第一级中的至少一个存储器模块,从任一所述存储器请求端口来存取所述第二级中的每个存储器模块。
41.根据权利要求40所述的方法,其中通过所述第一级中的至少一个存储器模块来存取所述第二级中每个存储器模块的处理包括:通过所述第一级中的每个存储器模块来存取所述第二级中的每个存储器模块。
42.根据权利要求40所述的方法,其中通过所述第一级中的至少一个存储器模块来存取所述第二级中每个存储器模块的处理包括:通过与所述第二级中的一组存储器模块相对应的所述第一级的存储器模块来存取所述第二级中的一组存储器模块。
43.根据权利要求40所述的方法,进一步包括从所述第二级中的至少一些存储器模块来存取所述第一级中的每一个存储器模块。
44.根据权利要求40所述的方法,其中通过所述第一级中的至少一个存储器模块,从任一所述存储器请求端口来存取所述第二级中每个存储器模块的处理包括:改变借以从所述存储器请求端口之一存取所述第二级存储器模块的所述第一级存储器模块的数目,以改变所述存储器请求端口和正在存取的所述第二级存储器模块之间的数据带宽。
45.根据权利要求40所述的方法,进一步包括在至少一些所述存储器模块中积累写存储器存取,并顺序地执行所存储的写存储器存取。
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- 2004-08-06 WO PCT/US2004/025522 patent/WO2005024560A2/en active Search and Examination
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- 2004-08-06 JP JP2006524680A patent/JP4825993B2/ja not_active Expired - Fee Related
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101236540B (zh) * | 2007-01-29 | 2011-07-20 | 国际商业机器公司 | 选择预取模式的方法、集线器器件、存储器系统及子系统 |
CN102792288A (zh) * | 2009-12-23 | 2012-11-21 | 提琴存储器公司 | 可配置的互连系统 |
CN106055495A (zh) * | 2015-04-14 | 2016-10-26 | 三星电子株式会社 | 用于控制半导体装置的方法 |
CN106055495B (zh) * | 2015-04-14 | 2021-06-22 | 三星电子株式会社 | 用于控制半导体装置的方法 |
CN112840401A (zh) * | 2018-10-16 | 2021-05-25 | 美光科技公司 | 存储器装置处理 |
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EP1665056B1 (en) | 2008-10-08 |
TW200521675A (en) | 2005-07-01 |
US8244952B2 (en) | 2012-08-14 |
WO2005024560A3 (en) | 2005-12-15 |
US20110113189A1 (en) | 2011-05-12 |
WO2005024560A2 (en) | 2005-03-17 |
US20070033317A1 (en) | 2007-02-08 |
ATE410735T1 (de) | 2008-10-15 |
US7581055B2 (en) | 2009-08-25 |
JP2007504530A (ja) | 2007-03-01 |
EP1665056A2 (en) | 2006-06-07 |
KR100928852B1 (ko) | 2009-11-30 |
EP1665056A4 (en) | 2007-02-28 |
US7386649B2 (en) | 2008-06-10 |
US7873775B2 (en) | 2011-01-18 |
CN100580643C (zh) | 2010-01-13 |
JP4825993B2 (ja) | 2011-11-30 |
KR20060126910A (ko) | 2006-12-11 |
US7136958B2 (en) | 2006-11-14 |
US20080215792A1 (en) | 2008-09-04 |
US20120303885A1 (en) | 2012-11-29 |
US20050050255A1 (en) | 2005-03-03 |
US20090282182A1 (en) | 2009-11-12 |
US9082461B2 (en) | 2015-07-14 |
DE602004017029D1 (de) | 2008-11-20 |
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