CN1875355A - 包括多个存储器集线器模块的多处理器系统和方法 - Google Patents

包括多个存储器集线器模块的多处理器系统和方法 Download PDF

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CN1875355A
CN1875355A CNA2004800317853A CN200480031785A CN1875355A CN 1875355 A CN1875355 A CN 1875355A CN A2004800317853 A CNA2004800317853 A CN A2004800317853A CN 200480031785 A CN200480031785 A CN 200480031785A CN 1875355 A CN1875355 A CN 1875355A
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约瑟夫·M·杰德洛
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Micron Technology Inc
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    • GPHYSICS
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    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Abstract

一种基于处理器的电子系统,包括以第一级和第二级形式设置的几个存储器模块。第一级存储器模块是通过几个处理器中的任一处理器直接存取的,并且第二级存储器模块是由处理器通过第一级存储器模块进行存取的。通过改变用于存取第二级存储器模块的第一级存储器模块的数目,来改变处理器和第二级存储器模块之间的数据带宽。每个存储器模块都包括几个连接到存储器集线器的存储装置。存储器集线器包括连接到每个存储装置的存储器控制器,连接到相应处理器或存储器模块的链路接口,以及将任一存储器控制器连接到任一链路接口的交叉开关。

Description

包括多个存储器集线器模块的多处理器系统和方法
技术领域
本发明涉及计算机系统,并且尤其涉及一种具有能够以多种配置连接到几个存储器集线器模块的几个处理器或其它存储器存取装置的计算机系统。
背景技术
计算机系统使用存储装置如DRAM(动态随机存取存储器)装置来存储处理器所存取的指令和数据。这些存储装置通常作为计算机系统中的系统存储器。在典型计算机系统中,处理器通过处理器总线和存储器控制器与系统存储器进行通信。处理器发布存储器请求,该存储器请求包括诸如读命令的存储器命令、以及指明数据或指令要被读出或写入的位置的地址。存储器控制器利用该命令和地址来产生应用于系统存储器的适当命令信号以及行和列地址。响应于这些命令和地址,数据在系统存储器和处理器之间被传送。存储器控制器常常是系统控制器的一部分,系统控制器也包括用于将处理器总线连接到扩展总线如PCI(外围部件互联)总线的总线桥电路。
虽然存储装置的操作速度已不断增加,但是这种操作速度的增加没有跟上处理器操作速度的增加。结果,处理器与它所连接的存储装置之间的数据带宽大大低于处理器的数据带宽能力。处理器与存储装置之间的数据带宽在很大程度上受处理器和存储装置之间的更低数据带宽的限制。
除处理器与存储装置之间的有限带宽以外,计算机系统的性能也受到增加从存储装置读取数据所需时间的等待时间问题的限制。更具体地说,当存储装置读命令被耦合到存储装置如SDRAM(同步动态随机存取存储器)装置时,只有在几个时钟周期的延迟之后,所读取的数据才从SDRAM装置输出。因此,虽然SDRAM装置能够以高数据速率同步输出猝发数据,但是最初提供数据时的延迟可以大大降低使用这种SDRAM装置的计算机系统的操作速度。
图1示出了一种缓解存储器等待时间问题的方法。如图1所示,计算机系统10包括连接到几个存储器模块20a-f的处理器14,虽然可以使用更少或更多数量的存储器模块20。每个存储器模块20都包括连接到几个存储装置28的存储器集线器24,存储装置28可以是SDRAM装置。在图1中,存储器模块20被显示为通过单向输入总线30和单向输出总线38连接到处理器14以及互连。然而,应该理解,存储器模块20可以通过双向总线(未示出)连接到处理器14以及互连。
在图1中,存储器模块20被显示为以点对点配置方式进行连接,其中每条总线30和38只在两个点之间进行连接。然而,作为选择可以使用其它总线系统。例如,也可以使用如图2A所示的开关总线系统、如图2B所示的共享总线系统或其它某种总线系统。图2A所示的开关总线系统包括连接到开关电路42的处理器40。开关电路42连接到几个存储器模块44a-d、图形处理器46及I/O(输入/输出)设备48。在操作中,开关电路42将处理器40连接到存储器模块44a-d、图形处理器46或I/O设备48中的任何一个。图2B所示的共享总线系统包括通过共享总线系统58连接到几个存储器模块54a-c的处理器50。
上述体系结构的任何一种也可用于将多个处理器连接到多个存储器模块。例如,如图3所示,一对处理器60、62通过各自的双向总线系统64连接到各自的存储器模块组66a-e、68a-e。存储器模块66a-e和68a-e的每一个都包括连接到几个存储装置28的存储器集线器24。
如图1和3所示的存储器集线器结构能够提供远远优于其中处理器直接或通过系统或存储器控制器连接到几个存储装置的体系结构的性能。然而,它们仍然受到几种限制。例如,图1所示的体系结构对于处理器14可以存取存储器模块20a-f的方式不提供高度灵活性。例如,如果总线30-38包括32位数据总线,则即使正在从存储器模块20a-f读出、或者正在向存储器模块20a-f写入较少数量的数据位,所有对存储器模块20a-f的存取也都将是32位双字节形式。
图1和3所示体系结构的灵活性也受其它方面的限制。例如,图3所示的体系结构对于处理器60和62分别可以存取存储器模块66a-e和68a-e的方式不提供高度灵活性。虽然处理器60可以存取存储器模块66a-f的任何一个,并且处理器62可以存取存储器模块68a-e的任何一个,但是处理器60不能存取存储器模块68a-e的任何一个,而且处理器62也不能存取存储器模块66a-e的任何一个。结果,如果处理器60向存储器模块66a-e写入充足的数据,从而达到了存储器模块66a-e的存储容量,则即使存储器模块68a-e中可能有大量未使用容量,处理器60也将不能存储任何更多的数据。
图1和3所示存储器体系结构的另一个限制是处理器14、60和62在存取它们各自的存储器模块20、66和68的过程中所引起的较长等待时间。在通过位于存储器模块和处理器之间的任何存储器模块来存取每个存储器模块的范围内,在通过其间的存储器模块来传送地址、数据和控制信号的过程中可以引起大延迟。进一步,如果存储器模块20、66和68的任何一个变得有缺陷,则必须通过该有缺陷的模块进行存取的存储器模块将变得不可用。
因此,需要这样一种存储器系统体系结构,该存储器系统体系结构具有较强容错(fault-intolerant)能力,提供较短等待时间存储器存取,并允许多处理器对于它们存取基于集线器的存储器模块的方式具有高度灵活性。
发明内容
一种存储器系统包括连接到第一级存储器模块的多个存储器请求器。第一级存储器模块的每一个都包括在数量上和存储器请求器数目相对应的第一组存储器端口。第一级中的每个存储器端口都连接到相应的一个存储器请求器。第一级存储器模块进一步包括第二组存储器端口。该存储器系统还包括第二级存储器模块,第二级存储器模块的每一个都具有通过第二组存储器端口连接到第一级中至少一个存储器模块的至少一个存储器端口。第一和第二级中的每个存储器模块都包括多个存储装置、以及连接到存储装置和第一组及任何第二组存储器端口的存储器集线器。存储器集线器优选地包括:连接到模块中相应存储装置的多个存储器控制器;多个链路接口,每个链路接口都连接到存储器请求器之一或另一模块;以及交叉开关,该交叉开关具有连接到相应链路接口的第一多个开关端口、以及连接到相应存储器控制器的多个存储器端口。该交叉开关用于选择性地将每个链路接口连接到任一存储器控制器。
附图说明
图1是包括几个存储器模块的、基于处理器的常规电子系统的框图,其中每个存储器模块都包括连接到几个存储装置的存储器集线器。
图2A和2B所示为用于将存储器模块连接到多个处理器的各种常规体系结构的框图。
图3是包括连接到相应存储器模块组的多个处理器的、基于处理器的常规电子系统的框图,其中每个存储器模块都包括连接到几个存储装置的存储器集线器。
图4是根据本发明一个实施例的、连接到几个存储器模块的基于处理器的系统的框图。
图5是可用于图4和图6的基于处理器的系统中的存储器模块的框图。
图6是根据本发明另一实施例的、连接到几个存储器模块的基于处理器的系统的框图。
具体实施方式
图4示出了根据本发明一个例子的基于处理器的电子系统100。系统100包括三个处理器104、106、108以及DMA(直接存储器存取)装置110,如图形控制器。DMA装置110和处理器104-108的每一个都包括4个存储器存取端口112、114、116和118。端口112-118优选地包括数据端口以及单独或共享控制和地址端口。然而,应该理解,可以使用其它某种存储器端口配置,如用于接收和发送分组的端口。系统100还包括第一级(130)4个存储器模块132、134、136和138,每个存储器模块都包括第一组4个存储器存取端口142、144、146和148。如下所说明的,存储器模块132-138的每一个都包括连接到8个存储装置的存储器集线器,这8个存储装置优选地为DRAM(动态随机存取存储器)装置,并且更为优选地是SDRAM(同步DRAM)装置。然而,应该理解,在存储器模块132-138的每一个中,可以将更多或更少数量的存储装置连接到存储器集线器。
第一处理器104的存储器存取端口112、114、116和118通过相应总线162、164、166和168分别连接到存储器模块132、134、136和138的每一个的存储器存取端口142。类似地,第二处理器106的存储器存取端口112、114、116和118通过相应总线172、174、176和178分别连接到存储器模块132、134、136和138的每一个的存储器存取端口144,并且第三处理器108的存储器存取端口112、114、116和118通过相应总线182、184、186和188分别连接到存储器模块132、134、136和138的每一个的存储器存取端口146。结果,处理器104-108的任何一个都能够存取存储器模块132-138的任何一个。以类似的方式,DMA装置110的存储器存取端口112、114、116和118通过相应总线192、194、196和198分别连接到存储器模块132、134、136和138的存储器存取端口148。因而,DMA装置108也能够存取存储器模块132、134、136和138的每一个。
存储器模块132、134、136和138的每一个也包括第二组4个存储器存取端口202、204、206和208,这第二组4个存储器存取端口202、204、206和208连接到第二级(210)4个存储器模块212、214、216和218。更具体地说,存储器模块132的存储器存取端口202、204、206和208通过相应总线232、234、236和238分别连接到存储器模块212、214、216和218的相应存储器存取端口222。类似地,存储器模块134的存储器存取端口202、204、206和208通过相应总线242、244、246和248分别连接到存储器模块212、214、216和218的每一个的存储器存取端口224,并且存储器模块136的存储器存取端口202、204、206和208通过相应总线252、254、256和258分别连接到存储器模块212、214、216和218的每一个的存储器存取端口226。最后,存储器模块138的存储器存取端口202、204、206和208通过相应总线262、264、266和268分别连接到存储器模块212、214、216和218的每一个的存储器存取端口228。
和第一级130中的存储器模块132-138一样,第二级210中的存储器模块212-218的每一个都包括连接到8个存储装置的存储器集线器。如以下更详细说明的,第一级130的存储器模块132-138中的每一个存储器集线器都包括能够将存储器存取端口112-118的任何一个连接到存储器存取端口202-208的任何一个的交叉开关(图4中未示出)。同样地,第二级210中的存储器模块212-218的每一个中的存储器集线器都能够将存储器存取端口202-208的任何一个连接到存储器存取端口222-228的任何一个。结果,处理器102-106和DMA装置108的任何一个都能够直接存取存储器模块132-138的任何一个,以及通过存储器模块132-138存取存储器模块212-218的任何一个。与利用图1和3所示类型的存储器体系结构可以得到的等待时间相比,处理器102-106与存储器模块132-138和212-218之间、以及DMA装置108与存储器模块132-138和212-218之间的这种紧密接近性导致了较短的等待时间。
图4所示存储器拓扑结构的另外优点是,通过只改变到存储器模块212-218的互连数量,就能够改变处理器102-106或DMA装置108的任何一个与第二级210中的存储器模块212-218的任何一个之间的数据带宽。例如,如果每一条总线都是16位宽,则处理器106可以只利用一条从处理器106延伸到模块132-138之一的总线、以及一条从模块132-138之一延伸到模块212-218之一的总线,来通过16位数据总线连接到存储器模块212-218的任何一个。处理器106可以通过连接到模块132-138中的两个模块、并通过相应总线从这两个模块132-138的每一个连接到模块212-218之一,经由32位数据总线连接到存储器模块212-218的任何一个。处理器106可以通过连接到模块132-138中的三个模块、并通过相应总线从这三个模块132-138的每一个连接到模块212-218之一,经由48位数据总线连接到存储器模块212-218的任何一个。最后,处理器106可以通过连接到所有4个模块132-138、并通过相应总线从这4个模块132-138的每一个连接到模块212-218之一,经由64位数据总线连接到存储器模块212-218的任何一个。
图5示出了可用于图4的存储器模块132-138、212-218中的存储器集线器300的一个实施例。存储器集线器300包括4个链路接口304a-d,这4个链路接口304a-d连接到相应总线,如图4所示第一组中的总线。类似地,4个附加链路接口308a-d被包括进来,它们也连接到相应总线,如图4所示第二组中的总线。所有链路接口304和308都连接到交叉开关310,交叉开关310可以具有常规或以下开发的结构。如前面参考图4所说明的,交叉开关310能够将链路接口304a-d的任何一个连接到链路接口308a-d的任何一个。链路接口304a-d和308a-d可以是单向或双向接口,并且耦合到或耦合自链路接口304a-d和308a-d的存储器存取的性质可以随意变化,包括常规DRAM地址、控制和数据信号、共享地址和控制信号、以及分组存储器存取信号。
交叉开关310也能够将链路接口304a-d和308a-d的任何一个连接到4个DRAM控制器314a-d,每个DRAM控制器都连接到多个DRAM装置(图5中未示出)。DRAM控制器314a-d可以是常规DRAM控制器或以下开发的某种DRAM控制器结构。当然,DRAM控制器314a-d的特定结构和操作将取决于存储器模块中所使用的DRAM装置的性质。交叉开关310将链路接口304a-d连接到DRAM控制器314a-d,以允许多个存储器存取装置的任何一个向连接到控制器314a-d的DRAM装置写数据、或从中读数据,如以上参考图5所说明的。交叉开关310将链路接口308a-d连接到DRAM控制器314a-d,以允许将任何数据从连接到DRAM控制器314a-d的DRAM装置传送到包括存储器集线器300的其它存储器模块,或者将任何数据从包括存储器集线器300的其它存储器模块传送给连接到DRAM控制器314a-d的DRAM装置。
对于由相应DRAM控制器314a-d服务的每个DRAM装置,存储器集线器300还包括高速缓冲存储器320a-d和写缓冲器324a-d。如本领域所周知的,可以是SRAM(静态随机存取存储器)装置的高速缓冲存储器320a-d的每一个都存储由相应DRAM控制器314a-d服务的DRAM装置中所存储的最近或经常存取数据。如果DRAM装置正忙于为读存储器请求服务,或者有其它读请求被挂起,则写缓冲器324a-d积累针对由DRAM控制器314a-d中相应DRAM控制器服务的DRAM装置的写地址和数据。通过这样积累写存储器请求,可以以流水线方式更有效地处理它们,因为不必引起与交替写和读请求关联的延迟。
如上所述,可以将数据从一个包括存储器集线器300的存储器模块传送到另一个包括存储器集线器300的存储器模块。这些模块间数据传送受DMA(直接存储器存取)引擎330控制,DMA引擎330可以具有常规或以下开发的结构。DMA引擎330也可用于在禁止部分有缺陷存储器模块的操作之前,将数据从多个有缺陷存储器模块传送给正确运行的存储器模块。
存储器集线器300一般将包括除图5所示部件以外的部件。然而,为简洁或清楚起见而省略了这些部件。同样,在某些应用中,可以省略图5所示的部件。例如,如果写/读存取翻转可以接受,则可以省略写缓冲器324a-d。同样,虽然图5所示的存储器集线器300包括2组4个链路接口304a-d和308a-d、以及4个DRAM控制器314a-d,但是链路接口组的数目、每一组中链路接口的数目以及DRAM控制器的数目可以随意变化。
图6示出了基于处理器的电子系统350的替换实施例。系统350包括4个存储器请求器352a-d,如处理器或直接存储器存取装置,存储器请求器352a-d的每一个都通过一般以358表示的总线连接到第一级354的4个存储器模块356a-d。从而,用和图4实施例相同的方式来配置存储器模块356a-d。然而,不是象图4实施例那样将第一级354中的每个存储器模块356连接到第二级存储器模块中的每个存储器模块,而是将存储器模块356a-d每一个都连接到第二级360中的相应一组4个存储器模块。从而,第一存储器模块356a连接到4个存储器模块362a-d,第二存储器模块356b连接到4个存储器模块362e-h,第三存储器模块356c连接到4个存储器模块362i-l,以及第四存储器模块356d连接到4个存储器模块362m-p。图6所示拓扑结构比图4所示拓扑结构的有利之处在于,与使用图4所示拓扑结构的第二级210中的存储器模块相比,第二级360的存储器模块362提供更大的存储容量。然而,图6所示存储器拓扑结构的不利之处在于,它提供较小的带宽和较小的存取第二级360中的存储器模块362的灵活性。
由以上应该理解,虽然在此为说明起见而描述了本发明的特定实施例,但是在不背离本发明精神和范围的情况下可以进行各种更改。例如,虽然处理器104-108和DMA装置110被显示为直接连接到存储器模块132-138,但是应该理解,它们可以通过其它装置如总线桥进行连接。同样,图4和图6分别显示的系统100和350正常将包括除所示部件以外的部件。因此,本发明不受除附加权利要求以外的事物的限制。

Claims (45)

1.一种用于将多个存储器请求器的每一个连接到多个存储装置的每一个的存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
第一多个链路接口;以及
具有第一多个开关端口和多个存储器端口的交叉开关,每个所述开关端口都连接到相应的一个所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将每个所述链路接口连接到任何一个所述存储器控制器。
2.根据权利要求1所述的存储器集线器,进一步包括第二多个链路接口,并且其中所述交叉开关进一步包括第二多个开关端口,该第二多个开关端口的每一个都连接到所述第二多个链路接口中的相应的一个链路接口。
3.根据权利要求1所述的存储器集线器,其中每个所述存储器控制器都包括动态随机存取存储器控制器。
4.根据权利要求1所述的存储器集线器,进一步包括与每个所述存储器控制器相关联的相应的高速缓冲存储器装置,每个所述高速缓冲存储器装置都用于存储通过所述交叉开关的相应的一个存储器端口存取的数据。
5.根据权利要求1所述的存储器集线器,其中每个所述链路接口都包括双向链路接口。
6.根据权利要求1所述的存储器集线器,其中每个所述链路接口都包括一对单向链路,该对单向链路之一包括输入端口,并且该对单向链路的另一个包括输出端口。
7.根据权利要求1所述的存储器集线器,进一步包括与每个所述存储器控制器相关联的相应的写缓冲器,每个所述写缓冲器都用于通过所述交叉开关的相应的一个存储器端口接收写数据和关联的写地址,并存储所述写数据和地址以便随后耦合到相应的一个所述存储器控制器。
8.根据权利要求7所述的存储器集线器,其中每个所述写缓冲器为多个写存储器存取积累写数据和地址,然后在没有任何介入读存储器存取的情况下,顺序地将多个写数据和地址耦合到相应的一个所述存储器控制器。
9.根据权利要求1所述的存储器集线器,进一步包括连接到所述交叉开关和所述存储器控制器的直接存储器存取装置,该直接存储器存取装置用于使所述交叉开关和每个所述存储器控制器执行存储器写和读存取。
10.一种存储器模块,包括:
基板;
由所述基板承载的多个存储装置;以及
由所述基板承载的存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
第一多个链路接口,该第一多个链路接口的每一个用于连接到多个存储器请求器的每一个;以及
具有第一多个开关端口和多个存储器端口的交叉开关,每个所述开关端口都连接到相应的一个所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将每个所述链路接口连接到任何一个所述存储器控制器。
11.根据权利要求10所述的存储器模块,其中所述存储器集线器进一步包括第二多个链路接口,并且其中所述交叉开关进一步包括第二多个开关端口,该第二多个开关端口的每一个都连接到所述第二多个链路接口中的相应的一个链路接口。
12.根据权利要求10所述的存储器模块,其中每个所述存储装置都包括动态随机存取存储器装置。
13.根据权利要求10所述的存储器模块,其中所述存储器集线器进一步包括与每个所述存储器控制器相关联的相应的高速缓冲存储器装置,每个所述高速缓冲存储器装置都用于存储通过所述交叉开关的相应的一个存储器端口存取的数据。
14.根据权利要求10所述的存储器模块,其中所述基板包括半导体基板,并且其中所述存储装置、链路接口、存储器控制器和交叉开关被制造为所述半导体基板上的公共集成电路。
15.根据权利要求10所述的存储器模块,其中所述存储器集线器中的每个链路接口都包括双向链路接口。
16.根据权利要求10所述的存储器模块,其中所述存储器集线器中的每个链路接口都包括一对单向链路,该对单向链路之一包括输入端口,并且该对单向链路的另一个包括输出端口。
17.根据权利要求10所述的存储器模块,其中所述存储器集线器进一步包括与每个所述存储器控制器相关联的相应的写缓冲器,每个所述写缓冲器都用于通过所述交叉开关的相应的一个存储器端口接收写数据和关联的写地址,并存储所述写数据和地址以便随后耦合到相应的一个所述存储器控制器。
18.根据权利要求17所述的存储器模块,其中每个所述写缓冲器为多个写存储器存取积累写数据和地址,然后在没有任何介入读存储器存取的情况下,顺序地将多个写数据和地址耦合到相应的一个所述存储器控制器。
19.根据权利要求10所述的存储器模块,其中所述存储器集线器进一步包括连接到所述交叉开关和所述存储器控制器的直接存储器存取装置,该直接存储器存取装置用于使所述交叉开关和每个所述存储器控制器执行存储器写和读存取。
20.一种存储器系统,包括:
多个存储器请求器;
连接到所述存储器请求器的第一级存储器模块,该第一级中的每个存储器模块都连接到多个所述存储器请求器,每个所述存储器模块包括:
多个存储装置;以及
存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
第一多个链路接口,该第一多个链路接口的每一个都连接到相应的一个所述存储器请求器;以及
具有第一多个开关端口和多个存储器端口的交叉开关,每个所述开关端口都连接到相应的一个所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将每个所述链路接口连接到任何一个所述存储器控制器。
21.根据权利要求20所述的存储器系统,其中所述存储器集线器进一步包括第二多个链路接口,并且其中所述交叉开关进一步包括第二多个开关端口,该第二多个开关端口的每一个都连接到所述第二多个链路接口中的相应的一个链路接口。
22.根据权利要求20所述的存储器系统,其中每个所述存储装置都包括动态随机存取存储器装置。
23.根据权利要求20所述的存储器系统,其中所述存储器集线器进一步包括与每个所述存储器控制器相关联的相应的高速缓冲存储器装置,每个所述高速缓冲存储器装置都用于存储通过所述交叉开关的相应的一个存储器端口存取的数据。
24.根据权利要求20所述的存储器系统,其中基板包括半导体基板,并且其中所述存储装置、链路接口、存储器控制器和交叉开关被制造为所述半导体基板上的公共集成电路。
25.根据权利要求20所述的存储器系统,其中所述存储器集线器中的每个链路接口都包括双向链路接口。
26.根据权利要求20所述的存储器系统,其中所述存储器集线器中的每个所述链路接口都包括一对单向链路,该对单向链路之一包括输入端口,并且该对单向链路的另一个包括输出端口。
27.根据权利要求20所述的存储器系统,其中所述存储器集线器进一步包括与每个所述存储器控制器相关联的相应的写缓冲器,每个所述写缓冲器都用于通过所述交叉开关的相应的一个存储器端口接收写数据和关联的写地址,并存储所述写数据和地址以便随后耦合到相应的一个所述存储器控制器。
28.根据权利要求27所述的存储器系统,其中每个所述写缓冲器为多个写存储器存取积累写数据和地址,然后在没有任何介入读存储器存取的情况下,顺序地将多个写数据和地址耦合到相应的一个所述存储器控制器。
29.根据权利要求20所述的存储器系统,其中所述存储器集线器进一步包括连接到所述交叉开关和所述存储器控制器的直接存储器存取装置,该直接存储器存取装置用于使所述交叉开关和每个所述存储器控制器执行存储器写和读存取。
30.根据权利要求20所述的存储器系统,其中至少一些所述存储器请求器包括处理器。
31.根据权利要求20所述的存储器系统,其中至少一些所述存储器请求器包括直接存储器存取装置。
32.根据权利要求20所述的存储器系统,进一步包括连接到所述第一级的多个存储器模块的第二级存储器模块,该第二级的每个存储器模块都包括:
多个存储装置;以及
存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
第一多个链路接口,该第一多个链路接口的每一个都连接到所述第一级中的相应的一个存储器模块;以及
具有第一多个开关端口和多个存储器端口的交叉开关,每个所述开关端口都连接到相应的一个所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将每个所述链路接口连接到任何一个所述存储器控制器。
33.根据权利要求20所述的存储器系统,进一步包括第二级中的多组存储器模块,该第二级中存储器模块组的数目在数量上对应于所述第一级的存储器模块的数目,所述第二级中的每组存储器模块都连接到所述第一级中的相应的一个存储器模块,所述第二级中的每个存储器模块都包括:
多个存储装置;以及
存储器集线器,该存储器集线器包括:
多个存储器控制器,该多个存储器控制器的每一个都连接到至少一个所述存储装置;
链路接口,该链路接口连接到所述第二级中相应的一组存储器模块所对应的所述第一级的存储器模块;以及
具有开关端口和多个存储器端口的交叉开关,所述开关端口连接到所述链路接口,并且每个所述存储器端口都连接到相应的一个所述存储器控制器,所述交叉开关用于选择性地将所述链路接口连接到任何一个所述存储器控制器。
34.根据权利要求20所述的存储器系统,其中所述存储装置、链路接口、存储器控制器和交叉开关被制造为半导体基板上的公共集成电路。
35.一种存储器系统,包括:
多个存储器请求器;
连接到所述存储器请求器的第一级存储器模块,该第一级存储器模块的每一个都包括在数量上和所述存储器请求器的数目相对应的第一组存储器端口,所述第一级中的每个存储器端口都连接到相应的一个所述存储器请求器,所述第一级存储器模块进一步包括第二组存储器端口,所述第一级中的每个存储器模块都包括多个存储装置以及连接到所述存储装置和所述第一及其第二组存储器端口的存储器集线器;
第二级存储器模块,该第二级存储器模块的每一个都包括通过所述第二组存储器端口连接到所述第一级的存储器模块的至少一个存储器端口,所述第二级中的每个存储器模块都包括多个存储装置以及连接到所述存储装置和所述至少一个存储器端口的存储器集线器。
36.根据权利要求35所述的存储器系统,其中所述第二级中的每一个存储器模块都包括在数量上和所述第一级的存储器模块的数目相对应的多个存储器端口,所述第二级的每个存储器模块中的存储器端口都通过所述第二组中的相应的存储器端口连接到所述第一级存储器模块。
37.根据权利要求35所述的存储器系统,其中所述第二级中的多组存储器模块的每一组都连接到所述第一级中的相应的一个存储器模块,所述第一级中的每一个存储器模块都包括连接到所述第二级的相应的一组存储器模块所对应的所述第一级的存储器模块的存储器端口。
38.根据权利要求35所述的存储器系统,其中所述第一级中的每个存储器模块中的存储器集线器都包括交叉开关,所述交叉开关用于将所述第一组存储器端口的任何一个连接到所述第二组存储器端口的任何一个和任何一个所述存储装置。
39.根据权利要求38所述的存储器系统,其中所述交叉开关进一步用于将所述第二组存储器端口的任何一个连接到任何一个所述存储装置。
40.一种用于从多个存储器请求端口存取存储装置的方法,该方法包括:
设置第一级中的第一多个存储器模块,该第一级中的每个存储器模块都包括多个存储装置;
设置第二级中的第二多个存储器模块,该第二级中的每个存储器模块都包括多个存储装置;
从任一所述存储器请求端口存取所述第一级中的每个存储器模块;以及
通过所述第一级中的至少一个存储器模块,从任一所述存储器请求端口来存取所述第二级中的每个存储器模块。
41.根据权利要求40所述的方法,其中通过所述第一级中的至少一个存储器模块来存取所述第二级中每个存储器模块的处理包括:通过所述第一级中的每个存储器模块来存取所述第二级中的每个存储器模块。
42.根据权利要求40所述的方法,其中通过所述第一级中的至少一个存储器模块来存取所述第二级中每个存储器模块的处理包括:通过与所述第二级中的一组存储器模块相对应的所述第一级的存储器模块来存取所述第二级中的一组存储器模块。
43.根据权利要求40所述的方法,进一步包括从所述第二级中的至少一些存储器模块来存取所述第一级中的每一个存储器模块。
44.根据权利要求40所述的方法,其中通过所述第一级中的至少一个存储器模块,从任一所述存储器请求端口来存取所述第二级中每个存储器模块的处理包括:改变借以从所述存储器请求端口之一存取所述第二级存储器模块的所述第一级存储器模块的数目,以改变所述存储器请求端口和正在存取的所述第二级存储器模块之间的数据带宽。
45.根据权利要求40所述的方法,进一步包括在至少一些所述存储器模块中积累写存储器存取,并顺序地执行所存储的写存储器存取。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236540B (zh) * 2007-01-29 2011-07-20 国际商业机器公司 选择预取模式的方法、集线器器件、存储器系统及子系统
CN102792288A (zh) * 2009-12-23 2012-11-21 提琴存储器公司 可配置的互连系统
CN106055495A (zh) * 2015-04-14 2016-10-26 三星电子株式会社 用于控制半导体装置的方法
CN112840401A (zh) * 2018-10-16 2021-05-25 美光科技公司 存储器装置处理

Families Citing this family (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7149874B2 (en) * 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US7133991B2 (en) * 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US7136958B2 (en) * 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7788451B2 (en) 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7257683B2 (en) * 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US7447240B2 (en) * 2004-03-29 2008-11-04 Micron Technology, Inc. Method and system for synchronizing communications links in a hub-based memory system
US6980042B2 (en) 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7363419B2 (en) 2004-05-28 2008-04-22 Micron Technology, Inc. Method and system for terminating write commands in a hub-based memory system
US20060036826A1 (en) * 2004-07-30 2006-02-16 International Business Machines Corporation System, method and storage medium for providing a bus speed multiplier
US7389375B2 (en) * 2004-07-30 2008-06-17 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
US7296129B2 (en) 2004-07-30 2007-11-13 International Business Machines Corporation System, method and storage medium for providing a serialized memory interface with a bus repeater
US7224595B2 (en) 2004-07-30 2007-05-29 International Business Machines Corporation 276-Pin buffered memory module with enhanced fault tolerance
US7331010B2 (en) 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
US7441060B2 (en) * 2004-10-29 2008-10-21 International Business Machines Corporation System, method and storage medium for providing a service interface to a memory system
US7299313B2 (en) 2004-10-29 2007-11-20 International Business Machines Corporation System, method and storage medium for a memory subsystem command interface
US7277988B2 (en) * 2004-10-29 2007-10-02 International Business Machines Corporation System, method and storage medium for providing data caching and data compression in a memory subsystem
US7305574B2 (en) * 2004-10-29 2007-12-04 International Business Machines Corporation System, method and storage medium for bus calibration in a memory subsystem
US7512762B2 (en) * 2004-10-29 2009-03-31 International Business Machines Corporation System, method and storage medium for a memory subsystem with positional read data latency
US7478259B2 (en) 2005-10-31 2009-01-13 International Business Machines Corporation System, method and storage medium for deriving clocks in a memory system
US7685392B2 (en) 2005-11-28 2010-03-23 International Business Machines Corporation Providing indeterminate read data latency in a memory system
DE102006006571A1 (de) * 2006-02-13 2007-08-16 Infineon Technologies Ag Halbleiteranordnung und Verfahren zum Betreiben einer Halbleiteranordnung
US7640386B2 (en) * 2006-05-24 2009-12-29 International Business Machines Corporation Systems and methods for providing memory modules with multiple hub devices
US7769942B2 (en) * 2006-07-27 2010-08-03 Rambus, Inc. Cross-threaded memory system
US7493439B2 (en) * 2006-08-01 2009-02-17 International Business Machines Corporation Systems and methods for providing performance monitoring in a memory system
US7669086B2 (en) 2006-08-02 2010-02-23 International Business Machines Corporation Systems and methods for providing collision detection in a memory system
US7587559B2 (en) * 2006-08-10 2009-09-08 International Business Machines Corporation Systems and methods for memory module power management
US7594207B2 (en) * 2006-09-13 2009-09-22 Cadence Design Systems, Inc. Computationally efficient design rule checking for circuit interconnect routing design
US7870459B2 (en) 2006-10-23 2011-01-11 International Business Machines Corporation High density high reliability memory module with power gating and a fault tolerant address and command bus
US7721140B2 (en) * 2007-01-02 2010-05-18 International Business Machines Corporation Systems and methods for improving serviceability of a memory system
US7969445B2 (en) * 2007-06-20 2011-06-28 Nvidia Corporation System, method, and computer program product for broadcasting write operations
US7996641B2 (en) * 2007-06-27 2011-08-09 International Business Machines Corporation Structure for hub for supporting high capacity memory subsystem
US7921271B2 (en) * 2007-06-27 2011-04-05 International Business Machines Corporation Hub for supporting high capacity memory subsystem
US8037270B2 (en) * 2007-06-27 2011-10-11 International Business Machines Corporation Structure for memory chip for high capacity memory subsystem supporting replication of command data
US20090006774A1 (en) * 2007-06-27 2009-01-01 Gerald Keith Bartley High Capacity Memory Subsystem Architecture Employing Multiple-Speed Bus
US7809913B2 (en) * 2007-06-27 2010-10-05 International Business Machines Corporation Memory chip for high capacity memory subsystem supporting multiple speed bus
US8037272B2 (en) * 2007-06-27 2011-10-11 International Business Machines Corporation Structure for memory chip for high capacity memory subsystem supporting multiple speed bus
US7818512B2 (en) * 2007-06-27 2010-10-19 International Business Machines Corporation High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules
US8019949B2 (en) * 2007-06-27 2011-09-13 International Business Machines Corporation High capacity memory subsystem architecture storing interleaved data for reduced bus speed
US8037258B2 (en) * 2007-06-27 2011-10-11 International Business Machines Corporation Structure for dual-mode memory chip for high capacity memory subsystem
US7822936B2 (en) * 2007-06-27 2010-10-26 International Business Machines Corporation Memory chip for high capacity memory subsystem supporting replication of command data
US7921264B2 (en) * 2007-06-27 2011-04-05 International Business Machines Corporation Dual-mode memory chip for high capacity memory subsystem
US8086936B2 (en) * 2007-08-31 2011-12-27 International Business Machines Corporation Performing error correction at a memory device level that is transparent to a memory channel
US7840748B2 (en) * 2007-08-31 2010-11-23 International Business Machines Corporation Buffered memory module with multiple memory device data interface ports supporting double the memory capacity
US7899983B2 (en) * 2007-08-31 2011-03-01 International Business Machines Corporation Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module
US7861014B2 (en) * 2007-08-31 2010-12-28 International Business Machines Corporation System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel
US7865674B2 (en) * 2007-08-31 2011-01-04 International Business Machines Corporation System for enhancing the memory bandwidth available through a memory module
US7818497B2 (en) * 2007-08-31 2010-10-19 International Business Machines Corporation Buffered memory module supporting two independent memory channels
US8082482B2 (en) * 2007-08-31 2011-12-20 International Business Machines Corporation System for performing error correction operations in a memory hub device of a memory module
US20100269021A1 (en) * 2007-09-05 2010-10-21 Gower Kevin C Method for Performing Error Correction Operations in a Memory Hub Device of a Memory Module
US8019919B2 (en) * 2007-09-05 2011-09-13 International Business Machines Corporation Method for enhancing the memory bandwidth available through a memory module
US7930470B2 (en) * 2008-01-24 2011-04-19 International Business Machines Corporation System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller
US8140936B2 (en) * 2008-01-24 2012-03-20 International Business Machines Corporation System for a combined error correction code and cyclic redundancy check code for a memory channel
US7925825B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to support a full asynchronous interface within a memory hub device
US7925826B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency
US7930469B2 (en) * 2008-01-24 2011-04-19 International Business Machines Corporation System to provide memory system power reduction without reducing overall memory system performance
US7925824B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency
US7770077B2 (en) * 2008-01-24 2010-08-03 International Business Machines Corporation Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
US8154901B1 (en) * 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US8621159B2 (en) 2009-02-11 2013-12-31 Rambus Inc. Shared access memory scheme
US20100241783A1 (en) * 2009-03-23 2010-09-23 Honeywell International Inc. Memory node for use within a data storage system having a plurality of interconnected memory nodes
US9361955B2 (en) 2010-01-28 2016-06-07 Hewlett Packard Enterprise Development Lp Memory access methods and apparatus
US8938589B2 (en) 2010-01-28 2015-01-20 Hewlett-Packard Development Company, L. P. Interface methods and apparatus for memory devices using arbitration
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
US9432298B1 (en) 2011-12-09 2016-08-30 P4tents1, LLC System, method, and computer program product for improving memory systems
US8996822B2 (en) * 2011-07-29 2015-03-31 Micron Technology, Inc. Multi-device memory serial architecture
US9146867B2 (en) 2011-10-31 2015-09-29 Hewlett-Packard Development Company, L.P. Methods and apparatus to access memory using runtime characteristics
US9171846B2 (en) 2012-05-31 2015-10-27 Moon J. Kim Leakage and performance graded memory
EP2887223A4 (en) * 2012-10-12 2015-08-19 Huawei Tech Co Ltd MEMORY SYSTEM, MEMORY MODULE, METHOD OF ACCESSING MEMORY MODULE, AND COMPUTER SYSTEM
US20160124872A1 (en) * 2013-12-12 2016-05-05 Samsung Electronics Co., Ltd. Disaggregated memory appliance
US10254987B2 (en) * 2013-12-12 2019-04-09 Samsung Electronics Co., Ltd. Disaggregated memory appliance having a management processor that accepts request from a plurality of hosts for management, configuration and provisioning of memory
KR102353930B1 (ko) * 2013-12-12 2022-01-20 삼성전자주식회사 분리된 메모리 기기
US9558143B2 (en) * 2014-05-09 2017-01-31 Micron Technology, Inc. Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device
KR102365111B1 (ko) 2014-07-07 2022-02-18 삼성전자주식회사 메모리 모듈 세트, 이를 포함한 반도체 메모리 장치 및 반도체 메모리 시스템
US20160179387A1 (en) * 2014-12-19 2016-06-23 Jayesh Gaur Instruction and Logic for Managing Cumulative System Bandwidth through Dynamic Request Partitioning
CN110101590A (zh) 2015-10-08 2019-08-09 知识产权全资有限公司 用于处理头发的方法及其试剂盒
US9697884B2 (en) 2015-10-08 2017-07-04 Rambus Inc. Variable width memory module supporting enhanced error detection and correction
US10679722B2 (en) 2016-08-26 2020-06-09 Sandisk Technologies Llc Storage system with several integrated components and method for use therewith
US11487445B2 (en) * 2016-11-22 2022-11-01 Intel Corporation Programmable integrated circuit with stacked memory die for storing configuration data
US20180150256A1 (en) 2016-11-29 2018-05-31 Intel Corporation Technologies for data deduplication in disaggregated architectures
EP3549350A4 (en) 2016-11-29 2021-03-24 Intel Corporation MILLIMETRIC WAVE CHASSIS INTERCONNECTION TECHNOLOGIES
US10922258B2 (en) * 2017-12-22 2021-02-16 Alibaba Group Holding Limited Centralized-distributed mixed organization of shared memory for neural network processing
US11403035B2 (en) * 2018-12-19 2022-08-02 Micron Technology, Inc. Memory module including a controller and interfaces for communicating with a host and another memory module
US20210209035A1 (en) * 2020-12-26 2021-07-08 Intel Corporation Memory accesses using a memory hub

Family Cites Families (275)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US43426A (en) * 1864-07-05 Improvement in sewing
US112119A (en) * 1871-02-28 Improvement in self-centering chucks for lathes
US229770A (en) * 1880-07-06 Hand-truck
US3742253A (en) * 1971-03-15 1973-06-26 Burroughs Corp Three state logic device with applications
US4078228A (en) 1975-03-24 1978-03-07 Ohkura Electric Co., Ltd. Loop data highway communication system
US4045781A (en) 1976-02-13 1977-08-30 Digital Equipment Corporation Memory module with selectable byte addressing for digital data processing system
US4253144A (en) 1978-12-21 1981-02-24 Burroughs Corporation Multi-processor communication network
US4245306A (en) 1978-12-21 1981-01-13 Burroughs Corporation Selection of addressed processor in a multi-processor network
US4253146A (en) 1978-12-21 1981-02-24 Burroughs Corporation Module for coupling computer-processors
US4240143A (en) 1978-12-22 1980-12-16 Burroughs Corporation Hierarchical multi-processor network for memory sharing
US4608702A (en) 1984-12-21 1986-08-26 Advanced Micro Devices, Inc. Method for digital clock recovery from Manchester-encoded signals
US4724520A (en) 1985-07-01 1988-02-09 United Technologies Corporation Modular multiport data hub
US4843263A (en) 1986-01-10 1989-06-27 Nec Corporation Clock timing controller for a plurality of LSI chips
US4707823A (en) 1986-07-21 1987-11-17 Chrysler Motors Corporation Fiber optic multiplexed data acquisition system
US4831520A (en) * 1987-02-24 1989-05-16 Digital Equipment Corporation Bus interface circuit for digital data processor
JPH07117863B2 (ja) 1987-06-26 1995-12-18 株式会社日立製作所 オンラインシステムの再立上げ方式
US4891808A (en) 1987-12-24 1990-01-02 Coherent Communication Systems Corp. Self-synchronizing multiplexer
US5251303A (en) 1989-01-13 1993-10-05 International Business Machines Corporation System for DMA block data transfer based on linked control blocks
US5442770A (en) 1989-01-24 1995-08-15 Nec Electronics, Inc. Triple port cache memory
US4953930A (en) 1989-03-15 1990-09-04 Ramtech, Inc. CPU socket supporting socket-to-socket optical communications
KR920701894A (ko) 1989-04-28 1992-08-12 브루스 마르쿠스 컴퓨터 소프트웨어의 원격 제어 장치 및 그 보호 방법
US4982185A (en) 1989-05-17 1991-01-01 Blh Electronics, Inc. System for synchronous measurement in a digital computer network
JPH03156795A (ja) 1989-11-15 1991-07-04 Toshiba Micro Electron Kk 半導体メモリ回路装置
US5317752A (en) 1989-12-22 1994-05-31 Tandem Computers Incorporated Fault-tolerant computer system with auto-restart after power-fall
US5313590A (en) * 1990-01-05 1994-05-17 Maspar Computer Corporation System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer
JP2772103B2 (ja) 1990-03-28 1998-07-02 株式会社東芝 計算機システム立上げ方式
US5243703A (en) 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
BE1004668A3 (nl) 1991-04-02 1993-01-05 Bell Telephone Mfg Beschermingsinrichting voor een optische zender/ontvangerinrichting.
US5663901A (en) 1991-04-11 1997-09-02 Sandisk Corporation Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
US5461627A (en) 1991-12-24 1995-10-24 Rypinski; Chandos A. Access protocol for a common channel wireless network
JP2554816B2 (ja) 1992-02-20 1996-11-20 株式会社東芝 半導体記憶装置
US5355391A (en) 1992-03-06 1994-10-11 Rambus, Inc. High speed bus system
JP3517237B2 (ja) 1992-03-06 2004-04-12 ラムバス・インコーポレーテッド 同期バス・システムおよびそのためのメモリ装置
WO1993019422A1 (en) 1992-03-25 1993-09-30 Encore Computer U.S., Inc. Fiber optic memory coupling system
US5432907A (en) 1992-05-12 1995-07-11 Network Resources Corporation Network hub with integrated bridge
US5270964A (en) 1992-05-19 1993-12-14 Sun Microsystems, Inc. Single in-line memory module
GB2270780A (en) 1992-09-21 1994-03-23 Ibm Scatter-gather in data processing systems.
JPH0713945A (ja) 1993-06-16 1995-01-17 Nippon Sheet Glass Co Ltd 演算処理部および制御・記憶部分離型マルチプロセッサ ・システムのバス構造
US5497494A (en) 1993-07-23 1996-03-05 International Business Machines Corporation Method for saving and restoring the state of a CPU executing code in protected mode
US5729709A (en) 1993-11-12 1998-03-17 Intel Corporation Memory controller with burst addressing circuit
US5502621A (en) 1994-03-31 1996-03-26 Hewlett-Packard Company Mirrored pin assignment for two sided multi-chip layout
US5566325A (en) 1994-06-30 1996-10-15 Digital Equipment Corporation Method and apparatus for adaptive memory access
US6175571B1 (en) 1994-07-22 2001-01-16 Network Peripherals, Inc. Distributed memory switching hub
US5978567A (en) 1994-07-27 1999-11-02 Instant Video Technologies Inc. System for distribution of interactive multimedia and linear programs by enabling program webs which include control scripts to define presentation by client transceiver
US5801973A (en) 1994-07-29 1998-09-01 Discovision Associates Video decompression
US5553070A (en) 1994-09-13 1996-09-03 Riley; Robert E. Data link module for time division multiplexing control systems
JPH08123717A (ja) * 1994-10-25 1996-05-17 Oki Electric Ind Co Ltd 半導体記憶装置
US6804760B2 (en) 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5715456A (en) 1995-02-13 1998-02-03 International Business Machines Corporation Method and apparatus for booting a computer system without pre-installing an operating system
US5638534A (en) 1995-03-31 1997-06-10 Samsung Electronics Co., Ltd. Memory controller which executes read and write commands out of order
US5875352A (en) 1995-11-03 1999-02-23 Sun Microsystems, Inc. Method and apparatus for multiple channel direct memory access control
US5796413A (en) 1995-12-06 1998-08-18 Compaq Computer Corporation Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering
US5834956A (en) 1995-12-29 1998-11-10 Intel Corporation Core clock correction in a 2/N mode clocking scheme
US7681005B1 (en) 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
US5966724A (en) 1996-01-11 1999-10-12 Micron Technology, Inc. Synchronous memory device with dual page and burst mode operations
US5710733A (en) 1996-01-22 1998-01-20 Silicon Graphics, Inc. Processor-inclusive memory module
US5832250A (en) 1996-01-26 1998-11-03 Unisys Corporation Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits
US5819304A (en) 1996-01-29 1998-10-06 Iowa State University Research Foundation, Inc. Random access memory assembly
US5659798A (en) 1996-02-02 1997-08-19 Blumrich; Matthias Augustin Method and system for initiating and loading DMA controller registers by using user-level programs
US5687325A (en) * 1996-04-19 1997-11-11 Chang; Web Application specific field programmable gate array
US6064706A (en) 1996-05-01 2000-05-16 Alcatel Usa, Inc. Apparatus and method of desynchronizing synchronously mapped asynchronous data
US5818844A (en) 1996-06-06 1998-10-06 Advanced Micro Devices, Inc. Address generation and data path arbitration to and from SRAM to accommodate multiple transmitted packets
US5875454A (en) 1996-07-24 1999-02-23 International Business Machiness Corporation Compressed data cache storage system
JPH1049511A (ja) 1996-08-02 1998-02-20 Oki Electric Ind Co Ltd 1チップマイクロコンピュータ
JP4070255B2 (ja) 1996-08-13 2008-04-02 富士通株式会社 半導体集積回路
TW304288B (en) 1996-08-16 1997-05-01 United Microelectronics Corp Manufacturing method of semiconductor memory device with capacitor
US5706224A (en) 1996-10-10 1998-01-06 Quality Semiconductor, Inc. Content addressable memory and random access memory partition circuit
US6272600B1 (en) 1996-11-15 2001-08-07 Hyundai Electronics America Memory request reordering in a data processing system
US6167486A (en) 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US5887159A (en) 1996-12-11 1999-03-23 Digital Equipment Corporation Dynamically determining instruction hint fields
EP0849685A3 (en) 1996-12-19 2000-09-06 Texas Instruments Incorporated Communication bus system between processors and memory modules
US6308248B1 (en) 1996-12-31 2001-10-23 Compaq Computer Corporation Method and system for allocating memory space using mapping controller, page table and frame numbers
US6031241A (en) 1997-03-11 2000-02-29 University Of Central Florida Capillary discharge extreme ultraviolet lamp source for EUV microlithography and other related applications
US6271582B1 (en) 1997-04-07 2001-08-07 Micron Technology, Inc. Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die
KR100202385B1 (ko) 1997-06-04 1999-06-15 윤종용 Hdlc를 이용한 반이중 통신용 송신 장치
US6092158A (en) 1997-06-13 2000-07-18 Intel Corporation Method and apparatus for arbitrating between command streams
US6044429A (en) 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
US6243769B1 (en) 1997-07-18 2001-06-05 Micron Technology, Inc. Dynamic buffer allocation for a computer system
US6073190A (en) 1997-07-18 2000-06-06 Micron Electronics, Inc. System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair
US6760833B1 (en) 1997-08-01 2004-07-06 Micron Technology, Inc. Split embedded DRAM processor
US6105075A (en) 1997-08-05 2000-08-15 Adaptec, Inc. Scatter gather memory system for a hardware accelerated command interpreter engine
US6137780A (en) 1997-08-07 2000-10-24 At&T Corp Apparatus and method to monitor communication system status
JP4014708B2 (ja) 1997-08-21 2007-11-28 株式会社ルネサステクノロジ 半導体集積回路装置の設計方法
US6128703A (en) 1997-09-05 2000-10-03 Integrated Device Technology, Inc. Method and apparatus for memory prefetch operation of volatile non-coherent data
US6249802B1 (en) 1997-09-19 2001-06-19 Silicon Graphics, Inc. Method, system, and computer program product for allocating physical memory in a distributed shared memory network
US6185676B1 (en) 1997-09-30 2001-02-06 Intel Corporation Method and apparatus for performing early branch prediction in a microprocessor
US6223301B1 (en) 1997-09-30 2001-04-24 Compaq Computer Corporation Fault tolerant memory
US6473439B1 (en) * 1997-10-10 2002-10-29 Rambus Incorporated Method and apparatus for fail-safe resynchronization with minimum latency
JPH11120120A (ja) 1997-10-13 1999-04-30 Fujitsu Ltd カードバス用インターフェース回路及びそれを有するカードバス用pcカード
FR2770008B1 (fr) 1997-10-16 2001-10-12 Alsthom Cge Alkatel Dispositif de communication entre plusieurs processeurs
US5987196A (en) 1997-11-06 1999-11-16 Micron Technology, Inc. Semiconductor structure having an optical signal path in a substrate and method for forming the same
US6098158A (en) 1997-12-18 2000-08-01 International Business Machines Corporation Software-enabled fast boot
US6014721A (en) 1998-01-07 2000-01-11 International Business Machines Corporation Method and system for transferring data between buses having differing ordering policies
US6023726A (en) 1998-01-20 2000-02-08 Netscape Communications Corporation User configurable prefetch control system for enabling client to prefetch documents from a network server
US6721860B2 (en) * 1998-01-29 2004-04-13 Micron Technology, Inc. Method for bus capacitance reduction
GB2333896B (en) * 1998-01-31 2003-04-09 Mitel Semiconductor Ab Vertical cavity surface emitting laser
US6742098B1 (en) 2000-10-03 2004-05-25 Intel Corporation Dual-port buffer-to-memory interface
US7024518B2 (en) 1998-02-13 2006-04-04 Intel Corporation Dual-port buffer-to-memory interface
US6186400B1 (en) 1998-03-20 2001-02-13 Symbol Technologies, Inc. Bar code reader with an integrated scanning component module mountable on printed circuit board
US6038630A (en) * 1998-03-24 2000-03-14 International Business Machines Corporation Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses
US6079008A (en) 1998-04-03 2000-06-20 Patton Electronics Co. Multiple thread multiple data predictive coded parallel processing system and method
US6247107B1 (en) 1998-04-06 2001-06-12 Advanced Micro Devices, Inc. Chipset configured to perform data-directed prefetching
JPH11316617A (ja) 1998-05-01 1999-11-16 Mitsubishi Electric Corp 半導体回路装置
KR100283243B1 (ko) 1998-05-11 2001-03-02 구자홍 운영체제의 부팅방법
US6167465A (en) 1998-05-20 2000-12-26 Aureal Semiconductor, Inc. System for managing multiple DMA connections between a peripheral device and a memory and performing real-time operations on data carried by a selected DMA connection
SG75958A1 (en) 1998-06-01 2000-10-24 Hitachi Ulsi Sys Co Ltd Semiconductor device and a method of producing semiconductor device
US6405280B1 (en) * 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US6301637B1 (en) 1998-06-08 2001-10-09 Storage Technology Corporation High performance data paths
US6134624A (en) 1998-06-08 2000-10-17 Storage Technology Corporation High bandwidth cache system
US6067649A (en) * 1998-06-10 2000-05-23 Compaq Computer Corporation Method and apparatus for a low power self test of a memory subsystem
US6453377B1 (en) * 1998-06-16 2002-09-17 Micron Technology, Inc. Computer including optical interconnect, memory unit, and method of assembling a computer
US6289068B1 (en) 1998-06-22 2001-09-11 Xilinx, Inc. Delay lock loop with clock phase shifter
JP2000011640A (ja) 1998-06-23 2000-01-14 Nec Corp 半導体記憶装置
FR2780535B1 (fr) * 1998-06-25 2000-08-25 Inst Nat Rech Inf Automat Dispositif de traitement de donnees d'acquisition, notamment de donnees d'image
JP3178423B2 (ja) 1998-07-03 2001-06-18 日本電気株式会社 バーチャルチャネルsdram
US7346063B1 (en) * 1998-07-08 2008-03-18 Broadcom Corporation Memory management unit for a network switch
US6286083B1 (en) 1998-07-08 2001-09-04 Compaq Computer Corporation Computer system with adaptive memory arbitration scheme
JP3248617B2 (ja) * 1998-07-14 2002-01-21 日本電気株式会社 半導体記憶装置
US6272609B1 (en) 1998-07-31 2001-08-07 Micron Electronics, Inc. Pipelined memory controller
US6061296A (en) 1998-08-17 2000-05-09 Vanguard International Semiconductor Corporation Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices
US6029250A (en) 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6587912B2 (en) 1998-09-30 2003-07-01 Intel Corporation Method and apparatus for implementing multiple memory buses on a memory module
US6622188B1 (en) 1998-09-30 2003-09-16 International Business Machines Corporation 12C bus expansion apparatus and method therefor
US6910109B2 (en) * 1998-09-30 2005-06-21 Intel Corporation Tracking memory page state
US6243831B1 (en) 1998-10-31 2001-06-05 Compaq Computer Corporation Computer system with power loss protection mechanism
JP3248500B2 (ja) 1998-11-12 2002-01-21 日本電気株式会社 半導体記憶装置およびそのデータ読み出し方法
US6434639B1 (en) 1998-11-13 2002-08-13 Intel Corporation System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation
US6438622B1 (en) 1998-11-17 2002-08-20 Intel Corporation Multiprocessor system including a docking system
US6100735A (en) 1998-11-19 2000-08-08 Centillium Communications, Inc. Segmented dual delay-locked loop for precise variable-phase clock generation
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6463059B1 (en) 1998-12-04 2002-10-08 Koninklijke Philips Electronics N.V. Direct memory access execution engine with indirect addressing of circular queues in addition to direct memory addressing
US6349363B2 (en) 1998-12-08 2002-02-19 Intel Corporation Multi-section cache with different attributes for each section
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6067262A (en) 1998-12-11 2000-05-23 Lsi Logic Corporation Redundancy analysis for embedded memories with built-in self test and built-in self repair
FR2787600B1 (fr) 1998-12-17 2001-11-16 St Microelectronics Sa Memoire tampon associee a plusieurs canaux de communication de donnees
US6487556B1 (en) * 1998-12-18 2002-11-26 International Business Machines Corporation Method and system for providing an associative datastore within a data processing system
US6191663B1 (en) 1998-12-22 2001-02-20 Intel Corporation Echo reduction on bit-serial, multi-drop bus
US6367074B1 (en) * 1998-12-28 2002-04-02 Intel Corporation Operation of a system
US6598154B1 (en) 1998-12-29 2003-07-22 Intel Corporation Precoding branch instructions to reduce branch-penalty in pipelined processors
US6061263A (en) 1998-12-29 2000-05-09 Intel Corporation Small outline rambus in-line memory module
US6324485B1 (en) 1999-01-26 2001-11-27 Newmillennia Solutions, Inc. Application specific automated test equipment system for testing integrated circuit devices in a native environment
EP1703520B1 (en) 1999-02-01 2011-07-27 Renesas Electronics Corporation Semiconductor integrated circuit and nonvolatile memory element
US6327650B1 (en) * 1999-02-12 2001-12-04 Vsli Technology, Inc. Pipelined multiprocessing with upstream processor concurrently writing to local register and to register of downstream processor
US6285349B1 (en) 1999-02-26 2001-09-04 Intel Corporation Correcting non-uniformity in displays
US6389514B1 (en) * 1999-03-25 2002-05-14 Hewlett-Packard Company Method and computer system for speculatively closing pages in memory
US6496909B1 (en) 1999-04-06 2002-12-17 Silicon Graphics, Inc. Method for managing concurrent access to virtual memory data structures
US6433785B1 (en) 1999-04-09 2002-08-13 Intel Corporation Method and apparatus for improving processor to graphics device throughput
US6381190B1 (en) * 1999-05-13 2002-04-30 Nec Corporation Semiconductor memory device in which use of cache can be selected
JP3376315B2 (ja) 1999-05-18 2003-02-10 日本電気株式会社 ビット同期回路
US6233376B1 (en) 1999-05-18 2001-05-15 The United States Of America As Represented By The Secretary Of The Navy Embedded fiber optic circuit boards and integrated circuits
US6449308B1 (en) 1999-05-25 2002-09-10 Intel Corporation High-speed digital distribution system
US6294937B1 (en) 1999-05-25 2001-09-25 Lsi Logic Corporation Method and apparatus for self correcting parallel I/O circuitry
JP3721283B2 (ja) 1999-06-03 2005-11-30 株式会社日立製作所 主記憶共有型マルチプロセッサシステム
JP2001014840A (ja) 1999-06-24 2001-01-19 Nec Corp 複数ラインバッファ型メモリlsi
US6434736B1 (en) 1999-07-08 2002-08-13 Intel Corporation Location based timing scheme in memory design
US6401213B1 (en) * 1999-07-09 2002-06-04 Micron Technology, Inc. Timing circuit for high speed memory
US6460114B1 (en) 1999-07-29 2002-10-01 Micron Technology, Inc. Storing a flushed cache line in a memory buffer of a controller
US6477592B1 (en) * 1999-08-06 2002-11-05 Integrated Memory Logic, Inc. System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream
US6629220B1 (en) 1999-08-20 2003-09-30 Intel Corporation Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type
US6552564B1 (en) * 1999-08-30 2003-04-22 Micron Technology, Inc. Technique to reduce reflections and ringing on CMOS interconnections
US6539490B1 (en) * 1999-08-30 2003-03-25 Micron Technology, Inc. Clock distribution without clock delay or skew
US6307769B1 (en) 1999-09-02 2001-10-23 Micron Technology, Inc. Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
US6594713B1 (en) 1999-09-10 2003-07-15 Texas Instruments Incorporated Hub interface unit and application unit interfaces for expanded direct memory access processor
US6467013B1 (en) 1999-09-30 2002-10-15 Intel Corporation Memory transceiver to couple an additional memory channel to an existing memory channel
US6438668B1 (en) 1999-09-30 2002-08-20 Apple Computer, Inc. Method and apparatus for reducing power consumption in a digital processing system
US6636912B2 (en) 1999-10-07 2003-10-21 Intel Corporation Method and apparatus for mode selection in a computer system
US6421744B1 (en) 1999-10-25 2002-07-16 Motorola, Inc. Direct memory access controller and method therefor
KR100319292B1 (ko) 1999-12-02 2002-01-05 윤종용 빠른 부팅 속도를 갖는 컴퓨터 시스템 및 그 방법
US6501471B1 (en) 1999-12-13 2002-12-31 Intel Corporation Volume rendering
JP3546788B2 (ja) * 1999-12-20 2004-07-28 日本電気株式会社 メモリ制御回路
JP3356747B2 (ja) 1999-12-22 2002-12-16 エヌイーシーマイクロシステム株式会社 半導体記憶装置
US6496193B1 (en) 1999-12-30 2002-12-17 Intel Corporation Method and apparatus for fast loading of texture data into a tiled memory
US6628294B1 (en) 1999-12-31 2003-09-30 Intel Corporation Prefetching of virtual-to-physical address translation for display data
US6502161B1 (en) * 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
KR100343383B1 (ko) * 2000-01-05 2002-07-15 윤종용 반도체 메모리 장치 및 이 장치의 데이터 샘플링 방법
US6745275B2 (en) * 2000-01-25 2004-06-01 Via Technologies, Inc. Feedback system for accomodating different memory module loading
US6823023B1 (en) 2000-01-31 2004-11-23 Intel Corporation Serial bus communication system
US6185352B1 (en) 2000-02-24 2001-02-06 Siecor Operations, Llc Optical fiber ribbon fan-out cables
JP2001265539A (ja) 2000-03-16 2001-09-28 Fuji Xerox Co Ltd アレイ型記憶装置及び情報処理システム
JP2001274323A (ja) * 2000-03-24 2001-10-05 Hitachi Ltd 半導体装置とそれを搭載した半導体モジュール、および半導体装置の製造方法
US6370611B1 (en) * 2000-04-04 2002-04-09 Compaq Computer Corporation Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data
JP3603751B2 (ja) * 2000-06-02 2004-12-22 日本電気株式会社 メモリアクセス装置
US6728800B1 (en) * 2000-06-28 2004-04-27 Intel Corporation Efficient performance based scheduling mechanism for handling multiple TLB operations
US6594722B1 (en) 2000-06-29 2003-07-15 Intel Corporation Mechanism for managing multiple out-of-order packet streams in a PCI host bridge
US6799268B1 (en) 2000-06-30 2004-09-28 Intel Corporation Branch ordering buffer
JP2002014875A (ja) 2000-06-30 2002-01-18 Mitsubishi Electric Corp 半導体集積回路、半導体集積回路のメモリリペア方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体
US6754812B1 (en) * 2000-07-06 2004-06-22 Intel Corporation Hardware predication for conditional instruction path branching
US6816947B1 (en) 2000-07-20 2004-11-09 Silicon Graphics, Inc. System and method for memory arbitration
US6845409B1 (en) * 2000-07-25 2005-01-18 Sun Microsystems, Inc. Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices
US6647470B1 (en) 2000-08-21 2003-11-11 Micron Technology, Inc. Memory device having posted write per command
US6785780B1 (en) 2000-08-31 2004-08-31 Micron Technology, Inc. Distributed processor memory module and method
US6453393B1 (en) 2000-09-18 2002-09-17 Intel Corporation Method and apparatus for interfacing to a computer memory
US6625687B1 (en) 2000-09-18 2003-09-23 Intel Corporation Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing
US6526483B1 (en) * 2000-09-20 2003-02-25 Broadcom Corporation Page open hint in transactions
US6523092B1 (en) * 2000-09-29 2003-02-18 Intel Corporation Cache line replacement policy enhancement to avoid memory page thrashing
US6859208B1 (en) 2000-09-29 2005-02-22 Intel Corporation Shared translation address caching
US6523093B1 (en) * 2000-09-29 2003-02-18 Intel Corporation Prefetch buffer allocation and filtering system
US6658509B1 (en) 2000-10-03 2003-12-02 Intel Corporation Multi-tier point-to-point ring memory interface
US7187742B1 (en) 2000-10-06 2007-03-06 Xilinx, Inc. Synchronized multi-output digital clock manager
US6349050B1 (en) * 2000-10-10 2002-02-19 Rambus, Inc. Methods and systems for reducing heat flux in memory systems
US6631440B2 (en) 2000-11-30 2003-10-07 Hewlett-Packard Development Company Method and apparatus for scheduling memory calibrations based on transactions
US6792059B2 (en) 2000-11-30 2004-09-14 Trw Inc. Early/on-time/late gate bit synchronizer
US6807630B2 (en) 2000-12-15 2004-10-19 International Business Machines Corporation Method for fast reinitialization wherein a saved system image of an operating system is transferred into a primary memory from a secondary memory
US6801994B2 (en) 2000-12-20 2004-10-05 Microsoft Corporation Software management systems and methods for automotive computing devices
US6751703B2 (en) * 2000-12-27 2004-06-15 Emc Corporation Data storage systems and methods which utilize an on-board cache
US6622227B2 (en) * 2000-12-27 2003-09-16 Intel Corporation Method and apparatus for utilizing write buffers in memory control/interface
DE10110469A1 (de) 2001-03-05 2002-09-26 Infineon Technologies Ag Integrierter Speicher und Verfahren zum Testen und Reparieren desselben
US6782435B2 (en) 2001-03-26 2004-08-24 Intel Corporation Device for spatially and temporally reordering for data between a processor, memory and peripherals
US6904499B2 (en) 2001-03-30 2005-06-07 Intel Corporation Controlling cache memory in external chipset using processor
US6670959B2 (en) * 2001-05-18 2003-12-30 Sun Microsystems, Inc. Method and apparatus for reducing inefficiencies in shared memory devices
DE60236866D1 (de) 2001-05-24 2010-08-12 Tecey Software Dev Kg Llc Optische busanordnung für ein computersystem
US6925520B2 (en) * 2001-05-31 2005-08-02 Sun Microsystems, Inc. Self-optimizing crossbar switch
US6697926B2 (en) * 2001-06-06 2004-02-24 Micron Technology, Inc. Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
SE524110C2 (sv) 2001-06-06 2004-06-29 Kvaser Consultant Ab Anordning och förfarande vid system med lokalt utplacerade modulenheter samt kontaktenhet för anslutning av sådan modulenhet
US6920533B2 (en) * 2001-06-27 2005-07-19 Intel Corporation System boot time reduction method
US20030005344A1 (en) * 2001-06-29 2003-01-02 Bhamidipati Sriram M. Synchronizing data with a capture pulse and synchronizer
US6721195B2 (en) * 2001-07-12 2004-04-13 Micron Technology, Inc. Reversed memory module socket and motherboard incorporating same
US6665498B1 (en) 2001-07-20 2003-12-16 Wenbin Jiang High-speed optical data links
US6792496B2 (en) 2001-08-02 2004-09-14 Intel Corporation Prefetching data for peripheral component interconnect devices
US6904556B2 (en) * 2001-08-09 2005-06-07 Emc Corporation Systems and methods which utilize parity sets
US6681292B2 (en) * 2001-08-27 2004-01-20 Intel Corporation Distributed read and write caching implementation for optimized input/output applications
EP1421465B1 (en) 2001-08-29 2008-08-13 MediaTek Inc. Dynamic voltage control method and apparatus
US7941056B2 (en) * 2001-08-30 2011-05-10 Micron Technology, Inc. Optical interconnect in high-speed memory systems
US6665202B2 (en) 2001-09-25 2003-12-16 Integrated Device Technology, Inc. Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same
US6718440B2 (en) * 2001-09-28 2004-04-06 Intel Corporation Memory access latency hiding with hint buffer
DE10153657C2 (de) * 2001-10-31 2003-11-06 Infineon Technologies Ag Anordnung zur Datenübertragung in einem Halbleiterspeichersystem und Datenübertragungsverfahren dafür
US6886048B2 (en) * 2001-11-15 2005-04-26 Hewlett-Packard Development Company, L.P. Techniques for processing out-of-order requests in a processor-based system
US6646929B1 (en) 2001-12-05 2003-11-11 Lsi Logic Corporation Methods and structure for read data synchronization with minimal latency
KR100454123B1 (ko) 2001-12-06 2004-10-26 삼성전자주식회사 반도체 집적 회로 장치 및 그것을 구비한 모듈
US6775747B2 (en) 2002-01-03 2004-08-10 Intel Corporation System and method for performing page table walks on speculative software prefetch operations
US6804764B2 (en) 2002-01-22 2004-10-12 Mircron Technology, Inc. Write clock and data window tuning based on rank select
US6670833B2 (en) 2002-01-23 2003-12-30 Intel Corporation Multiple VCO phase lock loop architecture
US7006533B2 (en) 2002-02-19 2006-02-28 Intel Corporation Method and apparatus for hublink read return streaming
US7047374B2 (en) 2002-02-25 2006-05-16 Intel Corporation Memory read/write reordering
US6774687B2 (en) 2002-03-11 2004-08-10 Micron Technology, Inc. Method and apparatus for characterizing a delay locked loop
US6795899B2 (en) 2002-03-22 2004-09-21 Intel Corporation Memory system with burst length shorter than prefetch length
US6735682B2 (en) * 2002-03-28 2004-05-11 Intel Corporation Apparatus and method for address calculation
US7110400B2 (en) 2002-04-10 2006-09-19 Integrated Device Technology, Inc. Random access memory architecture and serial interface with continuous packet handling capability
US20030217223A1 (en) 2002-05-14 2003-11-20 Infineon Technologies North America Corp. Combined command set
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US6898674B2 (en) 2002-06-11 2005-05-24 Intel Corporation Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers
DE10234934A1 (de) 2002-07-31 2004-03-18 Advanced Micro Devices, Inc., Sunnyvale Antwortreihenwiederherstellungsmechanismus
US7149874B2 (en) * 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7102907B2 (en) * 2002-09-09 2006-09-05 Micron Technology, Inc. Wavelength division multiplexed memory module, memory system and method
US6667926B1 (en) 2002-09-09 2003-12-23 Silicon Integrated Systems Corporation Memory read/write arbitration method
US6821029B1 (en) 2002-09-10 2004-11-23 Xilinx, Inc. High speed serial I/O technology using an optical link
US6811320B1 (en) 2002-11-13 2004-11-02 Russell Mistretta Abbott System for connecting a fiber optic cable to an electronic device
DE10255937B4 (de) 2002-11-29 2005-03-17 Advanced Micro Devices, Inc., Sunnyvale Ordnungsregelgesteuerte Befehlsspeicherung
US6978351B2 (en) 2002-12-30 2005-12-20 Intel Corporation Method and system to improve prefetching operations
US7366423B2 (en) 2002-12-31 2008-04-29 Intel Corporation System having multiple agents on optical and electrical bus
US6961259B2 (en) 2003-01-23 2005-11-01 Micron Technology, Inc. Apparatus and methods for optically-coupled memory systems
JP3841762B2 (ja) 2003-02-18 2006-11-01 ファナック株式会社 サーボモータ制御システム
US7020757B2 (en) 2003-03-27 2006-03-28 Hewlett-Packard Development Company, L.P. Providing an arrangement of memory devices to enable high-speed data access
US7366854B2 (en) 2003-05-08 2008-04-29 Hewlett-Packard Development Company, L.P. Systems and methods for scheduling memory requests utilizing multi-level arbitration
US20050071542A1 (en) * 2003-05-13 2005-03-31 Advanced Micro Devices, Inc. Prefetch mechanism for use in a system including a host connected to a plurality of memory modules via a serial memory interconnect
US7386768B2 (en) * 2003-06-05 2008-06-10 Intel Corporation Memory channel with bit lane fail-over
US6937076B2 (en) 2003-06-11 2005-08-30 Micron Technology, Inc. Clock synchronizing apparatus and method using frequency dependent variable delay
US20050015426A1 (en) * 2003-07-14 2005-01-20 Woodruff Robert J. Communicating data over a communication link
US7133991B2 (en) 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US7136958B2 (en) * 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7177211B2 (en) * 2003-11-13 2007-02-13 Intel Corporation Memory channel test fixture and method
US7098714B2 (en) * 2003-12-08 2006-08-29 Micron Technology, Inc. Centralizing the lock point of a synchronous circuit
US7529800B2 (en) 2003-12-18 2009-05-05 International Business Machines Corporation Queuing of conflicted remotely received transactions
US7412574B2 (en) 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
US7788451B2 (en) 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7181584B2 (en) 2004-02-05 2007-02-20 Micron Technology, Inc. Dynamic command and/or address mirroring system and method for memory modules
US7257683B2 (en) 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US7447240B2 (en) 2004-03-29 2008-11-04 Micron Technology, Inc. Method and system for synchronizing communications links in a hub-based memory system
US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7363419B2 (en) 2004-05-28 2008-04-22 Micron Technology, Inc. Method and system for terminating write commands in a hub-based memory system
US7046060B1 (en) * 2004-10-27 2006-05-16 Infineon Technologies, Ag Method and apparatus compensating for frequency drift in a delay locked loop
US7116143B2 (en) 2004-12-30 2006-10-03 Micron Technology, Inc. Synchronous clock generator including duty cycle correction

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236540B (zh) * 2007-01-29 2011-07-20 国际商业机器公司 选择预取模式的方法、集线器器件、存储器系统及子系统
CN102792288A (zh) * 2009-12-23 2012-11-21 提琴存储器公司 可配置的互连系统
CN106055495A (zh) * 2015-04-14 2016-10-26 三星电子株式会社 用于控制半导体装置的方法
CN106055495B (zh) * 2015-04-14 2021-06-22 三星电子株式会社 用于控制半导体装置的方法
CN112840401A (zh) * 2018-10-16 2021-05-25 美光科技公司 存储器装置处理

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WO2005024560A3 (en) 2005-12-15
US20110113189A1 (en) 2011-05-12
WO2005024560A2 (en) 2005-03-17
US20070033317A1 (en) 2007-02-08
ATE410735T1 (de) 2008-10-15
US7581055B2 (en) 2009-08-25
JP2007504530A (ja) 2007-03-01
EP1665056A2 (en) 2006-06-07
KR100928852B1 (ko) 2009-11-30
EP1665056A4 (en) 2007-02-28
US7386649B2 (en) 2008-06-10
US7873775B2 (en) 2011-01-18
CN100580643C (zh) 2010-01-13
JP4825993B2 (ja) 2011-11-30
KR20060126910A (ko) 2006-12-11
US7136958B2 (en) 2006-11-14
US20080215792A1 (en) 2008-09-04
US20120303885A1 (en) 2012-11-29
US20050050255A1 (en) 2005-03-03
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US9082461B2 (en) 2015-07-14
DE602004017029D1 (de) 2008-11-20

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