CN1879227A - 具有颗粒半导体材料的应力半导体器件结构 - Google Patents

具有颗粒半导体材料的应力半导体器件结构 Download PDF

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CN1879227A
CN1879227A CNA2004800333678A CN200480033367A CN1879227A CN 1879227 A CN1879227 A CN 1879227A CN A2004800333678 A CNA2004800333678 A CN A2004800333678A CN 200480033367 A CN200480033367 A CN 200480033367A CN 1879227 A CN1879227 A CN 1879227A
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semi
conducting material
nfet
pfet
semiconductor device
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CN100468785C (zh
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B·B·多里斯
M·P·别良斯基
D·C·博伊德
D·奇丹巴尔拉奥
O·格卢斯秦克夫
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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Abstract

一种制造半导体器件结构的方法，包括：提供衬底(1)，在所述衬底(1)上提供电极(6)，在所述电极(6)中形成凹槽(12)，所述凹槽具有开口，在所述凹槽内设置小颗粒半导体材料(17)，覆盖所述开口以包含所述凹槽内的所述小颗粒半导体材料，以及接着退火所得结构。

Description

具有颗粒半导体材料的应力半导体器件结构
技术领域
本发明涉及半导体器件结构，例如同时包括nFET和pFET器件的CMOS器件结构。
背景技术
提高迁移率对于未来的半导体，例如CMOS器件技术来说很重要。从常规工艺技术获得性能的提高变得非常困难。用于应力硅沟道的方法包括：使用从沟道底部施加应力的SiGe；从不同侧面施加应力的不同的浅沟槽隔离(STI)材料选择，和同样从侧面施加纵向应力的SiN蚀刻停止层。SiGe缓冲层或具有应变Si覆层的注入退火缓冲方法的缺点是公知的。缺点包括严重影响产量的位错，以及当扩散增加时明显的控制难度。另外，工艺十分复杂而且成本高昂。STI方法成本较低，但是不会自对准到栅极并具有RX尺寸敏感性。使用氮化硅蚀刻停止层产生应力的低成本方法的确提供一些好处，但是这些好处相信是相对不重要的。
发明内容
本发明使用沟道迁移率提高改善了器件性能。本发明通过使用适当调节的多晶硅栅极叠层的应力特性改善了沟道顶部的迁移率。在本发明之前，这些应力特性非常难控制。然而，本发明包括使用小颗粒多晶硅控制应力特性的方法和结构。本发明提供了给pFET沟道施加压缩应力而给nFET沟道施加拉伸应力的方法和结构。其它实施例包括给pFET沟道施加压缩应力而防止将压缩应力施加给nFET沟道。本发明的另一个实施例包括给nFET沟道施加拉伸应力而防止将拉伸应力施加给pFET沟道。
本发明的方法在栅极电极叠层中设置(例如，淀积)小颗粒多晶Si膜，此膜在退火后变为高拉伸。可以通过在低温下退火在多晶Si膜顶部设置的淀积SiN膜来抑制拉伸膜应力。
本发明的主要目的是提高半导体器件中的沟道迁移率。
根据本发明，制造半导体器件结构的方法包括提供衬底，在所述衬底上提供电极，在所述电极中形成凹槽，所述凹槽具有开口，在所述凹槽内设置小颗粒半导体材料，覆盖所述开口以包含所述凹槽内的所述小颗粒半导体材料，以及接着退火所得结构。本发明也包括半导体器件结构。
根据结合附图的后面的详细描述，本发明的其它目的将变得更加显而易见。
附图说明
图1-9为根据本发明优选实施例的工艺步骤的侧面示意图。
图10示出了优选的本发明的结构中的栅极和沟道中的模拟应力分布。
具体实施方式
现在转向附图，尤其是图1，提供了半导体衬底1。半导体衬底为体Si衬底、SOI衬底、或应力(应变)Si衬底。作为选择，衬底为包括多于一个表面取向的混合衬底。衬底还可以包括Si以外的半导体材料，例如Ge或III-V族元素或II-V族元素的任何组合。
在初始衬底清洁工序(常规的)之后，执行隔离方案。如在半导体制造中公知的，隔离方案用于相互电隔离选择的器件。隔离方案可以是标准的或修改的浅沟槽隔离(STI)方案。图1中示出了STI 2。作为选择，使用LOCOS工艺或平台隔离方案来实现隔离，如半导体器件制造领域内所公知的。对于用于制造半导体器件的各种公知或常规工艺，参照S.M.Sze，(McGraw Hill Publishing Co.，1988)的 VLSI Technology的第二版。
在形成隔离2之后，实施常规栅极氧化物预清洁工艺。如高性能逻辑制造工艺中的情况，各种常规栅极氧化物工艺可以用于制造具有不同栅极氧化物厚度的器件。例如，使用常规热氧化工艺形成栅极氧化物3。使用N2O、NO、O2或它们的任意组合形成氧化物3。可以使用常规等离子体工艺氮化氧化物。作为选择，可以在使用基础氧化物形成栅极氧化物之后淀积例如氧化铝、或氧化铪、或其它高k栅极介质的高k栅极介质。栅极介质材料3具有约(±10％)0.6nm到约7nm的范围内的近似(±10％)一致的厚度。
接下来，在整个晶片结构1、2、3上淀积膜4。膜4用作一次性(可去除)或半一次性栅极电极材料。在优选实施例中，膜4包括具有约80nm到约150nm的范围内的近似一致的厚度或高度(T)的多晶硅(多晶Si)材料。使用例如低压化学气相淀积(LPCVD)或快速热化学气相淀积(RPCVD)的淀积技术淀积可去除的栅极电极材料4。图1中示出了所得结构。多晶Si层4优选具有约1nm到约40nm范围内的标准颗粒尺寸。
接下来，使用常规光刻工艺在可去除的栅极电极材料4上构图光致抗蚀剂图像。通过使用常规干蚀刻工艺，使用附图中并未示出的光致抗蚀剂图像将需要的图形转移进可去除的栅极电极材料4中。干蚀刻工艺包括若干能够相对于栅极氧化物材料3选择蚀刻可去除栅极电极材料4的化学性质。图2中所示结构示出了完全构图的用于nFET栅极叠层3、5的可去除栅极电极5和用于pFET栅极叠层3、6的可去除栅极电极6。
然后使用图中并未示出的，如通常在高性能逻辑制造工艺中使用的常规栅极再氧化工艺。通过使用热氧化工艺形成再氧化，以获得从约1nm到约7nm的近似一致的厚度。在再氧化工艺之后，使用常规光刻工艺在pFET区上构图阻挡掩膜。阻挡(例如，抗蚀剂)掩膜(未在图中示出)用于阻挡或防止pFET区被注入，而适当的nFET区被注入。分别使用低能As和B注入，注入nFET延伸7和晕圈(未示出)。然后使用干或湿工艺除去抗蚀剂掩膜。在nFET区上构图另一个阻挡掩膜(未示出)。分别使用低能BF2或B注入和As注入，注入pFET延伸8和晕圈(未示出)。图2中示出了用于nFET和pFET的延伸注入分布7、8。
在延伸和晕圈注入之后，在整个晶片结构上形成介质衬里层9(图3)。用作衬里层9的介质膜优选为可以通过CVD或RTCVD或任何其它适合的淀积工艺淀积的SiN。衬里层9的目的是提供用于下一个工艺的CMP停止层。另外，在工艺流程的稍后时刻，将蚀刻SiN衬里9，以形成源极-漏极隔离物。图3中示出了所得结构。
工艺流程中的下一步骤是淀积氧化物膜10。淀积并使用化学机械抛光(CMP)平面化氧化物膜10。使用例如高密度等离子体(HDP)工艺淀积膜10。通过使用能够蚀刻氮化硅但不会蚀刻可观量的氧化物或多晶Si的干蚀刻工艺除去可去除栅极电极5之上的衬里9的顶部。图4中示出了在衬里层9的顶部被除去之后平面化的氧化物膜10和SiN衬里9结构。
本发明很重要的一方面是在本发明的工艺流程的此时，栅极凹蚀工艺用于从栅极电极5、6彻底或部分除去多晶Si。图5中示出了其中多晶Si被部分除去的优选实施例。使用任何适合的干或湿蚀刻工艺凹蚀多晶Si。初始多晶Si的部分12和部分13得以保留，并具有约1nm到约20nm范围内的近似一致的厚度。图5中示出了nFET栅极电极的凹蚀部分12和pFET栅极电极的凹蚀部分13。在另一个实施例(未示出)中，多晶Si被彻底除去。如果使用此实施例，那么接下来可以实施其后跟随常规栅极氧化工艺的常规栅极氧化物预清洁工艺。
本发明的另一个重要方面是在栅极凹蚀工艺之后，在整个晶片上淀积小颗粒多晶Si。小颗粒多晶硅公知来自Shimizu，S.et al. Proceeding of the 1997 Symposium on VLSI Technology，Kyoto，Japan10-12June 1997，也可来自S.Wolf，1999的 Silicon Processing for The VLSI Era，Vol 1-ProcessTechnology。颗粒结构优选为约1nm到约50nm范围内。更加优选的颗粒尺寸为约5nm到30nm范围内的基本上一致的尺寸。通过RTCVD或LPCVD淀积多晶Si。接下来，使用例如CMP和干蚀刻从氧化物层10的顶部平面化和凹蚀多晶Si。CMP和干蚀刻工艺都能够相对于SiO2层10选择性除去多晶Si。在CMP或干蚀刻之后，图6中示出了用于nFET的本发明的栅极电极结构14、12和用于pFET的本发明的栅极电极结构13、18。
在本发明的方法的此时，在nFET区上构图图7中所示的硬掩模15。使用包括SiN的介质膜和常规光刻工序构图掩模15。使用例如等离子体增强化学气相淀积的低温淀积工艺在约350℃到约700℃范围内的温度下淀积硬掩模15。优选在550℃下或更低的温度下淀积形成硬掩模15的材料，以防止多晶Si颗粒的再生长。接下来使用从约500℃到约600℃的温度将整个结构退火约1小时。作为选择，可以在约700℃到约1000℃下实施约1秒到约7秒的快速热退火。在另一个实施例中，在本工艺的将来时刻退火结构12、14。因为存在SiN覆层15，对于nFET栅极电极部分17，小颗粒多晶Si保持优选约5nm到约30nm的范围内的小尺寸。然而，pFET栅极电极部分18中的颗粒明显生长到大于约30nm的颗粒尺寸。
本发明人相信，本发明的工艺(例如，参照图7)与常规工艺技术存在显著差别。如果使小颗粒多晶Si经过标准热预算，那么多晶Si颗粒生长会引起拉伸应力的剧烈增长。拉伸应力在沟道区内产生压缩应力，此压缩应力会降低电子迁移率并限制nFET的性能。参照图10的模拟。本发明人相信，通过利用置于nFET区之上的SiN硬掩模15退火，几乎可以完全消除颗粒生长和导致拉伸应力的剧烈增长。对于每个器件，可以通过将小颗粒多晶Si淀积进入凹槽并用SiN硬掩模退火nFET分别优化颗粒结构。此步骤的出现可以导致nFET器件性能的显著改善。
本发明的工艺的下一步骤从氧化物膜10的整个水平部分或从整个水平部分(除了部分17上的，如图8中所示)除去SiN硬掩模15。因为如上所述凹蚀了多晶Si，所以硬掩模15的一部分19保留(设置)在如图8中所示的凹蚀孔中。结构19用于阻止颗粒在后面的标准尖端半导体制造工艺技术中公用的常规热循环期间生长。在SiN蚀刻之后，使用能够相对于SiN和多晶Si材料选择性除去SiO2膜的适当的干或使蚀刻工艺除去氧化物膜10。接下来，在衬里层9上实施干定向蚀刻工艺，以形成如图8中所示的隔离物20、25。虽然pFET的隔离物20和nFET的隔离物25对于本发明并不关键，但是它们可以具有如图中所示的不同高度。使用用于形成nFET和pFET延伸区7、8的类似阻挡掩模和注入工艺形成图8中所示的nFET源极-漏极区21和pFET源极-漏极区22。接下来实施快速热退火以激活结。因为nFET继续存在SiN层19，所以nFET栅极中的颗粒生长得以抑制，由此最小化了栅极电极叠层3、12、17中的拉伸和叠层下面的沟道区中的后续压缩。
然后使用湿或干蚀刻工艺除去栅极电极叠层上的剩余部分19。接着，在实施硅化物预清洁工艺之后进行常规硅化物工艺。参照图9和硅化物23。实施的标准后段制程工艺包括预金属介质淀积和平面化、接触蚀刻、形成接触衬里和形成接触，接着是金属布线和最终的芯片制造，所有这些都未在图中示出。
模拟结果显示，在约600℃的温度下退火约1小时的结果是未覆盖的多晶Si中的拉伸应力水平会增加约600MPa到约1200MPa，而覆盖的多晶Si中的拉伸应力只增加约10MPa。我们的模拟结果显示，可以将栅极材料中的应力的约33％到约50％(相对于栅极应力用了相反的符号)转移进沟道区。这样，未覆盖的栅极叠层施加了-200MPa到-300MPa，而覆盖的栅极叠层只将很少应力的或不将应力转移进沟道区。图10的图中示出了应力分布的一个模拟。
尽管示出和描述了这里认为是优选的本发明的实施例，但是对于本领域内的技术人员来说明显地是，在不脱离仅由所附权利要求限制的本发明的精神和范围的情况下，可以进行各种变化和修改。

Claims (20)

1.一种制造半导体器件结构的方法，包括：
提供衬底；
在所述衬底上提供电极；
在所述电极中形成凹槽，所述凹槽具有开口；
在所述凹槽内设置小颗粒半导体材料；
覆盖所述开口以包含所述凹槽内的所述小颗粒半导体材料；以及接着退火所得结构。
2.根据权利要求1的方法，其中所述退火步骤包括在约500℃到约600℃范围内的近似恒定温度下将所述所得结构退火约1小时。
3.根据权利要求1的方法，其中所述小颗粒半导体材料为具有约1nm到约30nm范围内的平均颗粒直径的多晶硅材料。
4.根据权利要求1的方法，其中所述覆盖步骤包括掩蔽所述整个开口。
5.一种半导体器件结构，包括：
第一半导体器件，具有第一栅极叠层，以及
第二半导体器件，具有第二栅极叠层；其中所述第一栅极叠层包括具有小于约30nm的平均颗粒尺寸的第一半导体材料，以及其中所述第二栅极叠层包括具有大于约30nm的平均颗粒尺寸的第二半导体材料。
6.根据权利要求5的结构，其中所述第一半导体材料为颗粒多晶硅。
7.根据权利要求5的结构，其中所述第一半导体器件为nFET而所述第二半导体器件为pFET。
8.根据权利要求5的结构，还包括位于所述第一栅极叠层下面的第一沟道，和位于所述第二栅极叠层下面的第二沟道；其中所述第二栅极叠层给所述第二沟道施加约-200MPa到约-600MPa范围内的压缩应力，而所述第一栅极叠层给所述第一沟道施加约-10MPa到约-100MPa范围内的压缩应力。
9.根据权利要求5的结构，还包括位于所述第一半导体器件和所述第二半导体器件之间的隔离区。
10.根据权利要求5的结构，其中所述第二半导体材料为颗粒多晶硅。
11.根据权利要求5的结构，还包括第三半导体材料和第四半导体材料，其中所述第一半导体材料位于所述第三半导体材料上，以及所述第二半导体材料位于所述第四半导体材料上。
12.根据权利要求11的结构，其中所述第三半导体材料是小颗粒多晶硅，以及所述第四半导体材料是小颗粒多晶硅。
13.一种用于制造半导体器件结构的方法，包括：
提供衬底；
在所述衬底上形成nFET和pFET；
用小颗粒多晶硅代替所述nFET和所述pFET的栅极电极的一部分；
覆盖所述nFET的所述小颗粒多晶硅，并接着加热所述nFET和所述pFET，以使所述nFET内的颗粒的平均直径小于所述pFET内的颗粒的平均直径。
14.根据权利要求13的方法，其中所述加热步骤包括在约500℃到约600℃范围内的温度下将所述nFET和所述pFET加热约1小时。
15.根据权利要求13的方法，其中所述小颗粒多晶硅具有约5nm到约30nm范围内的平均颗粒尺寸。
16.根据权利要求13的方法，其中所述代替步骤包括除去所述栅极电极的一部分以形成凹槽，并接着将所述颗粒多晶硅设置在所述nFET和所述pFET的凹槽内。
17.根据权利要求13的方法，其中所述代替步骤包括除去所述栅极电极的整个部分以形成凹槽，并接着将所述小颗粒多晶硅设置在所述凹槽内。
18.根据权利要求13的方法，其中所述覆盖步骤包括在所述nFET的所述颗粒多晶硅之上设置掩模，所述掩模主要包括SiN。
19.根据权利要求13的方法，还包括形成用于所述nFET和所述pFET的隔离物，所述隔离物具有不同的高度。
20.根据权利要求13的方法，还包括提供用于所述nFET和所述pFET的隔离物，所述用于所述pFET的隔离物的高度小于所述用于所述nFET的隔离物的高度。
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