CN1909226B

CN1909226B - Package substrate

Info

Publication number: CN1909226B
Application number: CN 200610094490
Authority: CN
Inventors: 浅井元雄; 森要二
Original assignee: Ibiden Co Ltd
Current assignee: Ibiden Co Ltd
Priority date: 1997-10-17
Filing date: 1998-09-28
Publication date: 2012-09-26
Anticipated expiration: 2018-09-28
Also published as: JPH11121932A; CN101017806A; CN1897264A; CN1909226A; CN1901180A; CN101013685B; CN100547780C; CN100431144C; CN101013685A

Abstract

According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 mum in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 mum in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.

Description

Base plate for packaging

The application is that application number is 200410045619.0, the applying date is on September 28th, 1998, division is submitted the dividing an application for the application for a patent for invention of " base plate for packaging " that day be on May 10th, 2004, denomination of invention to.

Technical field

The present invention relates to be used to load the base plate for packaging of IC chip, in more detail, the present invention relates to respectively to have formed the base plate for packaging of the weld zone that is connected usefulness that the IC chip is connected weld zone (pad) and the substrates such as motherboard, daughter board of usefulness at upper surface and lower surface.

Background technology

High integration IC chip is loaded on the base plate for packaging, is connected with substrates such as motherboard, daughter boards.Figure 23 illustrates IC chip 80 is loaded on the base plate for packaging 600 and is installed in the state on the motherboard 90, and the formation of this base plate for packaging is described with reference to Figure 23.This base plate for packaging 600 forms conductor circuit 658A, 658B on the two sides of chip substrate 630; Upper strata at this conductor circuit 658A, 658B forms

conductor circuit

658C, 658D; Middle across interlayer resin insulating layers 650, in the upper-layer configured interlayer resin insulating layers 750 of this conductor circuit 658C, 658D.And, on this interlayer resin insulating layers 650, form through hole 660B, 660A, on interlayer resin insulating layers 750, form through hole 660D, 660C.On the other hand, go up formation pedestal 676U on the surface of IC chip 80 1 sides (upper surface), be used for being connected, go up on the surface of daughter board 6000 (lower surface) and form pedestal 676D, be used for being connected with the weld zone 92 of motherboard 90 with the weld zone 82 of IC chip 80.This pedestal 676U forms on weld zone 675U, and pedestal 676D forms on weld zone 675D.Here,, between IC chip 80 and base plate for packaging 600, sealed resin 84 in order to realize the reliable connection of

pedestal

676U, 676D, same, between base plate for packaging 600 and motherboard 90, sealed resin 94.

As stated, base plate for packaging 600 is used for connecting high integration IC chip 80 and motherboard 90.That is, weld zone 82 diameters of IC chip 80 are little, are 133～170 μ m, and weld zone 92 diameters of motherboard 90 1 sides are big, are 600 μ m, can not directly the IC chip be installed on the motherboard, so, utilize base plate for packaging to carry out relaying.

Base plate for packaging forms the weld zone 675U of IC chip one side and the weld zone 675D of motherboard one side with the size of the weld zone 92 of weld zone of above-mentioned IC chip 82 and motherboard respectively accordingly.Therefore, to account for the ratio of surface area of motherboard one side of base plate for packaging 600 different for the area of the weld zone 675U area of ratio and weld zone 675D of surface area that accounts for IC chip one side of base plate for packaging 600.Here, interlayer insulating film 650 and chip substrate 630 are formed by resin, and

weld zone

675U, 675D are formed by metals such as nickel.Therefore; In manufacturing process; When sclerosis that utilizes interlayer resin insulating layers 650,750 and drying etc. are partly shunk this resin; Because the area of above-mentioned weld zone 675U accounts for ratio poor that the area of ratio and weld zone 675D of the surface area of IC chip one side accounts for the surface area of motherboard one side, base plate for packaging carries out situation from a side warpage to the IC chip can occur.And then, when loading actual uses of IC chip, under the situation of shrinking repeatedly because of the heating of IC chip, owing to this resin partly and metal section and part be shrinkage poor of weld zone, also can produce warpage.

On the other hand, in the multilager base plate that uses as base plate for packaging, 1 layer of conductor circuit in the multi-layer conductive circuit used as ground plane or bus plane, its objective is in order to reduce noise etc.But in the existing multi-layer wire substrate of that kind shown in figure 23, this ground plane (or bus plane) carried out with being connected through wiring of outside terminal.That is, become wiring 658A, the 658B (conductor circuit) of ground plane on the upper strata of substrate 630.This wiring (ground plane) 658B via through holes 660B is connected with wiring 658D-S, and this wiring 658D-S via through holes 660D is connected with pedestal 676U.

Here, being connected through wiring 658D-S of ground plane 658D and pedestal 676U carried out, so this wiring 658D-S causes noise easily, this noise just becomes the reason of the misoperation of the electronic component on the multi-layer wire substrate that is connected integrated chip etc.In addition, also need reserve in multi-layer wire substrate the space of this wiring being carried out cabling, this has just hindered the realization of densification.

On the other hand, generally form capacitor, be used for reducing the noise of the signal between IC chip and the motherboard etc. in the inside of base plate for packaging.In example shown in Figure 23, the inner conductor circuit 658B on the two sides that is located at chip substrate 630,658A are formed as bus plane and ground plane, thus, get involved chip substrate 630 and formed capacitor.

Figure 24 (A) is the plane graph of the inner conductor circuit 658B of formation on chip substrate 630.On this inner conductor circuit 658B, form contact (land) weld zone 640 that ground plane 638G and levels connect usefulness.Around this contact weld zone 640, form buffer insulation band 642.

Contact weld zone 640 is made up of with the wiring 640c that is connected contact 640a and weld zone 640b the contact 640a of the through hole 636 that connects chip substrate 630 shown in Figure 23, the weld zone 640b that is connected with the through hole 660A of the interlaminar insulating resin layer 650 that connects the upper strata.

Here, in the base plate for packaging of prior art, contact 640a is connected through wiring 640c with weld zone 640b, so the transfer path between top conductor layer and the lower floor's conductor layer is long, signal velocity is slow, and contact resistance is high simultaneously.

In addition, such shown in Figure 24 A, in weld zone 640, possibly there is bight K at the connecting portion that reaches between wiring 640C and the weld zone 640b between wiring 640C and the contact 640a.In the thermal cycle of base plate for packaging; Because of resinous chip substrate 630 and interlayer resin insulating layers 650 different with the thermal coefficient of expansion of the weld zone of making of metals such as copper 640; So stress concentrates on this bight K; That kind shown in figure 23, at interlayer resin insulating layers 650 generation crack L1, broken string can appear in conductor circuit 658D on this interlayer resin insulating layers 650 or through hole 660D.

On the other hand, the pedestal 676D via through holes 660D-of motherboard 90 1 sides wiring 678-weld zone 675 is connected with the conductor circuit 658C of internal layer.What Figure 24 (B) illustrated through hole 660D and pedestal 675D among Figure 23 looks enlarged drawing in the past sideways from C.The pedestal 675 of placing pedestal 676D is rounded, as stated, is connected with rounded through hole 660D through wiring 678.

IC chip 80 is cooled to when being in the condition of high temperature and the end-of-job in the work repeatedly in the thermal cycle of state of normal temperature.Here, the thermal coefficient of expansion of IC chip that is formed by silicon and the base plate for packaging 600 that formed by resin differs greatly, so in this thermal cycle, base plate for packaging 600 can produce stress, the sealing resin 94 between base plate for packaging 600 and the motherboard 90 can produce crack L2.Here, when this resin 94 generation crack L2, this crack L2 elongation and make base plate for packaging 600 through hole 660D and pedestal 675D be connected disconnection.That is, such like the enlarged drawing of looking sideways in the past from D of through hole 660D among Figure 23 that Figure 24 (C) illustrates and pedestal 675, the wiring 678 that connects the pedestal 675D that places pedestal 676D and through hole 660D is understood because of the existence of crack L2 and broken.

Summary of the invention

The present invention proposes in order to solve above-mentioned problem, and its purpose is to provide a kind of base plate for packaging with not warpage of pedestal.

The present invention also aims to provide a kind of multi-layer wire substrate and multi-layer printed wiring base plate of not allowing to be subject to noise effect.

The present invention also aims to provide a kind of base plate for packaging, can shorten the transmitting range between upper strata wiring and the lower-layer wiring.

The present invention also aims to provide a kind of base plate for packaging, broken string between pedestal and through hole, can not occur.

According to the present invention; A kind of base plate for packaging is provided; This base plate for packaging has the insulating barrier of outermost conductor circuit, the outermost conductor circuit of support and is located at the multi-layer wire substrate of the inner conductor circuit of this insulating barrier volume two; It is characterized in that: above-mentioned inner conductor circuit is bus plane and/or ground plane, connect above-mentioned insulating barrier and with through hole that above-mentioned inner conductor circuit is connected on formed pedestal.

The present invention also provides a kind of base plate for packaging; This base plate for packaging is the 1st conductor circuit with internal layer, the 1st interlayer resin insulating layers that on the 1st inner conductor circuit, forms, at the 2nd conductor circuit of the internal layer that forms on the 1st interlayer resin insulating layers, at the multi-layer wire substrate of the 2nd interlayer resin insulating layers that forms on the 2nd conductor circuit and the outermost conductor circuit that on the 2nd interlayer resin insulating layers, forms; It is characterized in that: the 2nd conductor circuit of above-mentioned internal layer is bus plane and/or terrace layer, connect above-mentioned the 2nd interlayer resin insulating layers and with through hole that above-mentioned the 2nd conductor circuit is connected on formed pedestal.

The present invention also provides a kind of base plate for packaging; Wherein, On the two sides of fuse substrate, form conductor layer; And then form conductor layer again through interlayer resin insulating layers, the conductor layer of above-mentioned fuse substrate one side is used as electrode layer, it is characterized in that: will be configured in fuse substrate on the conductor layer that forms above-mentioned electrode layer connect usefulness through hole contact with connect above the through hole of interlayer resin insulating layers of a side be connected being made of one of weld zone of usefulness.

The present invention also provides another kind of base plate for packaging; Wherein, On the two sides of fuse substrate, form conductor layer; And then form conductor layer again through interlayer resin insulating layers, the conductor layer above the above-mentioned a certain interlayer resin insulating layers is used as electrode layer, it is characterized in that: the contact that will be configured in the through hole of interlayer resin insulating layers below the perforation on the conductor layer that forms above-mentioned electrode layer with connect above the through hole of interlayer resin insulating layers of a side be connected being made of one of weld zone of usefulness.

The present invention also provides a kind of base plate for packaging; Form the multi-layer conductive circuit through the multilayer interlayer resin insulating layers; On the surface that IC chip one side is installed and the surface that is connected to other substrate one side, form pedestal; Between this is connected to surface and this other substrates of the side on other substrate, carry out resin-sealedly, it is characterized in that, be connected to the pedestal of the side surface on other substrate having formed this on the through hole.

The present invention also provides a kind of base plate for packaging; Form the multi-layer conductive circuit and form through the multilayer interlayer resin insulating layers by core substrate with on the two sides of above-mentioned core substrate; Be electrically connected through the through hole that is formed at above-mentioned interlayer resin insulating layers between the above-mentioned conductor circuit of mutually different layer; On the surface that IC chip one side is installed and the surface that is connected to other substrate one sides, form pedestal; Between this is connected to surface and this other substrates of the side on other substrates, carry out resin-sealedly, it is characterized in that, on each sets of vias of forming by a plurality of above-mentioned through holes, form one this be connected to the pedestal of the side surface on other substrates.

In the present invention, the weld zone of IC chip one side of base plate for packaging is little, and the shared ratio in metal section and part weld zone is also little, and the weld zone of substrates such as motherboard one side is big, and the ratio of metal section and part is also big.Here, between the figure of the conductor circuit of the IC of base plate for packaging one side, form virtual pattern, thus, increase metal section and part, thereby adjust the ratio of the metal section and part of this IC chip one side and motherboard one side, make base plate for packaging not produce warpage.Here, so-called virtual pattern is meant the existence that does not have electrical connection or capacitor etc., only is the figure on the mechanical sense.

In the present invention, the weld zone of IC chip one side of base plate for packaging is little, and the shared ratio in metal section and part weld zone is also little, and the weld zone of substrates such as motherboard one side is big, and the ratio of metal section and part is also big.Here; Periphery at the conductor circuit of the IC of base plate for packaging chip one side forms virtual pattern, thus, increases metal section and part; Thereby adjust the ratio of the metal section and part of this IC chip one side and motherboard one side; Simultaneously, utilize metal virtual pattern to improve the mechanical strength of base plate for packaging outer peripheral portion, make base plate for packaging not produce warpage.

Have, in the present invention, virtual pattern can be electrically connected with power supply or ground plane again, perhaps, virtual pattern itself also can be power supply or ground plane.So, can prevent the noise of holding wire.

Description of drawings

Fig. 1 is the sectional view of the base plate for packaging of expression the 1st example of the present invention.

Fig. 2 is the X1-X1 cross-sectional view of base plate for packaging shown in Figure 1.

Fig. 3～Fig. 9 is the figure of manufacturing process of the base plate for packaging of expression the 1st example of the present invention.

Figure 10 is the sectional view of the base plate for packaging of expression the 2nd example of the present invention.

Figure 11 (A) is the plane graph of the base plate for packaging of the 2nd example, and Figure 11 (B) is the ground plan of IC chip.

Figure 12 is illustrated in the sectional view of placing the IC chip on the base plate for packaging shown in Figure 10 and being installed in the state on the motherboard.

Figure 13 is the sectional view of the multi-layer printed wiring base plate of expression the 3rd example of the present invention.

Figure 14 is the sectional view of formation of multi-layer printed wiring base plate of the variation of expression the 3rd example of the present invention.

Figure 15 is the sectional view of the base plate for packaging of expression the 4th example of the present invention.

Figure 16 (A) be the 4th example base plate for packaging formation the plane graph of chip substrate of internal layer copper figure, Figure 16 (B) is the local amplification view of Figure 16 (A).

Figure 17 is the sectional view of base plate for packaging of the variation of expression the 4th example of the present invention.

Figure 18 (A) is the plane graph of the conductor circuit that on base plate for packaging, forms of the variation of the 4th example, and Figure 18 (B) is the local amplification view of Figure 18 (A).

Figure 19 is the sectional view of the base plate for packaging of expression the 5th example of the present invention.

Figure 20 is illustrated in the sectional view of placing the IC chip on the base plate for packaging shown in Figure 19 and being installed in the state on the motherboard.

Figure 21 is the sectional view of base plate for packaging of the variation of expression the 5th example of the present invention.

Figure 22 is the X5-X5 cross-sectional view of the base plate for packaging of Figure 21.

Figure 23 is the sectional view of the base plate for packaging of prior art.

Figure 24 (A) is the plane graph of the inner conductor circuit of Figure 23, and Figure 24 (B) is that the C of Figure 23 vows view, and Figure 24 (C) is that the D of Figure 23 vows view.

Embodiment

(the 1st example)

The formation of the base plate for packaging of the 1st example of the present invention is described with reference to Fig. 1.Fig. 1 illustrates the cross sectional shape of the base plate for packaging of the 1st example, and this base plate for packaging constitutes the encapsulation of so-called integrated circuit, has been used for placing in the above under the state of integrated circuit (not shown) attaching it on the motherboard (not shown).This base plate for packaging is provided with in the above and is used for the pedestal 76U that is connected with the pedestal side of integrated circuit; A side is provided with and is used for the pedestal 76D that is connected with the pedestal of motherboard below, between this integrated circuit and motherboard, works to transmit signal etc. and the power supply that comes from motherboard supplied with and carry out relaying.

On the chip substrate 30 of base plate for packaging with below on form internal layer copper figure 34U, 34D as ground plane.In addition, get involved conductor circuit 58U, virtual pattern 58M and the through hole 60U that interlayer resin insulating layers 50 forms as holding wire on the upper strata of the 34U of internal layer copper figure, through hole 60U connects this interlayer resin insulating layers 50.Upper strata at conductor circuit 58U and virtual pattern 58M; Form outermost layer conductor circuit 158U and the through hole 160U that connects this interlayer resin insulating layers 150 through interlayer resin insulating layers 150, on this conductor circuit 158U and through hole 160U, form the weld zone 75U that supports pedestal 76U.Here, the diameter of the weld zone 75U of IC chip one side is 133～177 μ m.

On the other hand; (the upper strata here means that with substrate 30 be the center on the upper strata of the ground plane of side below chip substrate 30 (internal layer copper figure) 34D; Deserve to be called side above the substrate, the following title downside of substrate), through the conductor circuit 58D of interlayer resin insulating layers 50 formation as holding wire.Upper strata at this conductor circuit 58D; Form outermost layer conductor circuit 158D and the through hole 160D that connects this interlayer resin insulating layers 150 through interlayer resin insulating layers 150, on this conductor circuit 158D and through hole 160D, form the weld zone 75D that supports pedestal 76D.Here, the diameter of the weld zone 75D of motherboard one side is 600 μ m.

Fig. 2 illustrates the X1-X1 cross section of Fig. 1.That is, Fig. 2 illustrates the cross section of base plate for packaging, and X1-X1 longitudinal section and Fig. 1 among Fig. 2 are suitable.As shown in Figure 2, between the conductor circuit 58U-conductor circuit 58U that constitutes holding wire, form virtual pattern 58M.Here, so-called virtual pattern is meant the existence that does not have electrical connection or capacitor etc., only is the figure on the mechanical sense.

Identical with the base plate for packaging of the above-mentioned prior art of Figure 23, the base plate for packaging of the 1st example, the weld zone little (diameter is 133～177 μ m) of surface (top) configuration of its IC chip one side is so the ratio that the weld zone metal section and part accounts for is little.On the other hand, the weld zone big (diameter is 600 μ m) of the surface of motherboard etc. (following) configuration is so the ratio that metal section and part accounts for is big.Here; In the base plate for packaging of this example, between the conductor circuit 58U of the holding wire of IC chip one side that forms base plate for packaging, 58U, form virtual pattern 58M, so; Metal section and part has increased; Thereby adjusted the ratio of the metal section and part of this IC chip one side and motherboard one side, after the base plate for packaging stated manufacturing process with use, warpage can not take place in base plate for packaging.

Next, specify the manufacturing approach of base plate for packaging shown in Figure 1 for example.At first, the composition of A. plated by electroless plating with bonding agent, the agent of B. interlayer insulation resin, C. resin filler, D. solder resist is described.

A. prepare the feedstock composition (bonding agent is used on the upper strata) of plated by electroless plating with bonding agent

[resin combination 1.]

Cresols type epoxy resin (Japanese chemical drug system with concentration 25%; Molecular weight 2500) and the acrylic compound of concentration 80wt% be dissolved in and form resin solution among the DMDG; With this resin solution of 35 Unit Weights, the photo-sensitive monomer of 3.15 Unit Weights (the synthetic system in East Asia; ARONIXM315), (the SAMNOPUKO system S-65) obtains after mixing with the NMP of 3.6 Unit Weights for the antifoaming agent of 0.5 Unit Weight.

[resin combination 2.]

With the average grain diameter of the polyether sulphur (PES) of 12 Unit Weights, 7.2 Unit Weights is that (Sanyo changes into system for the epoxy particles of 1.0 μ m; POLYMERPOLE) and 3.09 Unit Weight average grain diameters be after the epoxy particles of 0.5 μ m mixes; And then add the NMP of 30 Unit Weights, steep with pearl and obtain after mixer (beads mixer) mixes.

[hardener composition 3.]

(four countries change into system with the imidazole hardeners of 2 Unit Weights; 2E4MZ-CN), (Japanese chemical drug system DETX-S) obtains after mixing with the NMP of 1.5 Unit Weights for the light sensitizer of the light initiator (CIBA GEIGY IRUGAKYUA I-907) of 2 Unit Weights, 0.2 Unit Weight.

B. prepare the feedstock composition (lower floor uses bonding agent) that the agent of interlayer insulation resin is used

[resin combination 1.]

[resin combination 2.]

With the average grain diameter of the polyether sulphur (PES) of 12 Unit Weights and 14.49 Unit Weights is that (Sanyo changes into system for the epoxy particles of 0.5 μ m; POLYMERPOLE) after the mixing; And then add the NMP of 30 Unit Weights, steep with pearl and obtain after mixer (beads mixer) mixes.

[hardener composition 3.]

C. prepare the feedstock composition of the usefulness that the resin filler uses

[resin combination 1.]

With the Bisphenol F type epoxy monomer of 100 Unit Weights (oiling snow land (シェ Le) system, molecular weight 310, YL983U), the surface applied of 170 Unit Weights the average grain diameter of silane bonding agent be the SiO of 1.6 μ m ₂Spherical particle (ADOMATEC system; CRS1101-CE; Here the size of the largest particles after state below the thickness (15 μ m) of internal layer copper figure) and smoothing agent (the SAMNOPUKO system of 1.5 Unit Weights; PELENOLE S4) mixes, and after under 23 ± 1 ℃ the state viscosity of this mixture being adjusted to 45000～49000cps, obtain.

[hardener composition 2.]

6.5 (four countries change into system to the imidazole hardeners of Unit Weight, 2E4MZ-CN).

D. solder resist composition

Obtain photonasty oligomer (molecular weight 4000) after the 50% epoxy radicals propyleneization with the cresols type epoxy resin (Japanese chemical drug system) that is dissolved in 60% weight among the DMDG; The photonasty oligomer that 46.67 grams are such, 15.0 grams are dissolved in bisphenol A-type resin (the oiling snow land system of 80% weight in the methyl ethyl ketone; EPICOTE 1001), 1.6 the gram imidazole hardeners (four countries change into system; 2E4MZ-CN), multivalence acrylic monomer (the Japanese chemical drug system of the photo-sensitive monomer of 3 grams; R604), the multivalence acrylic monomer of 1.5 grams (common prosperity society chemistry system; DPE6A) and 0.71 gram disperse system antifoaming agent (SAMNOPUKO makes; S-65) mix, and then this mixture is added two propiophenones (Northeast chemistry is made) of the conduct light initiator of 2 grams and the rice phase Le Shi ketone as light sensitizer of 0.2 gram (Northeast chemistry manufacturing), after under 25 the state viscosity of this mixture being adjusted to 2.0Pas, obtain the solder resist mixture.

Have, Brookfield viscometer (Tokyo gauge, DVL-B type) is used in viscosimetric analysis again, uses rotor No.4 during 60rpm, uses rotor No.3 during 6rpm.

Next, the manufacturing approach of base plate for packaging 100 is described with reference to Fig. 3～9.

E. the manufacturing of base plate for packaging

(1) at the Copper Foil 32 that by thickness is the two sides lamination 18 μ m of the glass epoxy resin of 1mm or the substrate 30 that BT (Bismaleimide Triazine) resin forms, form copper containing layer lamination 30A, and with it as parent material (with reference to the operation (A) of Fig. 3).At first,, carry out plated by electroless plating again and handle, utilize pattern etching to form internal layer copper figure 34U, 34D and through hole 36 (operation of Fig. 3 (B)) on the two sides of substrate 30 the above-mentioned copper containing layer lamination 30A processing of holing.

(2) substrate 30 that has formed internal layer copper figure 34U, 34D and through hole 36 is washed, after the drying, used NaOH (10g/l), NaClO as oxidation bath (melanism bath) ₂(40g/l) and Na ₃PO ₄(6g/l), use NaOH (10g/l) and NaBH as reducing bath ₄(6g/l) carry out OR and handle, formed roughened layer 38 (the operation C of Fig. 3) on the surface of internal layer copper figure 34U, 34D and through hole 36 thus.

(3) will prepare feedstock composition that the resin filler of C uses mixes and obtains the resin filler after mixing.

(4) two sides that was coated in substrate 30 in 24 hours with interior resin filler 40 that obtains after using the spin coated machine with above-mentioned (3) preparation; Make its be filled between conductor circuit (internal layer copper figure) 34U and the conductor circuit 34U with through hole 36 in; Drying is 20 minutes under 70 ℃ condition; To another side, equally with the resin filler be filled between the conductor circuit 24 with through hole 36 in, dry 20 minutes (with reference to the operation (D) of Fig. 3) under 70 ℃ condition.

A face of the substrate 30 after the processing that (5) utilizes the belt skin grinder that has used the banded pouncing paper of #600 (three are total to the physics and chemistry length of schooling) to grind above-mentioned (4) finishes; Make the surface of contact 36a of surface and the through hole 36 of its internal layer copper figure 34U, 34D not stay resin filler 40; Then; Polish grinding, be used for removing the scratch that the grinding because of above-mentioned belt skin grinder causes.Another side to substrate carries out so a series of milled processed (operation of Fig. 4 (E)) too.

Secondly, under the condition of 100 ℃, 120 ℃, 150 ℃ and 180 ℃, carry out the heat treated of 1 hour, 3 hours, 1 hour and 7 hours respectively, make 40 sclerosis of resin filler.

So; Just obtained a kind of circuit board, this circuit board has not only been removed skin section and inner conductor circuit 34U, the roughened layer above the 34D 38 of the resin filler 40 that is filled in through hole 36 grades, makes substrate 30 two sides level and smooth; And; The side of resin filler 40 and inner conductor circuit 34 bonds together through roughened layer 38 securely, and in addition, the internal face of through hole 36 and resin filler 40 bond together through roughened layer 38 securely.That is, through this operation, make resin filler 40 surface and internal layer copper figure 34 the surface at grade.

(6) substrate 30 that forms

conductor circuit

34U, 34D is carried out alkaline degreasing and soft etching, secondly, use the catalyst solution that forms by palladium bichloride and organic acid to handle, make it have the Pd catalyst, after this catalyst activityization, be immersed in by 3.2 * 10 ^-2The copper sulphate of mol/l, 3.9 * 10 ^-3The nickelous sulfate of mol/l, 5.4 * 10 ^-2The complex compound catalyst of mol/l, 3.3 * 10 ^-1The inferior sodium phosphate of mol/l, 5.0 * 10 ^-1The boric acid of mol/l and the interfacial agent of 0.1g/l (day letter chemical industry system; SURFIL 465) in the plated by electroless plating liquid of the PH=9 that constitutes; Flood after 1 minute; Make it to carry out vertical and horizontal vibrations, form acicular alloy cover layer and the roughened layer 42 (operation of Fig. 4 (F)) that forms by Cu-Ni-P on the surface of the contact 36A of conductor circuit 34 and through hole 36 with 4 seconds 1 time frequency.

And then, under temperature is 35 ℃, the condition of PH=1.2, make the fluorine boronation tin of 0.1mol/l and the thio urea of 1.0mol/l carry out the Cu-Sn displacement reaction, forming thickness on the surface of roughened layer is the Sn layer (not shown) of 0.3 μ m.

(7) will prepare the feedstock composition that the interlayer insulation resin agent of B uses and mix, and viscosity adjusted to obtained interlayer insulation resin agent (lower floor with) behind the 1.5Pa.s.

Secondly, the feedstock composition that the plated by electroless plating of preparing A is used with bonding agent mixes, and obtains plated by electroless plating with bonding agent (upper strata usefulness) after viscosity is adjusted to 7Pa.s.

(8) viscosity of using the spin coated machine to apply to obtain from above-mentioned (7) on the two sides of the substrate of above-mentioned (6) as back 24 hours of the preparation of 1.5Pa.s with interior interlayer insulation resin agent (lower floor with) 44; In the level held after 20 minutes; Drying (prebake conditions) is 30 minutes under 60 ℃ condition; Secondly, back 24 hours of the preparation that applies the viscosity that obtains from above-mentioned (7) and be 7Pa.s is with interior photosensitive adhesive agent solution (lower floor with) 46, in the level held after 20 minutes; Drying (prebake conditions) is 30 minutes under 60 ℃ condition, and forming thickness is the bonding agent 50d (operation of Fig. 4 (G)) of 35 μ m.

(9) in above-mentioned (8), formed the two sides of the substrate of bonding agent, the bonding photomask (not shown) that is printed with the black circle of φ 85 μ m utilizes extra-high-pressure mercury vapour lamp with 500mJ/cm ²Intensity exposure.Again it is developed in DMTG solution, and then, utilize extra-high-pressure mercury vapour lamp to this substrate 30 with 3000mJ/cm ²Intensity exposure; Under the condition of 100 ℃, 120 ℃ and 150 ℃, carry out the heat treated (back baking) of 1 hour, 1 hour and 3 hours respectively; Thus, the thickness that forms the opening (through hole forms and uses opening) 48 of the dimensional accuracy with the φ 85 μ m that are equivalent to photomask is the interlayer resin insulating layers (2 layers of formation) 50 (with reference to the operation (H) of Fig. 5) of 35 μ m.Have again, expose tin coating (not shown) on ground, the opening that becomes through hole 48 tops.

The substrate that (10) will form opening 48 flooded in chromic acid 19 minutes; Dissolving is also removed the epoxy particles that has interlayer resin insulating layers 50 surfaces; Thus; Make the surface coarsening (with reference to the operation (I) of Fig. 5) of this interlayer resin insulating layers 50, then, in neutralization solution (SPRAY society system), wash behind the dipping.

And then, through having handled the surface of this substrate of (the alligatoring degree of depth 6 μ m) and apply the palladium catalyst and handle, the surface of interlayer resin insulating layers 50 and through hole are examined with the internal face formation catalyst of opening 48 to carrying out asperitiesization.

(11) substrate is immersed in the plated by electroless plating aqueous solution of following composition, forming thickness at whole asperities is the non-cathode copper electroplating film 52 (with reference to the operation (J) of Fig. 5) of 0.6 μ m,

[the plated by electroless plating aqueous solution]

EDTA 150g/l

Copper sulphate 20g/l

HCHO 30g/l

NaOH 40g/l

α, α '-bipyridine 80g/l

PGE 0.1g/l

[plated by electroless plating condition]

Under 70 ℃ solution temperature, carried out 30 minutes

(12) stick commercially available photosensitive dry film on the non-cathode copper electroplating film 52 that in above-mentioned (11), forms, put mask again, with 100mJ/cm ²Intensity exposure, the sodium carbonate with 0.8% carries out development treatment, formation thickness is the plating etchant resist 54 (with reference to the operation (K) of Fig. 5) of 15 μ m.

(13) then, under following condition, carry out the cathode copper plating to not forming the part of electroplating etchant resist, forming thickness is the cathode copper electroplating film 56 (with reference to the operation (L) of Fig. 5) of 15 μ m.

[the metallide aqueous solution]

Sulfuric acid 180g/l

Copper sulphate 80g/l

Additive (ATOTEX JAPAN system, KAPARASIDO GL)

1ml/l

[metallide condition]

Current density 1A/dm ²

30 minutes time

The temperature room temperature

(14) with 5% KOH peel off removed the plating etchant resist after; Mixed liquor with sulfuric acid and hydrogen peroxide carries out etch processes to the plated by electroless plating film under this plating etchant resist 52 again; And its dissolving removed, forming by non-cathode copper electroplating film 52 is

conductor circuit

58U, 58D and through hole 60U, the 60D (with reference to the operation (M) of Fig. 6) of 18 μ m with the thickness that cathode copper electroplating film 56 forms.

(15) carry out and (6) same processing, form the alligatoring face 62 that forms by Cu-Ni-P on the surface of

conductor circuit

58U, 58D and through

hole

60U, 60D, and then, Sn displacement (with reference to the operation (N) of Fig. 7) is carried out on this surface.

(16), and then form the conductor circuit on upper strata through carrying out the operation of above-mentioned (7)～(15) repeatedly.That is, use spin coated machine insulation resin agent between the overlay of the two sides of substrate 30 (lower floor uses), form insulating compound layer 144.In addition, use the spin coated machine on this insulating compound layer 144, to apply photosensitive adhesive (upper strata is used), form bond layer 146 (with reference to the operation (O) of Fig. 7).Two sides at the substrate 30 that has formed insulating compound layer 144 and bond layer 146; Bonding photomask; And make public, develop; Formation has the interlayer resin insulating layers 150 of opening (through hole forms with opening 148), then, this interlayer resin insulating layers 150 is made asperities (with reference to the operation (P) of Fig. 7).After this, on the surface of this substrate 30 that has carried out this asperities processing, form non-cathode copper electroplating film 152 (with reference to the operation (Q) of Fig. 8).Next, after plating etchant resist 154 is set on the non-cathode copper electroplating film 152, do not forming formation cathode copper electroplating film 156 (with reference to the operations (R) of Fig. 8) on the part of etchant resist.Then, with KOH peel off remove electroplate etchant resist 154 after, the plated by electroless plating film 152 under this platings etchant resist 154 is removed in dissolving, formation conductor circuit 158U, 158D and through hole 160U, 160D (with reference to the operation (S) of Fig. 8).Then, form alligatoring face 162, on the surface of this alligatoring face 162, form roughened layer 162 (operation 9 (T) of Fig. 9) again on the surface of conductor circuit 158 and through hole 160.But the alligatoring face 162 that surface at this conductor circuit 158 and through hole 160 is not formed carries out the Sn displacement.

(17) apply the thick above-mentioned D. of 45 μ m on the two sides of the substrate 30 that obtains from above-mentioned (16) solder resist composition 70 α have been described.Then, after 70 ℃ of 20 minutes and 70 ℃ of dried of 30 minutes, the photomask (not shown) that the bonding thickness that is decorated with circular pattern (sheltering pattern) is 5mm is with 1000mJ/cm ²The ultraviolet exposure of intensity carries out the DMTG development treatment.Then; Under the condition of 80 ℃, 100 ℃, 120 ℃ and 150 ℃, carry out the heat treated of 1 hour, 1 hour, 1 hour and 3 hours respectively, be formed on the solder mask (thickness 20 μ m) 70 (with reference to the operation (U) of Fig. 9) that weld zone part (comprising through hole and contact on every side) has opening (aperture 200 μ m) 71.

(18) secondly, with this substrate 30 by 2.31 * 10 ^-1The nickel chloride of mol/l, 2.8 * 10 ^-1The inferior sodium phosphate of mol/l, 1.85 * 10 ^-1Dipping is 20 minutes in the non-electrolytic nickel electroplate liquid of the PH=4.5 that the lemon sodium of mol/l constitutes, and forming thickness at peristome 71 is the nickel electrodeposited coating 72 of 5 μ m.And then, under 80 ℃ condition, with this substrate 30 by 4.1 * 10 ^-2The potassium auricyanide of mol/l, 1.87 * 10 ^-1The ammonium chloride of mol/l, 1.16 * 10 ^-1The natrium citricum of mol/l and 1.7 * 10 ^-1 Flood 7 minutes 20 seconds in the non-electrolytic gold plating bath that the inferior sodium phosphate of mol/l constitutes; On nickel coating, forming thickness is the Gold plated Layer 74 of 0.03 μ m; Thus, at through

hole

160U, 160D and conductor circuit 158U, the last formation weld zone 75U of 158D, 75D (with reference to Fig. 1).

(19) then, on the peristome 71 of solder mask 70, brush soldering paste, and under 200 ℃ condition, reflux (reflow), thus, form pedestal (welding body) 76U, 76D, form base plate for packaging 100 (with reference to Fig. 1) at last.

Have again, in above-mentioned example, show the example of the base plate for packaging that utilizes the formation of half additive method, but formation of the present invention also is applicable to the base plate for packaging that utilizes full additive method to form certainly.

In the 1st example; Between the conductor circuit 58U that forms between interlayer resin insulating layers 50 and the interlayer resin insulating layers 150, form virtual pattern 58M, between the internal layer copper figure 34D that forms on the chip substrate 30 or between outermost layer conductor circuit 158U, form virtual pattern 58M but also can replace.

As stated; In the base plate for packaging of the 1st example, between the conductor circuit of the holding wire of IC chip one side that forms base plate for packaging, form virtual pattern, increase the metal section and part of IC chip one side of base plate for packaging; Adjust the ratio of the metal section and part of this IC chip one side and motherboard one side; Therefore, in the manufacturing and use of base plate for packaging, warpage can not take place.

(the 2nd example)

The formation of the base plate for packaging of the 2nd example of the present invention is described with reference to Figure 10～Figure 12.Figure 10 illustrates the sectional view of the base plate for packaging of the 2nd example.Figure 11 (A) illustrates the plane of base plate for packaging; Figure 11 (B) illustrates the bottom surface of the IC chip that is installed on this base plate for packaging, and Figure 12 is illustrated in the cross section that under the state of IC chip 80 device on base plate for packaging shown in Figure 10 base plate for packaging is installed in the state on the motherboard 90.This base plate for packaging that kind shown in figure 12; Be provided with above and be used for the pedestal 76U that is connected with weld zone 82 1 sides of IC chip 80; Below a side be provided with and be used for the weld zone 76D that is connected with the pedestal 92 of motherboard 90, play between IC chip 80 and motherboard 90, to transmit signal etc. and the power supply that comes from motherboard supplied with and carry out relaying.

That kind shown in figure 10, on the chip substrate 30 of base plate for packaging with below formation become internal layer copper figure 34U, the 34D of ground plane.In addition, get involved conductor circuit 58U and the through hole 60U that interlayer resin insulating layers 50 forms as holding wire, through hole 60 these interlayer resin insulating layers 50 of perforation on the upper strata of the 34U of internal layer copper figure.On the upper strata of conductor circuit 58U, form outermost layer conductor circuit 158U, virtual pattern 159 and connect the through hole 160U of this interlayer resin insulating layers 150 through interlayer resin insulating layers 150.This virtual pattern 159 is in the periphery of conductor circuit 158U shown in Figure 11, promptly form along the periphery of base plate for packaging.On this conductor circuit 158U and through hole 160U, form the weld zone 75U that supports pedestal 76U.Here, the diameter of the weld zone 75U of IC chip one side is 120～170 μ m.

On the other hand, the conductor circuit 58D that the upper strata of the ground plane of side (internal layer copper figure) 34D forms as holding wire through interlayer resin insulating layers 50 below chip substrate 30.Upper strata at this conductor circuit 58D; Form outermost layer conductor circuit 158D and the through hole 160D that connects this interlayer resin insulating layers 150 through interlayer resin insulating layers 150, on this conductor circuit 158D and through hole 160D, form the weld zone 75D that supports pedestal 76D.Here, the diameter of the weld zone 75D of motherboard side is 600～700 μ m.

Figure 11 (A) is the plane graph of base plate for packaging 200, promptly is that the A of Figure 10 vows view.Here, the X2-X2 longitudinal section of suitable Figure 11 of Figure 10 (A).Like Figure 11 (A) and shown in Figure 10,, form the virtual pattern 159 of width 10mm in the lower floor of solder mask 70 in the periphery of the conductor circuit 158U that constitutes holding wire.Here, so-called virtual pattern is meant the existence that does not have electrical connection or capacitor etc., only is the figure on the mechanical sense.

Identical with the base plate for packaging of the above-mentioned prior art of Figure 23, in the base plate for packaging of the 2nd example, the weld zone 76U little (diameter is 120～170 μ m) of the surface (top) of its IC chip 80 1 sides configuration is so the ratio that the weld zone metal section and part accounts for is little.On the other hand, the weld zone 75D big (diameter is 600～700 μ m) of the surface (following) of motherboard 90 sides configuration is so the ratio that metal section and part accounts for is big.Here; In the base plate for packaging of this example, form virtual pattern 159 in the periphery of the outermost layer conductor circuit 158U of the IC of base plate for packaging chip one side, so; The metal section and part that leans on the IC chip side of base plate for packaging has increased; Thereby adjusted the ratio of the metal section and part of this IC chip one side and motherboard one side, simultaneously, improved the mechanical strength of base plate for packaging periphery because of the effect of metal virtual pattern 159; After in the manufacturing and use of the base plate for packaging stated, warpage can not take place in base plate for packaging.

Figure 11 (A) illustrates the plane graph (A of Figure 10 vows view) of completed base plate for packaging, and Figure 11 (B) illustrates the ground plan of IC chip.Make this base plate for packaging 100 under the state that loads IC chip 80, pass through reflow ovens, shown in figure 12, through pedestal 76U this IC chip is installed.Then, the base plate for packaging 100 that the IC chip has been installed is installed on the motherboard 90, makes it pass through reflow ovens, carry out of the installation of this base plate for packaging 100 thus to motherboard 90.

The 2nd example～after the manufacturing approach of base plate for packaging of the 5th example stated the same with above-mentioned the 1st example of explaining with reference to Fig. 3～Fig. 9, its explanation of Therefore, omited.

Have again; In above-mentioned the 2nd example; Though be on interlayer resin insulating layers 150 outermost conductor circuit 158U around formed virtual pattern 159, also can replace the internal layer copper figure 34D that forms on the chip substrate 30, or conductor circuit 58U between interlayer resin insulating layers 50-interlayer resin insulating layers 150 around form virtual pattern 159.

In the base plate for packaging of the 2nd example of above explanation; Around the conductor circuit of the IC of base plate for packaging chip one side, form virtual pattern; The metal section and part of IC chip one side of base plate for packaging has increased; Thereby adjusted the ratio of the metal section and part of this IC chip one side and motherboard one side, in the manufacturing and use of base plate for packaging, warpage can not take place in base plate for packaging.

(the 3rd example)

The formation of the base plate for packaging of the 3rd example of the present invention is described with reference to Figure 13.

Formation forms the internal layer copper figure 34D as holding wire below as the internal layer copper figure 34U of holding wire on the chip substrate 30 of base plate for packaging 300.In addition, the conductor circuit 58U that forms as bus plane through interlayer resin insulating layers 50 on the upper strata of internal layer copper figure 34U.On the upper strata of this conductor circuit 58U, form outermost conductor circuit 158U and the through hole 160U that connects this interlayer resin insulating layers 150 through interlayer resin insulating layers 150, on this through hole 160U, form pedestal 76U.That is, in the 3rd example, on the through hole 160U that is installed on the conductor circuit 58U that forms bus plane, form pedestal 76U, this bus plane directly is connected with outside weldings salient point (not shown).

On the other hand, the upper strata of the holding wire of a side below chip substrate 30 (internal layer copper figure) 34D becomes the conductor circuit 58D of ground plane through interlayer resin insulating layers 50.On the upper strata of this conductor circuit 58U, form outermost conductor circuit 158D and the through hole 160D that connects this interlayer resin insulating layers 150 through interlayer resin insulating layers 150.On this through hole 160D, form pedestal 76D.That is, in this example, on the through hole 160D that is installed on the conductor circuit 58D that forms ground plane, form pedestal 76D, this ground plane directly is connected with outside weldings salient point (not shown).

The formation of this example is; With the conductor circuit 58U of the downside that is configured in the interlayer resin insulating layers 150 that supports outermost

layer conductor circuit

158U, 158D, 58D as bus plane, ground plane; Through

hole

160U, 160D directly are connected this

conductor circuit

58U, 58D is last; On this through hole,

form pedestal

76U, 76D, thus bus plane or ground plane with do not need being connected of pedestal to connect up, therefore; Can not receive the influence that causes because of the noise that overlaps in the wiring, can be reduced in and give and accept signal between integrated circuit and the motherboard and the power supply that comes from motherboard one side supplied with the The noise when carrying out relaying.In addition, just because of some place does not need wiring, so can seek the densification of circuit board.Have again; In the multi-layer printed wiring base plate of this example; Respectively with

conductor circuit

58U, 58D as bus plane and ground plane; But conductor circuit 58U or conductor circuit 58D also can be in one decks, with the formation that pieces together of conductor circuit that plays the bus plane effect and the conductor circuit that plays the ground plane effect.

Next the multi-layer printed wiring base plate of the variation of the 3rd example is described with reference to Figure 14.

Figure 14 is the sectional view of formation of the multi-layer printed wiring base plate of expression the 2nd example of the present invention.On chip substrate 230 with below formation become internal layer copper figure 234U, the 234D of ground plane.That is, utilize ground plane (internal layer copper figure) 234U and ground plane (internal layer copper figure) 234D that substrate 230 is clipped in the middle to form capacitor.

In addition, the conductor circuit 258U that forms as holding wire through interlayer resin insulating layers 250 on the upper strata of internal layer copper figure 234U.On the upper strata of this conductor circuit 258U, form the through hole 360U that connects interlayer resin insulating layers 350, on this through hole 360U, form pedestal 376U.

On the other hand, the upper strata of the ground plane of side below substrate 230 (internal layer copper figure) 234D becomes the conductor circuit 258D of holding wire through interlayer resin insulating layers 250.On the upper strata of this conductor circuit 258D, become the conductor circuit 388D of bus plane through interlayer resin insulating layers 350.On the upper strata of this conductor circuit 388D, form the through hole 380D that connects interlayer resin insulating layers 390, on this through hole 380D, form pedestal 376D.That is, in this example, on the through hole 380D that is installed on the conductor circuit 388D that forms bus plane, form pedestal 376D, this bus plane directly is connected with outside weldings salient point (not shown).

The formation of the variation of the 3rd example is; Through hole 380D directly is connected on the conductor circuit 388D that constitutes bus plane; On this through hole, form pedestal 376D; So bus plane with do not need being connected of pedestal the wiring, therefore, can not receive the influence that causes because of the noise that overlaps in the wiring.

As stated, in the base plate for packaging of the 3rd example, with the inner conductor circuit of the insulating barrier lower floor that supports the outermost layer conductor circuit as bus plane and/or ground plane; Through hole directly is connected on the 2nd conductor circuit; On this through hole, form pedestal, thus bus plane or ground plane with do not need being connected of pedestal the wiring, therefore; Can not receive the influence that causes because of the noise that overlaps in the wiring; In addition, just because of some place does not need wiring, so can seek the densification of circuit board.

In addition, in the base plate for packaging of the 3rd example, with the 2nd conductor circuit of the downside that is configured in the 2nd interlayer resin insulating layers that supports the outermost layer conductor circuit as bus plane and/or ground plane; Through hole directly is connected on the 2nd conductor circuit; On this through hole, form pedestal, thus bus plane or ground plane with do not need being connected of pedestal the wiring, therefore; Can not receive the influence that causes because of the noise that overlaps in the wiring; In addition, just because of some place does not need wiring, so can seek the densification of circuit board.

(the 4th example)

The formation of the base plate for packaging of the 4th example of the present invention is described with reference to Figure 15.On the chip substrate 30 of base plate for packaging 400 with below formation become internal layer copper figure 34U, the 34D of ground plane.In addition, become the conductor circuit 58U of holding wire through interlayer resin insulating layers 50, and connect this interlayer resin insulating layers 50 formation through hole 60U on the upper strata of internal layer copper figure 34U.On the upper strata of this conductor circuit 58U, form outermost layer conductor circuit 158U and the through hole 160U that connects this interlayer resin insulating layers 150 through interlayer resin insulating layers 150, on this conductor circuit 158U, through hole 160U, form the weld zone 75U that supports pedestal 76U.Here, the diameter of the weld zone 75U of IC chip one side is 133～177 μ m.

On the other hand, the upper strata of the internal layer copper figure 34D of a side below substrate 30 becomes the conductor circuit 58D of holding wire through interlayer resin insulating layers 50.On the upper strata of this conductor circuit 58D, form outermost layer conductor circuit 158D and the through hole 160D that connects this interlayer resin insulating layers 150 through interlayer resin insulating layers 150, on this conductor circuit 158D, through hole 160D, form the weld zone 75D that supports pedestal 76D.The diameter of the weld zone 75D of this motherboard one side is 600 μ m.In addition, last ground connection (electrode) layer that disposes of internal layer copper figure 34U, the 34D of subtend configuration utilizes two

internal layer copper

34U, 34D to form capacitor in that chip substrate 30 is clipped in the middle.

Figure 16 (A) is the plane graph of the internal layer copper figure 34U of formation on chip substrate 30.On this internal layer copper figure 34U, form and be used for contact-weld zone 41 of being connected with lower floor one side with upper strata one side.Figure 16 (B) is the figure after the contact-weld zone in the zone shown in the B among Figure 16 (A) 41 is amplified.The X3-X3 cross section of Figure 16 (B) is equivalent to the X3-X3 cross section of Figure 15 (B).

Such shown in Figure 16 (B); This contact-weld zone 41 is that the weld zone 41b that the contact 41a of through hole shown in Figure 15 36 is connected with through hole 60U with the interlayer resin insulating layers 50 that connects the upper strata is made of one formation, the buffer insulation band 43 that disposes the about 200 μ m of width on every side in this contact one weld zone 41.

Here, in the base plate for packaging of this example, such shown in Figure 16 (B); Contact 41a and weld zone 41b are made of one, and this contact 41a is not connected through wiring with weld zone 41b, so; Shortened the transfer path between the conductor circuit 58U of upside of lower floor (the conductor circuit 58D of lower floor's one side of chip substrate 30) and upper strata (interlayer resin insulating layers 50); The transfer rate of signal can be improved, simultaneously, resistance value can be reduced.In addition; Because of this contact 41a is not connected through wiring with weld zone 41b; So not as the base plate for packaging of the prior art shown in above-mentioned Figure 24 (A); Stress concentrate on connect up and contact and wiring and weld zone between connecting portion, therefore, the crack that can not produce owing to concentrating of stress and in base plate for packaging, not breaking.At this, the internal layer copper figure 34U to chip substrate 30 upsides illustrates and explains, and the formation of the internal layer copper figure 34D of downside too.

Next, the base plate for packaging of the variation of example of the present invention is described with reference to Figure 17 and Figure 18.In above-mentioned the 4th example shown in Figure 15, in last ground plane (electrode layer) 34G and the contact-weld zone 41 of forming of the internal layer copper figure 34U, the 34D that are formed at chip substrate 30 two sides.Different therewith, the same with the situation shown in Figure 16 (A) in the 2nd example, in last bus plane (electrode layer) 58G and the contact-weld zone 61 of forming of the conductor circuit 58U, the 58D that are formed at interlayer resin insulating layers 50 upper stratas.

Figure 17 is the sectional view of base plate for packaging of the variation of the 4th example, and Figure 18 (A) is the plane graph of the conductor circuit 58U that on interlayer resin insulating layers 50, forms.On this conductor circuit 58U, form bus plane 58G and the contact-weld zone 61 that is used for being connected with lower floor one side with upper strata one side.Figure 18 (B) is the figure after the contact-weld zone in the zone shown in the B among Figure 18 (A) 61 is amplified.The X4-X4 cross section of Figure 18 (B) is suitable with the X4-X4 cross section of Figure 17.

That kind shown in figure 17; This contact-weld zone 61 is that the weld zone 61b that the contact 61a of the through hole 60U that is connected with internal layer copper figure 34U is connected with through hole 160U with the interlayer resin insulating layers 150 that connects the upper strata is made of one formation; Such shown in Figure 18 (B), the buffer insulation band 63 that disposes the about 200 μ m of width on every side in this contact-weld zone 61.

In the base plate for packaging of the variation of the 4th example; Contact 61a and weld zone 61b are made of one, and this contact 61a is not connected through wiring with weld zone 61b, so; Shortened the transfer path between the conductor circuit 158U of upside of lower floor (the internal layer copper figure 34U of upper strata one side of chip substrate 30) and upper strata (interlayer resin insulating layers 150); The transfer rate of signal can be improved, simultaneously, resistance value can be reduced.In addition; Because of this contact 61a is not connected through wiring with weld zone 61b; So not as the base plate for packaging of the prior art shown in above-mentioned Figure 24 (A); Stress concentrate on connect up and contact and wiring and weld zone between connecting portion, therefore, the crack that can not produce owing to concentrating of stress and in base plate for packaging, not breaking.

Have again, in above-mentioned example, be made of one forming circular contact and weld zone, but, also can the contact and the weld zone of various shapes such as ellipse, polygon be made of one for the present invention.

As stated, in the base plate for packaging of the 4th example, contact is not connected through wiring with the weld zone; So, shortened the transfer path between the conductor circuit (conductor layer) on lower floor and upper strata, can improve the transfer rate of signal; Simultaneously, can reduce resistance value.In addition, because of this contact is not connected through wiring with the weld zone, so stress do not concentrate on connect up and contact and wiring and weld zone between connecting portion, therefore, the crack that can not produce owing to concentrating of stress and in base plate for packaging, not breaking.

(example 5)

The formation of the base plate for packaging of the 5th example of the present invention is described with reference to Figure 19 and Figure 20.It is shown in figure 20 that Figure 19 illustrates the base plate for packaging 500 of the 5th example in its cross section, constitutes the form of so-called integrated circuit encapsulation, loads in the above under the state of IC chip 80 it is installed on the motherboard 90.

On the chip substrate 30 of base plate for packaging with below on become internal layer copper figure 34U, the 34D of ground plane.In addition, become the conductor circuit 58U of holding wire through interlayer resin insulating layers 50, and connect this interlayer resin insulating layers 50 formation through hole 60U on the upper strata of internal layer copper figure 34U.On the upper strata of this conductor circuit 58U, form outermost layer conductor circuit 158U and the through hole 160U that connects this interlayer resin insulating layers 150 through interlayer resin insulating layers 150, on this conductor circuit 158U, through hole 160U, form the weld zone 75U that supports pedestal 76U.Here, the diameter of the weld zone 75U of IC chip one side is 133～177 μ m.

On the other hand, the upper strata of the ground plane of a side below chip substrate 30 (internal layer copper figure) 34D becomes the conductor circuit 58D of holding wire through interlayer resin insulating layers 50.On the upper strata of this conductor circuit 58D, form outermost layer conductor circuit 158D and the through hole 160D that connects this interlayer resin insulating layers 150 through interlayer resin insulating layers 150, on this through hole 160D, form the weld zone 75D that supports pedestal 76D.Here, the diameter of the weld zone 75D of motherboard one side is 600 μ m.

In the base plate for packaging of the 5th example; Through on through hole 160D, forming the pedestal 76D of motherboard 60 1 sides, pedestal directly is connected with through hole, so; Even the crack appears in base plate for packaging, between pedestal 76D and through hole 160D, can not break yet.Promptly; In the base plate for packaging 600 of the prior art shown in above-mentioned Figure 23 (B), 378 pedestal 375D is connected with through hole 360 through connecting up, this weld zone 375D goes up and places pedestal 376D; So; When crack L2 appears in inside, because of the event of this crack L2 wiring of connecting through hole 376D and pedestal 376D is sometimes broken off, the disconnection that is connected of pedestal 376D and through hole 360D.In contrast, in the base plate for packaging of the 5th example,, between pedestal 76D and through hole 160D, can not break because of the crack even the crack occurs yet.

Next, explain IC chip 80 is installed to the situation on the base plate for packaging 500 of the 5th example shown in Figure 19.Shown in figure 20; The weld zone 76U that IC chip 80 is placed on base plate for packaging 500 goes up and makes the weld zone 82 of this IC chip 80 corresponding with it; Make it pass through heating furnace; The weld zone 76U of base plate for packaging 500 is melted on the weld zone 82 of IC chip 80, and therefore, base plate for packaging 500 has just linked together with IC chip 80.

Then, the solder flux that when utilizing heating to make weld zone 76U be melted on the weld zone 82 and it is solidified, oozes out is carried out purified treatment.At this,, remove deflux with the gap of vinyl chloride organic solvents such as (chloroethene) injection base plate for packaging 500 and IC chip 80.Then, resin is filled in the gap of base plate for packaging 500 and IC chip 80, carries out resin fill.Simultaneously, entire I C chip 80 is carried out moulding, arrive this, the installing of IC chip 80 with resin.

Next, base plate for packaging 500 is installed on the motherboard 90.The weld zone 92 of motherboard 90 and the weld zone 76D of base plate for packaging 500 are placed accordingly; Make it pass through heating furnace; The weld zone 76U of base plate for packaging 500 is melted on the weld zone 82 of IC chip 80, and therefore, base plate for packaging 500 has just linked together with IC chip 90.Then,, resin 94 is filled in the gap of base plate for packaging 500 and motherboard 90, carries out resin-sealedly, install to this as shown in Figure 20.

Below, the base plate for packaging 501 of the variation of the 5th example of the present invention is described with reference to Figure 20 and Figure 21.

In the base plate for packaging 500 of above-mentioned the 5th example shown in Figure 19,1 through hole 160D goes up and places 1 pedestal 76D.Different therewith, in the base plate for packaging 500 of the 5th example, that kind shown in figure 21 is placed 1 pedestal 276 on a plurality of (3) through hole 260,260,260.Promptly; Such shown in Figure 22 suitable (the X5-X5 hatching of the suitable Figure 21 of X6-X6 hatching among Figure 22) with the X5-X5 cross section of Figure 21; Through hole 260 be by 3 each other near through hole constitute; On the shared contact 260a of this 3 through holes 260, form nickel coating 72 and Gold plated Layer 74, thereby form 1 big contact 275.And, on this big contact 275, place big pedestal 276.

In the base plate for packaging 501 of the variation of the 5th example; Form on through hole 260 through pedestal 276, pedestal 276 directly is connected, therefore with through hole 260; Even for example in base plate for packaging 501, the crack occurs, can not break between pedestal 276 and the through hole 260 yet.In addition, because of pedestal 276 forms on a plurality of through holes 260,260,260, even 1 and conductor circuit 58D disconnection in a plurality of through hole also can utilize remaining through hole that pedestal 276 is connected with conductor circuit 58D, so, can realize anti-invalidation functions.

In addition, as stated, the diameter of the weld zone 75U of IC chip 80 1 sides is 133～170 μ m, and the diameter of the weld zone 75D of motherboard one side is 6000 μ m, and size differs 4～5 times, and the big weld zone 75D that on 1 through hole, forms motherboard one side is very difficult.Therefore, in the base plate for packaging 501 of the variation of the 5th example, pedestal 276 is formed on a plurality of through holes 260,260,260, form big pedestal according to this.Here, in above-mentioned variation, on 3 through holes, form 1 pedestal, but also can on the through hole more than 2 or 4, form 1 pedestal.

As stated, in the base plate for packaging of the variation of the 5th example, on through hole, form through making pedestal; Pedestal directly is connected with through hole; Therefore, even the crack appears in base plate for packaging, can not break between pedestal 276 and the through hole 260 yet.In addition,,, also can utilize remaining through hole that pedestal is connected with through hole even 1 in a plurality of through hole for example breaks off in inside because of pedestal 276 forms on a plurality of through holes, so, can realize anti-invalidation functions.This external cause pedestal forms on a plurality of through holes, so can form the weld zone bigger than through hole.

In above-mentioned example, enumerated base plate for packaging has been directly installed on example on the motherboard, but, also can use base plate for packaging of the present invention with being well suited for for base plate for packaging being connected the situation on the motherboard through daughter board.

Claims

1. base plate for packaging forms the multi-layer conductive circuit and forms through the multilayer interlayer resin insulating layers by core substrate with on the two sides of above-mentioned core substrate,

Be electrically connected through the through hole that is formed at above-mentioned interlayer resin insulating layers between the above-mentioned conductor circuit of mutually different layer,

On the surface that IC chip one side is installed and the surface that is connected to other substrate one sides, form pedestal, between this is connected to surface and this other substrates of the side on other substrates, carry out resin-sealedly, it is characterized in that,

On each sets of vias of forming by a plurality of above-mentioned through holes, form one this be connected to the pedestal of the side surface on other substrates.

2. base plate for packaging according to claim 1 is characterized in that, on above-mentioned through hole, is formed with the weld zone of the above-mentioned pedestal of supporting.

3. base plate for packaging according to claim 1 and 2 is characterized in that, is formed with roughened layer on the surface of above-mentioned through hole.