CN1912849A - Chip dynamic tracing method of microprocessor - Google Patents
Chip dynamic tracing method of microprocessor Download PDFInfo
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- CN1912849A CN1912849A CN 200610030754 CN200610030754A CN1912849A CN 1912849 A CN1912849 A CN 1912849A CN 200610030754 CN200610030754 CN 200610030754 CN 200610030754 A CN200610030754 A CN 200610030754A CN 1912849 A CN1912849 A CN 1912849A
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Abstract
This invention relates to an on-chip tracing method of a microprocessor, which sets some positions as viewing points in the execution process of a program by an on-chip tracer (OCT), then traces, records and outputs the information of the assigned internal registers at these points used in the field of 8051 serial microprocessor or other microprocessor fields.
Description
Technical field
The present invention relates to dynamic tracking method on a kind of sheet of microprocessor, can be applicable to the chip microprocessor of 8051 series, also can be applicable to other microprocessors, field of microprocessors.
Background technology
Dynamic tracking (Dynamic Trace) is meant the trace information of logging program operation in real time, and these information are sent to the process that outside debugging acid is analyzed and debugged by certain means.In the debugging performance history of embedded system that with the microprocessor is core, catch high speed signal for convenience and processor is debugged, such as carrying out debugging, recovery, modification etc., the track when needing the recording processor high-speed cruising according to history of program execution.Therefore, in equipment such as most logic analyser and in-circuit emulator, all be useful on the tracking unit of dynamic tracking processor running orbit, be used for monitoring the various internal informations of processor, like this debugging person just easily trace routine carry out flow process, search program mistake, reconfiguration program running orbit etc.But, in the common way that realizes dynamic tracking, all need the storer of a larger capacity to keep in various tracked processor internal informations.Therefore, for dynamic tracking on the sheet, can increase the difficulty of design and production cost etc. at the inner integrated storer that is used for dynamic tracking of processor.
Summary of the invention
The object of the present invention is to provide dynamic tracking method on a kind of sheet of microprocessor.By tracking module (On-Chip Tracer:OCT) on the independently sheet that is integrated in processor inside, some positions that debugging person is concerned about in can program process are set to observation point (Watchpoint), and the information of these positions followed the tracks of, writes down and real-time output, to realize the purpose of dynamic tracking.And whole process do not need special trace buffer unit, only needs a spot of register just can satisfy the temporary requirement of data.
For achieving the above object, design of the present invention is as follows:
Make up an on-chip tracer (On-Chip Tracer:OCT) that is integrated in processor inside, is observation point by this module with some position mark in the program process, then in the process that program is carried out, the address of every instruction and these observation point compared detect observation point.If there is observation point to be detected, CPU operation suspension then waits for that the OCT module analyzes the bit string line output of the internal register of this given viewpoint appointment to the debugging acid of outside.If data output finishes the then execution of notification processor automatic recovery program.If run into next observation point, just repeat tracking, record and the output procedure of front again.And so forth, be finished or debugging person suspends or stop this dynamic tracking process up to program.
According to above-mentioned design, the present invention adopts following technical proposals:
Dynamic tracking method on a kind of sheet of microprocessor, it is characterized in that by an on-chip tracer (OCT), some position in the program process is set to observation point (Watchpoint), then the information of the internal register of these given viewpoint appointments is followed the tracks of, is write down and real-time output; Its concrete steps are:
A., an asynchronous serial transmitting-receiving submodule is set, to realize communicating by letter of OCT module and processor outside;
B. set a debug command register DBGCMD, store the dynamic tracking debug command that debugging person is sent to the OCT module;
C. set n observation point address register WPi (i=0～n-1), store the first address that debugged person is set to the program of observation point;
D. set internal register and select sign register SFR_SEL, be stored in the selection signal of the internal register of the tracked and record of each given viewpoint;
E. set a present instruction first address register PCC, store the first address of the current instruction of carrying out of CPU automatically;
F. start the dynamic tracking process by " starting the dynamic tracking order ", in the process of dynamic tracking, the OCT module is according to circumstances carried out the dynamic tracking operation then, and sets coherent signal.
The above-mentioned method that an asynchronous serial transmitting-receiving submodule is set is:
This serial transmitting-receiving submodule adopts semiduplex asynchronous serial communication pattern, carries out serial communication by 1 signal wire and processor outside, and transmission and reception are two independently processes.The fundamental purpose of receiving unit is to receive the various debug commands that debugging acid sends, and data and the program address relevant with each order, and the purpose that sends then is the content strings line output with the selected internal register that goes out of each given viewpoint.Simultaneously, receive and process of transmitting has all adopted the data frame format of 1 position of rest (1 level)+valid data position+1 start bit (0 level) (to see Fig. 2 (a) and Fig. 3) respectively.
Some signals and the register relevant with serial communication are defined as follows (see figure 4):
A.NEA: the external pin that asynchronous serial transmitting-receiving submodule and processor outside communicate then is divided into NEA_I (serial data input end) and NEA_O (serial data output terminal) in the OCT inside modules;
B.RX_CLK/TX_CLK: the sampling clock when being asynchronous serial transmitting-receiving submodule reception and transmission serial data respectively, frequency all is 1/100 of a processor clock frequency;
C.RX_SHIFT/TX_SHIFT: the serial-shift pulse when being asynchronous serial transmitting-receiving submodule reception and transmission data respectively, frequency all is 1/8 of RX_CLK/TX_CLK, therefore, the baud rate of communication is 1/800 of a processor operating rate;
D.RX_SHIFTER: receive shift register, reception be each debug command and relevant data and address, data layout is seen Fig. 2;
E.TX_SHIFTER_1: send shift register, transmission be that data layout is seen Fig. 3 in the data of each given viewpoint internal register and the address of this observation point.
The method of an above-mentioned debug command register of setting DBGCMD is:
Definition DBGCMD is one 4 a register, and it is used to store the binary coding of the debug command that debugging acid sends, and the debug command that receives is decoded as control signal corresponding.
DBGCMD can store 8 orders relevant with dynamic tracking, sees Table 1.Wherein, other binary codings of not using among the DBGCMD temporarily keep, and can expand afterwards.
The dynamic tracking order of table 1 DBGCMD storage
| Binary coding | The order symbol | Functional description |
| 0000 | DBG_RST | Under debugging mode, whole microprocessor system is resetted |
| 1010 | WP_SET | Certain bar instruction in the program is set to an observation point |
| 1011 | WP_REMOVE | Remove the observation point of an appointment |
| 1100 | WP_CLR | The observation point that disposable removing is all |
| 0011 | SFR_SET | Be set in each given viewpoint and need internal register tracked and record |
| 1101 | D_DBG | Start the dynamic tracking process |
| 1110 | D_DBG_PAUSE | Suspend the dynamic tracking process |
| 1111 | D_DBG_Stop | Stop the dynamic tracking process |
Above-mentioned setting n observation point address register WPi (method of i=0～n-1) is:
Definition WPi (i=0～n-1) be the register of individual 16 of n, storage be the first address that is set to the instruction of observation point.After the system reset, the value of this n observation point address register all is a high value.
The OCT module is provided with or removes observation point according to following three kinds of situations:
A) if receive WP_SET order, 16 bit address that the OCT module just will receive with this order are stored in (order of storage is from WP0, arrives WPn-1 at last) in the WPi register as the address of an observation point.If the observation point that debugging person is provided with surpasses n, then the address of n+1 observation point just overrides the 1st observation point, and n+2 observation point overrides the 2nd, and the like.
B) if receive the WP_REMOVE order, the OCT module will be compared 16 bit address that receive this moment with the address that before was set at observation point, will remove with the observation point of this matching addresses then.
C) if receive the WP_CLR order, the OCT module is just with the disposable full scale clearance of all observation point, and the data of the observation point register after being eliminated all are high value.
Internal register of above-mentioned setting selects the method for sign register SFR_SEL to be:
Definition SFR_SEL is the register of a n position, the corresponding according to the order of sequence n of it each internal register commonly used, and it is defined as follows:
| Internal register n selects signal | …… | Internal register 2 is selected signal | |
When receiving selection internal register order SFR_SET, the OCT module just will be stored among the SFR_SEL with the n bit register selection signal (seeing Fig. 2 (d)) that the SFR_SET order receive this moment.If this moment, a certain position of SFR_SEL was 1, then this pairing internal register will be tracked, and the content of this internal register all will be output in each given viewpoint simultaneously.Otherwise if this position is 0, so Dui Ying this internal register does not just need tracked and record.
The method of an above-mentioned present instruction first address of setting register PCC is:
Definition PCC is 1 16 a address register, storage be 16 first addresss of the current instruction of carrying out.Its value is by OCT module automatic setting.After the system reset, the value of PCC is 00h.
The concrete grammar of setting the PCC register is: in the process that program is carried out, in the 1st clock period of every instruction, the value of the program pointer that points to this instruction is delivered in the PCC register.PCC can preserve this address always, when the 1st clock period of next bar instruction arrives, just is updated to new address.
Above-mentionedly in the process of dynamic tracking, according to circumstances carry out dynamic tracking operation and have following three kinds:
If after a. the dynamic tracking process started, the OCT module did not receive other control commands, then the OCT module will compare WPi (i=0～n-1) carry out the detection of observation point with the content of PCC automatically in the process that program is carried out.If detect observation point, the OCT module is just analyzed the bit string line output of the selected internal register of this given viewpoint to outside debugging acid.
The concrete steps that detect observation point and export internal register information are:
A) WP_MATCH: the observation point matched signal, high level is effective;
WP_STOP: observation point coupling stop signal;
Detect the method for observation point and see Fig. 7.In the process that program is carried out, in the 3rd clock period of every instruction, (content of i=0～n-1) compares with present instruction first address register PCC respectively with n observation point address register WPi.As long as have the content of an observation point address register and the content of PCC to mate fully, just explanation has detected an observation point, so the WP_MATCH signal is effective immediately.After the instruction that executes this given viewpoint, CPU also needs to carry out a non-operation instruction NOP to guarantee the integrality of execution process instruction again.Then, in the 2nd clock period of this NOP instruction, the WP_STOP signal is effective, simultaneously, the OCT module all is stored in the value of all selected internal registers that go out in the corresponding temporary register, and not having the content of the selected pairing temporary register of internal register with those then all is 0.In the next clock period after effectively of WP_STOP signal and then, the OCT module enters the preparatory stage of serial transmission.
B) TX_SFR_DATA: the register of storing n internal register data and current observation point first address;
TX_SHIFTER_1: send shift register;
TX_BEGIN: send commencing signal;
CPU_STOP: the signal that stops the CPU work clock.
In the preparatory stage that serial sends, i.e. the 3rd clock period of NOP instruction, the TX_BEGIN signal is effective, and serial transmitting-receiving submodule all leaves the content of n temporary register and the first address of current observation point among the register TX_SFR_DATA according to the order of sequence.Then, TX_SFR_DATA and 1 start bit and 1 position of rest are left in according to the order of sequence send among the shift register TX_SHIFTER_1 again.From the 4th clock period of NOP instruction, the OCT module enters the output stage that serial sends, and sees Fig. 7.Simultaneously, the CPU_STOP signal is effective, and CPU is out of service.
C) TX_END: the end signal of serial output.
At the output stage that serial sends, serial transmitting-receiving submodule is sent the content serial of TX_SHIFTER_1, and low level is preceding output the time, and left end constantly mends 0.When position of rest arrived the low order end of TX_SHIFTER_1, the all-zero signal of position of rest left end was detected by one " full null detector ", so the TX_END signal is effective immediately, the OCT module just stops the serial process of transmitting.See Fig. 4.
After b. if the dynamic tracking process starts, in the process of dynamic tracking, the OCT module receives the order D_DBG_PAUSE that suspends dynamic tracking, then in last clock period of present instruction, the CPU_STOP signal is effective, and CPU is out of service, and total system enters the halted state of dynamic tracking.At this moment, debugging person can come the ruuning situation of routine analyzer according to the processor internal information of the given viewpoint that is detected, thus search program mistake, reconfiguration program flow process etc.
If the current halted state that is in dynamic tracking of system, if debugging person sends the order D_DBG_PAUSE that suspends dynamic tracking once more, then system withdraws from halted state immediately, and reenters the dynamic tracking process.The CPU_STOP signal is invalid immediately simultaneously, and CPU begins to rerun from next bar instruction of previous time-out.
If after c. the dynamic tracking process started, in the process of dynamic tracking, the OCT module received the order D_DBG_STOP that stops dynamic tracking, then system withdraws from the dynamic tracking process immediately, and waits for that debugging person sends new dynamic tracking order.
The present invention compared with prior art, have following outstanding substantive distinguishing features and remarkable advantage: by the dynamic tracking module (OCT) on the sheet, can be set to observation point (Watchpoint) by some key positions in debugging person's program process, trigger the serial transmission by detecting observation point then, the content of this given viewpoint internal register is outputed to outside debugging acid analyze, with tracking and the record of a spot of register realization internal register.The present invention has realized the dynamic tracking to program operation process on the MCU of 8051 series, also can be applicable to other microprocessors and field of microprocessors.
Description of drawings:
Fig. 1 is the workflow diagram of dynamic tracking.
Data frame format diagrammatic sketch when Fig. 2 is serial received.
Data frame format diagrammatic sketch when Fig. 3 is the serial transmission.
Fig. 4 is the inner structure synoptic diagram of serial communication submodule.
Fig. 5 is the inner structure synoptic diagram of tracking module on the sheet (OCT).
Fig. 6 is each of SFR_SEL register and the corresponding relation figure of 24 internal registers.
Fig. 7 is the sequential chart that detects observation point.
Embodiment
Details are as follows in conjunction with the accompanying drawings for a preferred embodiment of the present invention:
Dynamic tracking method on the sheet of this microprocessor, by an on-chip tracer (OCT), adopt following workflow (see figure 1) to realize dynamic tracking to the processor operational process:
1) by the some observation point in debugging person's designated program.In this example, set n=8, totally 8 observation point address register WPi (0～7), therefore, debugging person can be provided with 0～8 observation point arbitrarily.
2) specify in each given viewpoint by debugging person and need internal register tracked and record.It is available to set 24 internal registers commonly used in this example, and the selection of these 24 internal registers is independent mutually, and debugging person can select the internal register of the tracked and record of 1～24 needs according to circumstances.
3) by starting the process that dynamic tracking order D_DBG starts dynamic tracking.In the process of dynamic tracking, CPU normally moves then, just in the beginning of every instruction, all will compare 8 observation point registers and present instruction first address register PCC to detect observation point.
4) in the process of dynamic tracking, if detect observation point, then CPU is out of service immediately, and waits for the content strings line output of OCT module with those selected internal registers of this given viewpoint.Treat that output procedure finishes, CPU resumes operation immediately.
5) in the process of dynamic tracking, if do not detect observation point, then CPU continues operation, and the OCT module continues the dynamic tracking process, is finished or debugging person sends the time-out of dynamic tracking or ceases and desist order up to program.
6) in the process of dynamic tracking, if debugging person sends the order D_DBG_STOP that stops dynamic tracking, then total system withdraws from the dynamic tracking pattern immediately, and waits for that debugging person sends new debug command.
7) in the process of dynamic tracking, if debugging person sends the order D_DBG_PAUSE that suspends dynamic tracking, then system enters halted state, the implementation status that this moment, debugging person can come routine analyzer according to the information of each given viewpoint internal register.If debugging person sends pause command once more, then system withdraws from halted state immediately, and gets back to the dynamic tracking process.
Present embodiment adopts Fig. 2 and data frame format shown in Figure 3 when receiving and send serial data, the data that receive and send all comprise 1 start bit and 1 position of rest, just valid data position difference separately.Simultaneously, the definition start bit is 0 level, and position of rest is 1 level.The definition of the valid data position when receiving and sending is respectively:
1) because the valid data that receive is various dynamic tracking orders (aforesaid table 1 is seen in definition) that debugging acid sends, and data and the program address relevant with each order, therefore, concerning different orders, need the different valid data form of definition, but their valid data figure place all is 28 (not comprising 2 bit flag positions).Each order and the valid data position relevant with this order are defined as follows respectively:
WP_SET/WP_REMOVE order: be provided with and remove the order of specifying observation point, the data bit relevant with these two orders is invalid bit, and 16 bit address then are the addresses of observation point that need be set up or the observation point that need be removed.
The WP_CLR order: remove the order of all 8 observation point, data bit relevant with this order and address bit are all invalid this moment;
SFR_SET order: select each given viewpoint to need the order of the internal register of tracked and record, 8 bit data that receive with this order and 16 bit address are altogether as the selection signal of 24 internal registers;
The D_DBG order: the startup command of dynamic tracking, the data bit that order is relevant is invalid therewith, and 16 bit address then are the start addresses that CPU begins executive routine;
D_DBG_PAUSE/D_DBG_STOP order: the time-out of dynamic tracking and ceasing and desisting order, data bit and the address bit relevant with these two orders are all invalid.
Valid data when 2) sending are formed (see figure 3) by the data of the selected internal register that goes out of each given viewpoint and the address of current observation point.But, in order to guarantee the figure place unanimity of each serial output, those contents that do not have selected internal register are also with complete 0 data output.Therefore, the address that always has 24 internal registers and 1 16 needs output.
In order to realize the serial communication of OCT module and external debug instrument, present embodiment has adopted following asynchronous serial communication structure (see figure 4):
NEA: the pin that serial communication is carried out in communicator module and processor outside;
NEAOE: during serial communication, the enable signal of reception and the multiplexing NEA pin of process of transmitting;
NEA_I/NEA_O: the serial received and the serially-transmitted data end that are the communicator inside modules respectively;
RX_CLK/TX_CLK: the work clock that is reception and process of transmitting respectively;
RX_SHIFT/TX_SHIFT: the serial-shift pulse that is reception and process of transmitting respectively;
RX_SHIFTER/TX_SHIFTER_1: the shift register that is reception and process of transmitting respectively;
RX_START/RX_OVER: the beginning and the end signal that are receiving course respectively;
TX_BEGIN/TX_SEND: the startup and the output signal that are process of transmitting respectively;
DBGCMD/RX_DATA/RX_ADDR: be respectively after receiving course finishes, the temporary register of the debug command that receives, data and address.
TX_SFR_DATA: the register of storing 24 internal register data and current observation point first address.
As can be seen from Figure 4, this serial communication submodule is divided into two independent parts: receiving unit and transmission part.When being in transmit status (TX_BEGIN or TX_SEND signal are effective), the NEAOE signal is (1 level) effectively, and the NEA pin of this moment is as output (being NEA_O), otherwise as if the NEAOE invalidating signal, then NEA is as input (NEA_I).
1) process of Jie Shouing is as follows:
At first, during system reset or after last receiving course finishes, 30 all "1"s signals are written among one 30 the reception shift register RX_SHIFTER.Then, detect from 1 to 0 negative saltus step if receive controller at the NEA_I end, the RX_START signal is just effective immediately, so under the control that receives shift pulse RX_CLK, the data that appear at the NEA_I end are moved into RX_SHIFTER to the right by serial, arrive the low order end of RX_SHIFTER up to start bit 0.At this moment, 0 detecting device detects 0 signal of RX_SHIFTER low order end, to receive signal RX_OVER effective so make, and simultaneously the order, data and the address that receive among the RX_SHIFTER stored into respectively in DBGCMD, RX_DATA and three registers of RX_ADDR.
In addition, in the sampling NEA_I end signal, adopted 3 to get 2 decision method and improve the accuracy and the anti-interference of reception.Just use with the sampling clock CLK_SAMP (frequency is 8 times of shift pulse RX_SHIFT) of RX_CLK same frequency in each middle continuous sampling 3 times that receives character, get in 3 the actual value of at least 2 identical sampled result then as this character.
2) process of Fa Songing is as follows:
If detect observation point, that is to say when WP_STOP and WP_MATCH signal are effective simultaneously, the enabling signal TX_BEGIN of process of transmitting is effective, and the address that is stored in the data of the internal register among the TX_SFR_DATA and current observation point is downloaded to and sends among the shift register TX_SHIFTER_1.Simultaneously, 1 signal that is produced by a d type flip flop is write into the high order end of TX_SHIFTER_1 as position of rest.Then, the TX_SEND signal is effective, and the data among the TX_SHIFTER_1 are shifted to the right on the NEA_O signal wire by serial under the control that sends shift pulse TX_SHIFT.In the process of data shift right, d type flip flop constantly writes 0 signal to TX_SHIFTER_1, arrives the low order end of TX_SHIFTER_1 up to position of rest.At this moment, complete 0 data of position of rest left end are detected by complete 0 detecting device, so trigger the TX_END signal, the notice transmit control device stops to send data.
The dynamic tracking debug command that receives through above-mentioned serial communication submodule has 8.In order to store these debug commands that receive, defined the binary coding (seeing Table 1) that 14 debug command register DBGCMD stores these 8 debug commands.Wherein, those binary codings of not using among the DBGCMD temporarily keep, and can expand afterwards.
Be stored in dynamic tracking order among the DBGCMD and can control the OCT module and finish various dynamic tracking function (see figure 5)s, comprising: the setting of observation point, the selection of internal register and in the process of dynamic tracking, detect observation point etc. processor.
1) setting of observation point:
WP0～WP7:8 observation point address register, storage be the first address that is set to the instruction of observation point.In the time of system reset, the content of 8 observation point address register WPi (i=0～7) all is a high value.
The setting of observation point realizes (see figure 5) by special " observation point is provided with network ", according to the different command that receives, can carry out the difference setting of observation point:
I) if receive observation point order WP_SET is set, observation point is provided with 16 bit address (seeing Fig. 2 (b)) that network just will receive this moment in the lump and is written among one of them WPi as the address of an observation point, the order that writes is from WP0, arrives WP7 then and finishes.Debugging person can according to circumstances be provided with 0～8 observation point.If the set observation point of debugging person has surpassed 8, the 9th observation point will override the 1st so, and the 10th override the 2nd, and the rest may be inferred.
Remove order WP_REMOVE if ii) receive observation point, observation point is provided with network and just 16 bit address (seeing Fig. 2 (b)) that receive this moment is compared with the address that is set to observation point, and that observation point that will mate then removes.
If iii) receive observation point clear command WP_CLR, observation point is provided with network and just 8 all observation point is disposed together.
2) selection of internal register:
SFR_SEL: register selection signal register, size are 24, storage be the selection signal of 24 internal registers.During system reset, 24 are selected signal all is 0.
Set up after the observation point, debugging person also needs to specify in the internal register that each given viewpoint needs is tracked and write down, and this is the (see figure 5) that realizes by " internal register selection network ".If the OCT module receives the SFR_SET order, internal register selects network just will to be stored among the register SFR_SEL with " 24 internal registers are selected signal " (the seeing shown in Fig. 2 (d)) that this order obtains this moment, selects the internal register of correspondence then according to each state of SFR_SEL.
Each of SFR_SEL register all is an independently register selection signal, and high level is effective, and with 24 corresponding one by one (see figure 6)s of internal register commonly used.Therefore, one to have 24 internal registers available, and debugging person can select wherein 0～24 arbitrarily.For example, if the lowest order SFR_SEL.0 of SFR_SEL is 1, then corresponding with it totalizer ACC is just selected, therefore all wants tracked and record at each given viewpoint ACC, if but SFR_SEL.0 is 0, then ACC does not just need tracked and record.The selection mode of other internal registers is identical with it.
3) in the process of dynamic tracking, detect observation point:
If debugging person has set observation point, and set in each given viewpoint and need internal register tracked and record, just can start the dynamic tracking process with the D_DBG order, then, CPU can bring into operation from obtaining " start address " (seeing Fig. 2 (e)) with this order.In the process of the normal operation of CPU, the OCT module is carried out the detection of observation point automatically.The method that detects observation point is as shown in Figure 7:
PCC: 16 first address registers of the current instruction of carrying out.
WP_MATCH: observation point matched signal.
WP_STOP: observation point coupling stop signal.
NOP: non-operation instruction.
The clock signal of CCLK:CPU operate as normal.
CPU_STOP: the signal that stops the work clock of CPU.
As can be seen from Figure 7, address stored is 75H among the observation point register WP0, and this is the first address of certain bar instruction.If CPU is the current MOV A that just executing instruction, #data, and also the first address of this instruction is 75H, so, the data among the PCC are exactly 75H.Next, the step of detection observation point is:
I) at this MOV A, the 3rd clock period C1P3 of #data instruction, the OCT module compares value and the PCC of WP0, and both conform to, so the WP_MATCH signal is effective immediately.Then, because the WP_MATCH signal is effective, execute after this MOV instruction, CPU also will carry out an extra non-operation instruction NOP, to guarantee MOV A, the integrality of #data instruction.Therefore, first clock period C1P1 in the NOP instruction, the value of PCC becomes first address 77H (because the MOVA of NOP instruction immediately, the machine code of #data takies two byte addresses, and after executing this MOV instruction, the program pointer of processor can point to by the first address of the instruction of this temporary transient replacement of extra NOP instruction institute).
Ii) at the 3rd clock period C1P3 of NOP instruction, this moment, WP0 and PCC did not match, so the WP_MATCH signal is invalid immediately.Simultaneously, carry out because this NOP instruction is that CPU is extra, therefore at the 2nd clock period C1P2 of this NOP instruction, the OCT module can make the WP_STOP signal effective.Then, the next clock period after WP_STOP is effective (being the C1P3 moment of NOP instruction), it is effective to send enabling signal TX_BEGIN.So, just be written among the transmission shift register TX_SHIFTER_1 in the tracked data in observation point 75H place, simultaneously, the NEA_O end begins to send the start bit (0 level) of serial data.
Iii) follow, at the 4th clock period C1P4 of NOP instruction, the CPU_STOP signal is effective, and the work clock CCLK of CPU is stopped.So CPU suspends, wait for that the OCT module analyzes the debugging acid that the CPU internal information serial at observation point 75H place outputs to the outside.Because CCLK stops, so the 4th clock period C1P4 of NOP instruction can be maintained to till the CCLK recovery.
Claims (7)
1. dynamic tracking method on the sheet of a microprocessor, it is characterized in that: by an on-chip tracer OCT, some position in the program process is set to observation point, then the information of the internal register of these given viewpoint appointments is followed the tracks of, is write down and real-time output; Its concrete steps are:
A., an asynchronous serial transmitting-receiving submodule is set, to realize communicating by letter of OCT module and processor outside;
B. set a debug command register DBGCMD, store the dynamic tracking debug command that debugging person is sent to the OCT module;
C. set n observation point address register WPi (i=0～n-1), store the first address that debugged person is set to the program of observation point;
D. set internal register and select sign register SFR SEL, be stored in the selection signal of the internal register of the tracked and record of each given viewpoint;
E. set a present instruction first address register PCC, store the first address of the current instruction of carrying out of CPU automatically;
F. start the dynamic tracking process by " starting the dynamic tracking order ", in the process of dynamic tracking, the OCT module is according to circumstances carried out the dynamic tracking operation then, and sets coherent signal.
2. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that the method that an asynchronous serial transmitting-receiving submodule is set among the described step a is:
This serial transmitting-receiving submodule adopts semiduplex asynchronous serial communication pattern, carries out serial communication by 1 signal wire and processor outside, and transmission and reception are two independently processes; The fundamental purpose of receiving unit is to receive the various debug commands that debugging acid sends, and data and the program address relevant with each order, and the purpose that sends then is the content strings line output with the selected internal register that goes out of each given viewpoint; Simultaneously, reception and process of transmitting have all adopted the data frame format of 1 position of rest+valid data position+1 start bit, and wherein position of rest is 1 level, and start bit is 0 level.Some signals and the register relevant with serial communication are defined as follows:
A.NEA: the external pin that asynchronous serial transmitting-receiving submodule and processor outside communicate then is divided into NEA_I in the OCT inside modules, i.e. serial data input end, and NEA_O, i.e. serial data output terminal;
B.RX_CLK/TX_CLK: the sampling clock when being asynchronous serial transmitting-receiving submodule reception and transmission serial data respectively, frequency all is 1/100 of a processor clock frequency;
C.RX_SHIFT/TX_SHIFT: the serial-shift pulse when being asynchronous serial transmitting-receiving submodule reception and transmission data respectively, frequency all is 1/8 of RX_CLK/TX_CLK, therefore, the baud rate of communication is 1/800 of a processor operating rate;
D.RX_SHIFTER: receive shift register, reception be each debug command and relevant data and address;
E.TX_SHIFTER_1: send shift register, transmission be in the data of each given viewpoint internal register and the address of this observation point.
3. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that the method for setting a debug command register DBGCMD among the described step b is:
Definition DBGCMD is one 4 a register, and it is used to store the binary coding of the debug command that debugging acid sends, and the debug command that receives is decoded as control signal corresponding.
DBGCMD can store 8 orders relevant with dynamic tracking, sees Table 1, and wherein, other binary codings of not using among the DBGCMD temporarily keep, and can expand afterwards.
The dynamic tracking order of table 1 DBGCMD storage
Binary coding The order symbol Functional description
0000 DBG_RST Under debugging mode, whole microprocessor system is resetted
1010 WP_SET Certain bar instruction in the program is set to an observation point
1011 WP_REMOVE Remove the observation point of an appointment
1100 WP_CLR The observation point that disposable removing is all
0011 SFR_SET Be set in each given viewpoint and need internal register tracked and record
1101 D_DBG Start the dynamic tracking process
1110 D_DBG_PAUSE Suspend the dynamic tracking process
1111 D_DBG_Stop Stop the dynamic tracking process
4. dynamic tracking method on the sheet of microprocessor according to claim 1, it is characterized in that setting among the described step c n observation point address register WPi (method of i=0～n-1) is:
Definition WPi (i=0～n-1) be the register of individual 16 of n, storage be the first address that is set to the instruction of observation point; After the system reset, the value of this n observation point address register all is a high value;
The OCT module is provided with or removes observation point according to following three kinds of situations:
A) if receive WP_SET order, 16 bit address that the OCT module just will receive with this order are stored in the WPi register as the address of an observation point, and the order of storage is from WP0, arrives WPn-1 at last; If the observation point that debugging person is provided with surpasses n, then the address of n+1 observation point just overrides the 1st observation point, and n+2 observation point overrides the 2nd, and the like;
B) if receive the WP_REMOVE order, the OCT module will be compared 16 bit address that receive this moment with the address that before was set at observation point, will remove with the observation point of this matching addresses then;
C) if receive the WP_CLR order, the OCT module is just with the disposable full scale clearance of all observation point, and the data of the observation point register after being eliminated all are high value.
5. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that setting in the described steps d internal register and selects the method for sign register SFR_SEL to be:
Definition SFR_SEL is the register of a n position, the corresponding according to the order of sequence n of it each internal register commonly used, and it is defined as follows:
Internal register n selects signal …… Internal register 2 is selected signal Internal register 1 is selected signal
When receiving selection internal register order SFR_SET, the OCT module just will order the n bit register selection signal storage that receive in SFR_SEL with SFR_SET this moment; If this moment, a certain position of SFR_SEL was 1, then this pairing internal register will be tracked, and the content of this internal register all will be output in each given viewpoint simultaneously; Otherwise if this position is 0, so Dui Ying this internal register does not just need tracked and record.
6. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that the method for setting a present instruction first address register PCC among the described step e is:
Definition PCC is 1 16 a address register, storage be 16 first addresss of the current instruction of carrying out; Its value is by OCT module automatic setting; After the system reset, the value of PCC is 00h;
The concrete grammar of setting the PCC register is: in the process that program is carried out, in the 1st clock period of every instruction, the value of the program pointer that points to this instruction is delivered in the PCC register; PCC can preserve this address always, the 1st clock period up to next bar instruction, just is updated to new address.
7. dynamic tracking method on the sheet of microprocessor according to claim 1 is characterized in that among the described step f that in the process of dynamic tracking, the dynamic tracking operation that the OCT module is according to circumstances carried out has following three kinds:
If after a. the dynamic tracking process started, the OCT module did not receive other control commands, then the OCT module will compare WPi (i=0～n-1) carry out the detection of observation point with the content of PCC automatically in the process that program is carried out; If detect observation point, the OCT module is just analyzed the bit string line output of the selected internal register of this given viewpoint to outside debugging acid;
The concrete steps that detect observation point and export internal register information are:
A) WP_MATCH: the observation point matched signal, high level is effective;
WP_STOP: observation point coupling stop signal;
In the process that program is carried out, in the 3rd clock period of every instruction, (content of i=0～n-1) compares with present instruction first address register PCC respectively with n observation point address register WPi; As long as have the content of an observation point address register and the content of PCC to mate fully, just explanation has detected an observation point, so the WP_MATCH signal is effective immediately; After the instruction that executes this given viewpoint, CPU also needs to carry out a non-operation instruction NOP to guarantee the integrality of execution process instruction again; Then, in the 2nd clock period of this NOP instruction, the WP_STOP signal is effective, simultaneously, the OCT module all is stored in the value of all selected internal registers that go out in the corresponding temporary register, and not having the content of the selected pairing temporary register of internal register with those then all is 0; In the next clock period after effectively of WP_STOP signal and then, the OCT module enters the preparatory stage of serial transmission;
B) TX_SFR_DATA: the register of storing n internal register data and current observation point first address;
TX_SHIFTER_1: send shift register;
TX_BEGIN: send commencing signal;
CPU_STOP: the signal that stops the CPU work clock;
In the preparatory stage that serial sends, i.e. the 3rd clock period of NOP instruction, the TX_BEGIN signal is effective, and serial transmitting-receiving submodule all leaves in the content of n temporary register and the first address of current observation point among the register TX_SFR_DATA according to the order of sequence; Then, TX_SFR_DATA and 1 start bit and 1 position of rest are left in according to the order of sequence send among the shift register TX_SHIFTER_1 again; From the 4th clock period of NOP instruction, the OCT module enters the output stage that serial sends; Simultaneously, the CPU_STOP signal is effective, and CPU is out of service;
C) TX_END: the end signal of serial output;
At the output stage that serial sends, serial transmitting-receiving submodule is sent the content serial of TX_SHIFTER_1, and low level is preceding output the time, and left end constantly mends 0; When position of rest arrived the low order end of TX_SHIFTER_1, the all-zero signal of position of rest left end was detected by one " full null detector ", so the TX_END signal is effective immediately, the OCT module just stops the serial process of transmitting;
After b. if the dynamic tracking process starts, in the process of dynamic tracking, the OCT module receives the order D_DBG_PAUSE that suspends dynamic tracking, then in last clock period of present instruction, the CPU_STOP signal is effective, and CPU is out of service, and total system enters the halted state of dynamic tracking; At this moment, debugging person can come the ruuning situation of routine analyzer according to the processor internal information of the given viewpoint that is detected, thus search program mistake, reconfiguration program flow process etc.; If the current halted state that is in dynamic tracking of system, if debugging person sends the order D_DBG_PAUSE that suspends dynamic tracking once more, then system withdraws from halted state immediately, and reenters the dynamic tracking process; The CPU_STOP signal is invalid immediately simultaneously, and CPU begins to rerun from next bar instruction of previous time-out;
If after c. the dynamic tracking process started, in the process of dynamic tracking, the OCT module received the order D_DBG_STOP that stops dynamic tracking, then system withdraws from the dynamic tracking process immediately, and waits for that debugging person sends new dynamic tracking order.
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2006
- 2006-09-01 CN CNB2006100307547A patent/CN100401267C/en not_active Expired - Fee Related
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