CN1933159A - Fast flash memory body and producing method thereof - Google Patents
Fast flash memory body and producing method thereof Download PDFInfo
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- CN1933159A CN1933159A CN 200510103417 CN200510103417A CN1933159A CN 1933159 A CN1933159 A CN 1933159A CN 200510103417 CN200510103417 CN 200510103417 CN 200510103417 A CN200510103417 A CN 200510103417A CN 1933159 A CN1933159 A CN 1933159A
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Abstract
This invention relates to a quick flash memory body including a first source/drain region and a second source/drain region in the base, a first floating grating at the base between the two regions and adjacent to the first region, a second floating grating on the base between the two regions and adjacent to the second region, a light doped area in the base between the two floating gratings and a control grating covering the two gratings, in which, the first floating grating is separated from the second. This memory body can increase the memory density and reduce cost.
Description
Technical field
The invention relates to a kind of semiconductor element and its manufacture method, and particularly relevant for a kind of fast flash memory bank and its manufacture method.
Background technology
Memory body as its name suggests, is a kind ofly to be used for storing data or the semiconductor element of information.When the microprocessor of computer becomes with better function, the formula of software and calculating become more complicated, and the capacity requirement of memory body also increases thereupon.In order to satisfy the trend of this increase in demand, technology and the processing procedure of making the cheap memory body of high power capacity become the trend motive force of making high integration element.
In various memory body products, non-volatility memory has the storage of repeating, reads or erase data, and can not lose the ability of data when power interruptions, therefore becomes the semiconductor element of widely using in PC or electronic equipment.Wherein, fast flash memory bank is to have a kind of non-volatility memories of advantage such as the ability of fast reading and writing and high memory capacity.
Fast flash memory bank is applied to comprising the multiple industry of communication industry, consumer electronic industry, Data Processing industry and transportation industry.Under the height requirement of more and more little electronic equipment, how to dwindle the size of fast flash memory bank, and increase the storage density of memory body, and reduce the main research topic that manufacturing cost becomes recent manufacturing technology.
Summary of the invention
Therefore, the present invention has at least a purpose to provide a kind of fast-flash memory body structure, and it can store at least two carriers (Carrier) at a unit fast flash memory bank.
The present invention has at least another purpose to provide a kind of manufacture method of fast flash memory bank, uses this manufacture method, and floating grid (Floating Gate) can have consistent shape, and can reduce cost.
In order to reach above-mentioned advantage or other advantages and to cooperate purpose of the present invention, as in this specific implementation and broadly described content, the present invention provides a kind of fast flash memory bank to a substrate.This fast flash memory bank comprises first source/drain, second source/drain, first floating grid, second floating grid, light doped region and control grid.First source/drain and second source/drain are arranged in substrate.In addition, first floating grid is positioned in the substrate in first source/drain and the second source/drain interval, and adjacent with first source/drain.Second floating grid is positioned in the substrate in first source/drain and the second source/drain interval, and adjacent with second source/drain.Light doped region is arranged in the substrate between first floating grid and second floating grid.In addition, the control grid is covered on first floating grid and second floating grid.
In the present invention, source/drain and light doped region have identical conduction type.The dopant ion concentration of light doped region is less than the dopant ion concentration of first source/drain and second source/drain.In addition, first floating grid and second floating grid are isolated with dielectric layer.Fast flash memory bank of the present invention more comprises several pouch-type implantation doped regions.Pouch-type is implanted the substrate that doped region is arranged in first source/drain and the second source/drain interval, and adjacent with second source/drain with first source/drain respectively.In addition, first floating grid and second floating grid are isolated with tunneling dielectric layer and substrate.First floating grid and second floating grid are with one dielectric layer and control gate isolation, and the dielectric constant of this dielectric layer is greater than 4.
In the present invention, because each unit memory cell all disposes first floating grid and second floating grid, each first floating grid and second floating grid can store at least one carrier.Therefore, for a unit memory cell, memory density is higher.
The present invention more proposes a kind of manufacture method of fast flash memory bank.The step that the method comprises has to be provided with in the below and forms several openings in the conductor layer of substrate.Then, form several source/drain in the substrate under first opening.In addition, form several dielectric plugs to fill up first opening.Dielectric plugs is higher than conductor layer and continues it, forms the multilayer clearance wall on the conductor layer that is patterned and the sidewall of dielectric plugs, the conductor layer of this multilayer clearance wall expose portion.In the conductor layer that is patterned, form second opening, patterning conductor layer is separated into first floating grid and second floating grid.Form and aim at voluntarily in the substrate of light doped region under second opening, form first dielectric layer then to fill up second opening.Expose the top surface of first floating grid and second floating grid.Then, form the control grid in substrate.
In the present invention, the dopant ion concentration of light doped region is less than the dopant ion concentration of source/drain.In addition, the step of formation multilayer clearance wall is included in and forms the conformal dielectric layer of one deck in the substrate.Then, on conformal dielectric layer, form one deck second dielectric layer.Then, carry out etch process to remove second dielectric layer partly and conformal dielectric layer partly up to exposing partially patterned conductor layer.In said circumstances, more can carry out the planarization processing procedure, this planarization processing procedure is to be stop layer with the part in the conformal dielectric layer of first floating grid and the second floating grid top surface.Afterwards, remove the top surface of other conformal dielectric layer up to exposure first floating grid and second floating grid.In addition, the above-mentioned step that removes other conformal dielectric layer can utilize cmp (CMP) processing procedure, wet etching processing procedure or dry ecthing procedure to finish.In addition, the grinding selectivity ratio of the conformal dielectric layer and second dielectric layer (Polishing Selective Ratio) approximately is 500.Conformal dielectric layer is to make with silicon nitride, and second dielectric layer is to make with silicon oxynitride.Specifically, the material of second dielectric layer is identical with the material of the dielectric plugs and first dielectric layer.In addition, form the step of aiming at light doped region voluntarily and can utilize every cubic centimeter 10 of ion concentration
18The implantation energy of the implantation of individual ion and about 10keV is reached.
In the present invention, because conductor layer is separated into first floating grid and second floating grid by first dielectric layer, each first floating grid and second floating grid can store at least one carrier.Therefore, for a unit memory cell, memory density has increased.In addition, light doped region is to be used as the cover curtain with dielectric plugs and multilayer clearance wall to be formed in the substrate voluntarily with aiming at, and does not use micro-photographing process separately.Therefore, cost is minimized.
Above general narration and ensuing specification specified are exemplary, and are to be used to provide the content further instruction of being advocated of the present invention.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
In order to provide the present invention is further understood, accompanying drawing is incorporated into and is constituted the part of this specification.These a little accompanying drawings illustrate embodiments of the invention, cooperate the content of explanation, to explain orally principle of the present invention.
Figure 1A to Fig. 1 H illustrates the manufacture method profile of the fast flash memory bank of a preferred embodiment of the present invention.
Fig. 2 illustrates the profile of the fast flash memory bank of another preferred embodiment of the present invention.
100,200: substrate 102,202: tunneling dielectric layer
104: conductor layer 104a, 204a: first floating grid
104b, 204b: second floating grid 108: rigid cover curtain layer
Opening 112,212 in 110: the first: source/drain
114a, 116a, 116c, 216c: dielectric plugs
114b, 116b, 128,128a, 130,230: dielectric layer
118:L type clearance wall 120: clearance wall
122: 124: the second openings of multilayer clearance wall
126,226: light doped region 132,232: the control grid
240: pouch-type is implanted doped region
Embodiment
Figure 1A to Fig. 1 H illustrates the manufacture method profile of the fast flash memory bank of a preferred embodiment of the present invention.
See also shown in the 1A, provide substrate 100, one deck conductor layer (not shown) and one deck rigid cover curtain layer (not shown) with tunneling dielectric layer 102.Conductor layer is positioned on the tunneling dielectric layer 102, and rigid cover curtain layer is positioned on the conductor layer.Tunneling dielectric layer 102 for example is made with silica, aluminium oxide, hafnium oxide, silicon nitride or silicon oxynitride, but does not limit above-mentioned material.The formation method of tunneling dielectric layer 102 for example is long-pending (LPCVD) processing procedure in low pressure chemical gas phase Shen, but is not limited thereto method.In addition, the thickness of tunneling dielectric layer 102 is about 5 to 15 nanometers.In addition, conductor layer for example is made with polysilicon, doped polycrystalline silicon, metal silicide or metal, but does not limit above-mentioned material.The thickness of conductor layer approximately is 40 to 100 nanometers.Moreover rigid cover curtain layer for example is to make with silica or silicon nitride, and the thickness of rigid cover curtain approximately is 50 to 200 nanometers, but the material and the thickness of rigid cover curtain are not limited.
Then, rigid cover curtain layer of patterning and conductor layer are with formation conductor layer 104 and rigid cover curtain layer 108, and first opening 110 among conductor layer 104 and the rigid cover curtain layer 108.In the present embodiment, 110 of first openings pass rigid cover curtain layer 108 and conductor layer 104, and the tunneling dielectric layer 102 of expose portion.Yet illustrated first opening, 110 structures of present embodiment not delimit the scope of the invention.That is to say that along with the difference of the demand of manufacturing, first opening 110 also can pass the substrate 100 of tunneling dielectric layer 102 with expose portion.
See also shown in the 1B, form several source/drain 112 in the substrate 100 under first opening 110 respectively.The formation method of source/drain 112 comprises that carrying out ion implants with every cubic centimeter 10 of implant concentration
19To 10
20Individual ion is to substrate 100.In addition, the ion that is implanted in the substrate 100 for example is arsenic ion, nitrogen ion or phosphonium ion.
In addition, form several dielectric plugs 114a and also fill up first opening 110 respectively.The formation method of dielectric plugs 114a comprises with one deck dielectric material and covers substrate 100, on rigid cover curtain layer 108, forming dielectric layer 114b, and respectively at forming dielectric plugs 114a in first opening 110.Dielectric material for example is silicon nitride, silica or has dielectric material with rigid cover curtain layer 108 DIFFERENT WET etching behaviors, but do not limited.In addition, the thickness of the dielectric layer that is constituted with dielectric layer 114b and dielectric plugs 114a is about 80 to 300 nanometers.
See also shown in the 1C, carry out the wet dip processing procedure removing part dielectric layer 114b and dielectric plugs 114a, and convert dielectric layer 114b and dielectric plugs 114a to dielectric layer 116b and dielectric plugs 116a.Therefore, dielectric layer 116b and dielectric plugs 116a can expose the part of the top surface of rigid cover curtain layer 108.When the dielectric layer that is made of dielectric layer 114b and dielectric plugs 114a is when being made by silica, the wet dip processing procedure can utilize the hydrofluoric acid of dilution or the hydrofluoric acid of buffering to reach, perhaps, when the dielectric layer that is made of dielectric layer 114b and dielectric plugs 114a is when being made by silicon nitride, the wet dip processing procedure can utilize hot phosphoric acid to reach.
Afterwards, see also shown in the 1D, peel off processing procedure with remove rigid cover curtain layer 108 and rigid cover curtain layer 108 on dielectric layer 116b.When rigid cover curtain layer 108 is when being made by silica, the wet dip processing procedure can utilize the hydrofluoric acid of dilution and the hydrofluoric acid of buffering to reach.Perhaps, when rigid cover curtain layer 108 is when being made by silicon nitride, the wet dip processing procedure can utilize hot phosphoric acid to reach.
In addition, forming multilayer clearance wall 122 on the conductor layer 104 and on the sidewall of dielectric plugs 116a.Multilayer clearance wall 122 expose portion conductor layers 104 wherein.The formation method of multilayer clearance wall 122 is included in and forms the conformal dielectric layer (not shown) of one deck in the substrate 100, on this conformal dielectric layer, form the one dielectric layer (not shown) then, carry out dielectric layer and partly the conformal dielectric layer of etch process afterwards, up to the conductor layer 104 of expose portion to remove part.Then, this conformal dielectric layer and this dielectric layer are converted into L type clearance wall 118 and clearance wall 120 respectively, and L type clearance wall 118 and clearance wall 120 common formation multilayer clearance walls 122.In addition, conformal dielectric layer (being L type clearance wall 118) approximately is 500 to the grinding selectivity ratio of dielectric layer (being clearance wall 120).In addition, conformal dielectric layer (being L type clearance wall 118) for example is made by utilizing long-pending (CVD) processing procedure in chemical gaseous phase Shen and electricity slurry to strengthen the long-pending formed silicon nitride of processing procedure in chemical gaseous phase Shen, but the material of conformal dielectric layer and formation method do not limit.Dielectric layer (being clearance wall 120) for example is that the material identical with forming dielectric plugs 116a is made.
See also shown in the 1E, utilize multilayer clearance wall 122 and dielectric plugs 116a to be the cover curtain, carry out etch process and conductor layer 104 is separated into the first floating grid 104a and the second floating grid 104b in conductor layer 104, to form second opening 124.In the present embodiment, second opening 124 only passes conductor layer 104 (shown in Fig. 1 D) and exposes the part of tunneling dielectric layer 102.Yet the structure of being presented in second opening 124 of present embodiment not delimit the scope of the invention.That is to say that for different manufacturing demands, second opening 124 also can pass the substrate 100 of tunneling dielectric layer 102 with expose portion.
In addition, light doped region 126 is aimed in formation voluntarily in the substrate 100 under second opening 124.Aim at the formation step of light doped region 126 voluntarily and can utilize every cubic centimeter 10 of ion concentration
18Individual, implant the implanting ions of the about 10keV of energy and reach.In addition, admixture for example is arsenic ion, nitrogen ion and phosphonium ion, but does not limit.
See also shown in the 1F, form one dielectric layer 128 to fill up second opening 124.Dielectric layer 128 for example is to utilize the dielectric material identical with formation dielectric plugs 116a and clearance wall 120 made, and dielectric layer 128 for example is to form with the LPCVD processing procedure.
See also shown in 1G and Fig. 1 H, carry out the planarization processing procedure up to exposing the first floating grid 104a and the second floating grid 104b.The method of carrying out this planarization processing procedure comprises that the partial L type clearance wall 118 (shown in Fig. 1 F) of the top surface that utilizes the first floating grid 104a and the second floating grid 104b is a stop layer, carry out the planarization processing procedure to remove the dielectric layer 128 and the multilayer clearance wall 122 of part, remove other L type clearance wall 118 then, up to the top surface that exposes the first floating grid 104a and the second floating grid 104b fully.In addition, the step that removes other L type clearance wall 118 for example is to carry out cmp (CMP) processing procedure, wet etch process or dry-etching processing procedure to reach, but does not limit.In this planarization processing procedure, in the incipient stage of CMP processing procedure, owing to dielectric layer 128, clearance wall 120 and dielectric plugs 116a are made by identical material, and the amount of grinding of L type clearance wall 118 is very little, and the grinding rate can be kept stable.Yet when the clearance wall 118 of major part has been removed, and the amount of grinding of L type clearance wall 118 reduces tempestuously, because the grinding selectivity ratio of 118 pairs of dielectric layers of L type clearance wall (being clearance wall 120 and dielectric plugs 116a), the CMP processing procedure can stop.After the planarization processing procedure, residual dielectric plugs is denoted as 116c, and residual dielectric layer is denoted as 128a in second opening 124.
See also shown in the 1H, in substrate 100, form dielectric layer 130.Dielectric layer 130 for example is a dielectric constant greater than 4 dielectric layer.Preferably, dielectric layer 130 for example is silicon oxide/silicon nitride/silicon oxide layer or silica/high dielectric material (High k Material)/silicon oxide layer, but does not limit.This high dielectric material can be the dielectric material that has greater than 4 dielectric constant.And this high dielectric material for example is aluminium oxide, hafnium oxide, silicon nitride or silicon oxynitride, but does not limit.Afterwards, in substrate 100, form control grid 132.The material of control grid 132 for example is with polysilicon, doped polycrystalline silicon, and metal silicide or metal are made, and controls the thickness that grid 132 has about 40 to 200 nanometers, and the material and the thickness of control grid 132 do not limit.
Please continue the H with reference to Fig. 1, the present invention more provides a fast-flash memory body structure.Fast-flash memory body structure of the present invention comprises several source/drain 112 that are arranged in substrate 100, the first floating grid 104a in substrate 100 between the source/drain 112 and the second floating grid 104b, wherein the first floating grid 104a and the second floating grid 104b are isolated from each other with dielectric layer 128a, and adjacent with source/drain 112 respectively.This fast flash memory bank more comprises the light doped region 126 in the substrate 100 between the first floating grid 104a and the second floating grid 104b.Moreover control grid 132 is positioned in the substrate 100, and isolates with the first floating grid 104a and the second floating grid 104b greater than 4 dielectric layer 130 by dielectric constant.In addition, source/drain 112 and light doped region 126 have identical conduction type.In addition, the first floating grid 104a and the second floating grid 104b isolate with tunneling dielectric layer 102 and substrate 100.
Fig. 2 illustrates the profile of the fast flash memory bank of another preferred embodiment of the present invention.The fast flash memory bank of another preferred embodiment of the present invention comprises that more several pouch-type in the substrate 200 are implanted doped region 240 between source/drain 212, and pouch-type is implanted doped region 240 respectively in abutting connection with source/drain 212.Pouch-type implantation doped region 240 for example is that the ion of the implantation substrate 200 of utilization and source/drain 212 different conduction-types forms.Implant substrate 200 and be about every cubic centimeter 10 with the ion concentration that forms pouch-type implantation doped region 240
16To 10
18Individual ion, and these ions for example are boron ion or boron fluoride.
In the present invention, because conductor layer 104 is separated into the first floating grid 104a and the second floating grid 104b by dielectric layer 128a, each the first floating grid 104a and the second floating grid 104b can store at least one carrier.Therefore, for a unit memory cell, memory density has increased.In addition, be used as cover curtain with dielectric plugs 116a and multilayer clearance wall 122, light doped region 126 is to aim at voluntarily and be formed in the substrate 100, and does not use micro-photographing process separately.Therefore, cost is minimized.In addition, be used as the grinding stop layer, can obtain good control for removing the CMP processing procedure that dielectric layer 128, clearance wall 120 and dielectric plugs 116a carried out with the L type clearance wall 118 that is positioned on the first floating grid 104a and the second floating grid top surface.Therefore, the first floating grid 104a and the shape of the second floating grid 104b behind the planarization processing procedure can be more consistent.
Obviously, for knowing this skill person, the present invention can do various adjustment and variation and not depart from the scope of the present invention and spirit.In above description,, then the present invention includes various adjustment and variation to itself if these are adjusted and change the scope that belongs to claim and equivalence narration.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (17)
1, a kind of fast flash memory bank is applicable to a substrate, and this fast flash memory bank comprises:
One first source/drain and one second source/drain, the position is in this substrate;
One first floating grid, the position is in this substrate in this first source/drain and this second source/drain interval, and this first floating grid abuts against this first source/drain;
One second floating grid, the position is in this substrate in this first source/drain and this second source/drain interval, and this second floating grid abuts against this second source/drain;
One light doped region is in this substrate between this first floating grid and this second floating grid of position; And
One control grid covers on this first floating grid and this second floating grid.
2, fast flash memory bank according to claim 1, wherein this first source/drain and this second source/drain have the conduction type identical with this light doped region (Conductivity Type).
3, fast flash memory bank according to claim 1, the wherein little dopant ion concentration of the dopant ion concentration of this light doped region in this first source/drain and this second source/drain.
4, fast flash memory bank according to claim 1, wherein this first floating grid and this second floating grid are isolated with a dielectric layer.
5, fast flash memory bank according to claim 1, more comprise most pouch-type implantation doped regions, the position and abuts against this first source/drain and this second source/drain respectively in this substrate in this first source/drain and this second source/drain interval.
6, fast flash memory bank according to claim 1, wherein this first floating grid and this second floating grid are isolated with a tunneling dielectric layer and this substrate.
7, fast flash memory bank according to claim 1, wherein this first floating grid and this second floating grid are to have a dielectric layer and this control gate isolation greater than 4 dielectric constant.
8, a kind of manufacture method of fast flash memory bank comprises:
Below one, be provided with and form most first openings in the conductor layer of substrate;
Form most source/drain in this substrate under this first opening respectively;
Form most dielectric plugs, to fill up this first opening respectively, those dielectric plugs height are at this conductor layer;
At the conductor layer of this patterning and respectively form a multilayer clearance wall, wherein this conductor layer of this multilayer clearance wall expose portion on the sidewall of this dielectric plugs;
In the conductor layer of this patterning, form one second opening, make this conductor layer separately form one first floating grid and one second floating grid;
Form one in this substrate under this second opening and aim at light doped region voluntarily;
Form one first dielectric layer to fill up this second opening;
Expose this first floating grid and this second floating grid; And
Form a control grid in this substrate, this control grid covers this substrate.
9, fast flash memory bank manufacture method according to claim 8, the wherein little dopant ion concentration of the dopant ion concentration of this light doped region in those source/drain.
10, the manufacture method of fast flash memory bank according to claim 8, the step that wherein forms this multilayer clearance wall comprises:
Form a conformal dielectric layer in this substrate, this conformal dielectric layer covers this substrate;
On this conformal dielectric layer, form one second dielectric layer; And
Carry out an etch process, to remove this second dielectric layer of part and this conformal dielectric layer of part, up to the part of the conductor layer that exposes this patterning.
11, the manufacture method of fast flash memory bank according to claim 10 wherein more comprises:
This conformal dielectric layer of part with the top surface of this first floating grid and this second floating grid is a stop layer, carries out a planarization processing procedure; And
Remove other this conformal dielectric layer, up to the top surface that exposes this first floating grid and this second floating grid.
12, the manufacture method of fast flash memory bank according to claim 11, the step that wherein removes other this conformal dielectric layer are to reach to carry out a cmp (CMP) processing procedure, a wet etch process or a dry-etching processing procedure.
13, the manufacture method of fast flash memory bank according to claim 10, wherein this conformal dielectric layer approximately is 500 to the grinding selectivity ratio (Polishing Selective Ratio) of this second dielectric layer.
14, the manufacture method of fast flash memory bank according to claim 10, wherein this conformal dielectric layer is to be made by silicon nitride.
15, the manufacture method of fast flash memory bank according to claim 10, wherein this second dielectric layer is to be made by silicon oxynitride.
16, the manufacture method of fast flash memory bank according to claim 10, wherein this second dielectric layer be by with constitute this dielectric plugs and this first dielectric layer identical materials is made.
17, the manufacture method of fast flash memory bank according to claim 8 wherein forms this step of aiming at light doped region voluntarily and can utilize every cubic centimeter 10 approximately
18The implanting ions of the implantation energy of the concentration of individual ion and about 10keV is reached.
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| CN200510103417A CN100592521C (en) | 2005-09-15 | 2005-09-15 | Fast flash memory element and producing method thereof |
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| CN200510103417A CN100592521C (en) | 2005-09-15 | 2005-09-15 | Fast flash memory element and producing method thereof |
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| CN1933159A true CN1933159A (en) | 2007-03-21 |
| CN100592521C CN100592521C (en) | 2010-02-24 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106562767A (en) * | 2016-11-04 | 2017-04-19 | 深圳大学 | Sweat detection system and manufacturing method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106562767A (en) * | 2016-11-04 | 2017-04-19 | 深圳大学 | Sweat detection system and manufacturing method therefor |
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