CN1941181B - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
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- CN1941181B CN1941181B CN2006101412288A CN200610141228A CN1941181B CN 1941181 B CN1941181 B CN 1941181B CN 2006101412288 A CN2006101412288 A CN 2006101412288A CN 200610141228 A CN200610141228 A CN 200610141228A CN 1941181 B CN1941181 B CN 1941181B
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- precharge
- signal
- local input
- unit
- output mode
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
Abstract
A semiconductor memory device includes: a bank including a plurality of cell blocks; a first group of local input/output lines to transfer data stored on a first group of the cell blocks according to a first data output mode; a second group of local input/output lines to transfer data stored on a second group of the cell blocks according to the first data output mode and a second data output mode; a first precharge unit precharging the first group of the local input/output lines; a second precharge unit precharging the second group of the local input/output lines; a precharge signal generator to precharge the first and second groups of the cell blocks for the first data output mode and the second group of the cell blocks for the second data output mode.
Description
Technical field
The present invention relates to a kind of semiconductor storage unit, relate in particular to a kind of pre-charge circuit that is used for the local input of semiconductor storage unit.
Background technology
Typically, have and stack storage block structured semiconductor storage unit and comprise a plurality of storage blocks (bank), each all disposes the memory cell array of one group of each self-contained a plurality of storage unit.Storage block is arranged in word-line direction, and memory cell array also is arranged in the direction of word line, and is connected to local input.Local input is used as data line by being connected to overall input/output line.The quantity of local input preparation and the storage block of cutting apart as many and connect pre-charge circuit, with each local input of precharge.
Fig. 1 illustrates the block scheme of a part that is used to describe a storage block, and described storage block is divided into several zones according to the output mode of the data of semiconductor storage unit.For example, for double data rate (DDR) (DDR) memory device, a storage block is divided into 4 zones (often being called as " 1/4th storage blocks "), because the DDR memory device is carried out the pre-patch of 4 bits (pre-patch) operation.Under the situation of 16 Bit data output modes, export 16 Bit datas from one 1/4th storage block.
On concrete, Fig. 1 illustrates local input precharge unit in one 1/4th storage block, traditional and is used for the block scheme of the precharge control signal generator of described local input precharge unit, and described 1/4th storage blocks are divided into a plurality of cell blocks.
Precharge control signal generator 103 control local input precharge unit LIOPCG1-LIOPCG8.Local input precharge unit LIOPCG1-LIOPCG8 is disposed on the side of the upper and lower local input 101 that is connected with cell block and 102, and each cell block comprises that the unit cell of predetermined quantity is to satisfy the data output function pattern of semiconductor storage unit.Described cell block also is divided into cell block Up Half (first) and one group of lower unit piece Down Half (second) on one group.
Upper and lower cell block Up Half and Down Half are connected respectively to the upper and lower local input 101 and 102 as data line.In one 1/4th storage block, there are write driver WTDRV1-WTDRV8 and local input precharge unit LIOPCG1-LIOPCG8.Write driver WTDRV1-WTDRV8 transmits data from overall input/output line to upper and lower local input 101 and 102.The upper and lower local input 101 of local input precharge unit LIOPCG1-LIOPCG8 precharge and 102.
Upper and lower cell block Up Half and Down Half symmetric offset spread.Last cell block Up Half is connected with last local input 101, and lower unit piece Down Half is connected with following local input 102.Write driver WTDRV1-WTDRV8 is connected with 102 with corresponding upper and lower local input 101 respectively with local input precharge unit LIOPCG1-LIOPCG8.
Described cell block is grouped into cell block Up Half and one group of lower unit piece Down Half on one group, so that use described storage block effectively owing to the data processing condition of semiconductor storage unit, therefore reduces current drain.Local input precharge unit LIOPCG1-LIOPCG8 in response to local input reset signal LIORST, carries out precharge operation.
For example, under the situation of 4 bits or 8 Bit data output function patterns, come output data by the last local input 101 or the following local input 102 that are connected with 8 cell blocks.Under the situation of 16 Bit data output function patterns, come output data by the local input 101 and 102 that is connected with 16 cell blocks.The reason of this behavior is that only 8 cell blocks are used for 4 bits and 8 Bit data output modes, and 16 cell blocks are used for 16 Bit data output modes.
But local input precharge unit LIOPCG1-LIOPCG8 is not used in the control signal of described 4 bits or 8 Bit data output function patterns usually.Therefore, local input 101 and following local input 102 in the local input precharge unit LIOPCG1-LIOPCG8 precharge simultaneously.That is whole upper and lower local input 101 and 102 of being connected with described 16 cell blocks of precharge.As a result, when carrying out 4 bits or 8 Bit data output function patterns, the upper and lower local input 101 and 102 that is connected with 16 cell blocks causes current drain thus all by unnecessarily precharge.
More specifically, local input reset signal LIORST is used to control local input precharge unit LIOPCG1-LIOPCG8.But, when local input/output line reset signal LIORST is provided to each local input precharge unit LIOPCG1-LIOPCG8, local input reset signal LIORST is usually by described 4 bits, 8 bits and the control of 16 Bit data output function patterns, but only by three phase inverter INV1, INV2 of precharge control signal generator 103 and INV3 control.Therefore, necessary exploitation is a kind of can be according to the device of operator scheme difference precharge unit piece, so that reduce current drain.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of semiconductor storage unit, it can reduce unnecessary current drain by the local input that precharge optionally and corresponding piece storage block are coupled.
According to one aspect of the present invention, a kind of semiconductor storage unit is provided, comprising: storage block comprises a plurality of cell blocks; First group of local input is used for being transmitted in the data of storing on first group of cell block according to first data output mode and second data output mode; Second group of local input is used for being transmitted in the data of storing on second group of cell block according to first data output mode and second data output mode; First precharge unit is used for first group of local input of precharge; Second precharge unit is used for second group of local input of precharge; The precharging signal generator, be used for first and second groups of local input that precharge is used for second data output mode, and be used for precharge and be used for one of first and second groups of local input of first data output mode, wherein said first data output mode is one of 4 Bit data operator schemes and 8 Bit data operator schemes, and described second data output mode is 16 Bit data operator schemes.
According to another aspect of the present invention, a kind of semiconductor storage unit is provided, comprising: go up memory block, be used for exporting stored data according to first data output mode and second data output mode; Following memory block is used for exporting stored data according to first data output mode and second data output mode; First precharge unit is used for the local input of memory block in the precharge; Second precharge unit is used for the local input of memory block under the precharge; And precharge controller, be used for according to first data output mode or second data output mode, control first and second precharge unit, wherein said first data output mode is one of 4 Bit data operator schemes and 8 Bit data operator schemes, and described second data output mode is 16 Bit data operator schemes.
Described precharging signal generation unit comprises: first impact damper is used to cushion described reset signal; Second impact damper is used to cushion described first precharge and selects signal; The 3rd impact damper is used to cushion second precharge and selects signal; The 3rd Sheffer stroke gate is used to receive the output signal of first and second impact dampers, and produces first precharging signal; And the 4th Sheffer stroke gate, be used to receive the output signal of the first and the 3rd impact damper, and produce second precharging signal.
Description of drawings
The explanation of following each example embodiment that relatively provides in conjunction with the accompanying drawings, above-mentioned and other purposes of the present invention and feature will become better understood, wherein:
Fig. 1 illustrates traditional local input precharge unit and is used for the block scheme of the precharge control signal generator of described traditional local input precharge unit; And
Fig. 2 illustrates the local input precharge unit and the block scheme that is used for the precharge control signal generator of described local input precharge unit according to one embodiment of the present of invention.
Embodiment
To describe semiconductor storage unit in detail referring to accompanying drawing according to various embodiment of the present invention.
Fig. 2 illustrates the local input precharge unit and the block scheme that is used for the precharge control signal generator of described local input precharge unit according to one embodiment of the present of invention.
On a side of the upper and lower local input 205 that is coupled to cell block and 207, prepared local input precharge unit LIOPCG1-LIOPCG8, each described cell block comprises the unit cell of predetermined quantity, with the data output function pattern of the plan of satisfying semiconductor storage unit.And described cell block is divided into cell block Up Half and one group of lower unit piece Down Half on one group.
Upper and lower cell block Up Half and Down Half symmetric offset spread.Last cell block Up Half and 205 couplings of last local input, and lower unit piece Down Half and following local input 207 couplings.Write driver WTDRV1-WTDRV8 and local input precharge unit LIOPCG11-LIOPCG18 are coupled with corresponding upper and lower local input 205 and 206 respectively.Local input precharge unit LIOPCG11-LIOPCG18 is grouped into: go up the precharge unit group, it comprises those local input precharge unit LIOPCG11, LIOPCG13, LIOPCG15 and LIOPCG17 with last local input 205 couplings; And following precharge unit group, it comprises those local input precharge unit LIOPCG12, LIOPCG14, LIOPCG16 and LIOPCG18 with following local input 206 couplings.Described precharge unit group and the described precharge unit group down of going up of precharge control signal generator 209 precharge.
Be used for the precharge control signal generator 209 of local input precharge unit LIOPCG11, comprise precharge selection signal generation unit 201 and precharging signal generation unit 203 to LIOPCG18.Precharge is selected signal generation unit 201 to produce first and second precharge and is selected signal C
0And C
1, precharge unit group and following precharge unit group in the selection.Signal C is selected in precharging signal generation unit 203 responses first and second precharge
0And C
1, with local input reset signal LIORST, produce precharging signal, and the precharging signal selectivity be transferred to precharge unit group and following precharge unit group by corresponding line 211 and 213.
Precharge is selected signal generation unit 201 to comprise NOR door NOR1, phase inverter INV4, a NAND door NAND1, is reached the 2nd NAND door NAND2.NOR door NOR1 receives the signal x4 of instruction 4 Bit data output function patterns and instructs the signal x8 of 8 Bit data output function patterns.Phase inverter INV4 is anti-phase with the output signal of NOR door NOR1.The one NAND door NAND1 receives output signal and internal address signal AX＜13 of phase inverter INV4 〉, and export first precharge and select signal C
0The 2nd NAND door NAND2 receives first precharge and selects signal C
0With the output signal of phase inverter INV4, and export second precharge and select signal C
1
Precharging signal generation unit 203 can comprise first group of phase inverter INV5 and INV6, second group of phase inverter INV7 and INV8, the 3rd group of phase inverter INV9 and INV10, a NAND door NAND3, and the 2nd NAND door NAND4.To the reset local input reset signal LIORST of local input 205 and 207 of first group of phase inverter INV5 and INV6 is anti-phase.Second group of phase inverter INV7 and INV8 select signal C with first precharge
0Anti-phase.The 3rd group of phase inverter INV9 and INVl0 select signal C with second precharge
1Anti-phase.The one NAND door NAND3 receives first group and the second group of phase inverter INV5 output signal to INV8, and exports first precharging signal to last precharge group LIOPCG11, LIOPCG13, LIOPCG15 and LIOPCG17.The 2nd NAND door NAND4 receives the output signal of first group and the 3rd group phase inverter INV5, INV6, INV9 and INVl0, and exports second precharging signal and arrive precharge group LIOPCG12, LIOPCG14, LIOPCG16 and LIOPCG18. down
The following table simple declaration is the operation of semiconductor storage unit according to an embodiment of the invention.
Table 1
Under 16 Bit data output function patterns, last local input 205 and following local input 207 are by precharge.Under 4 bits or 8 Bit data output function patterns, make up first and second precharge and select signal C
0And C
1, with local input on the selective precharge 205 and following local input 207.
According to each example embodiment of the present invention, produce precharging signal, be coupled to each local input of each corresponding unit piece with selective precharge.Therefore, the selective precharge of local input can reduce unnecessary current drain.
Present patent application is included on September 28th, 2005 and on April 25th, 2006 respectively to the related subject content of the korean patent application of Korean Patent office application KR2005-0090841 number and KR2006-0037512 number, all includes in this by reference that it is all content.
Though the present invention describes for some preferred embodiment, those skilled in the art be will be obvious that, do not breaking away under the situation of the spirit and scope of the present invention that define as claim, can carry out various changes and modifications.
For example, when input signal and output signal were activated into logic high state, logic pattern described in the above embodiments and device layout were that demonstration realizes.Therefore, when the logic state of signal changed, illustrated realization also changed.Therefore, many other realizations also are possible; But these realizations will can not describe in detail, to prevent any potential abuse technology reorganization of those skilled in the art or to revise.
In addition, precharging signal generation unit 203 and precharge select signal generation unit 201 to realize with many logical circuits.But, should be noted that this demonstration realizes just illustrative.
Claims (10)
1. semiconductor storage unit comprises:
Storage block comprises a plurality of cell blocks;
First group of local input is used for being transmitted in the data of storing on first group of cell block according to first data output mode and second data output mode;
Second group of local input is used for being transmitted in the data of storing on second group of cell block according to first data output mode and second data output mode;
First precharge unit is used for first group of local input of precharge;
Second precharge unit is used for second group of local input of precharge; And
The precharging signal generator is used for first and second groups of local input that precharge is used for second data output mode, and is used for precharge and is used for one of first and second groups of local input of first data output mode,
Wherein said first data output mode is one of 4 Bit data operator schemes and 8 Bit data operator schemes, and described second data output mode is 16 Bit data operator schemes.
2. according to the semiconductor storage unit of claim 1, wherein, described precharging signal generator comprises:
The signal generation unit is selected in precharge, is used in response to first data output mode and internal address signal, produces precharge and selects signal; And
The precharging signal generation unit is used for selecting signal and reset signal in response to corresponding precharge, produces precharging signal, first and second groups of local input of described reseting signal reset.
3. according to the semiconductor storage unit of claim 2, wherein, described precharge selects the signal generation unit to comprise:
First rejection gate, the various operator schemes that are used for being received in semiconductor storage unit are used to instruct the signal and being used to of 4 Bit data operator schemes to instruct the signal of 8 Bit data operator schemes;
First phase inverter is used for the output signal of anti-phase first rejection gate;
First Sheffer stroke gate is used to receive the output signal and the internal address signal of first phase inverter, and produces first precharge selection signal that is used to select first precharge unit; And
Second Sheffer stroke gate is used to receive the output signal of first Sheffer stroke gate and the output signal of first phase inverter, and produces second precharge selection signal that is used to select second precharge unit.
4. according to the semiconductor storage unit of claim 3, wherein, described precharging signal generation unit comprises:
First group of two phase inverter is used to cushion described reset signal;
Second group of two phase inverter is used to cushion described first precharge and selects signal;
The 3rd group of two phase inverters are used to cushion described second precharge and select signal;
The 3rd Sheffer stroke gate is used to receive the output signal of first and second groups of phase inverters, and produces first precharging signal that is used for first group of local input of precharge; And
The 4th Sheffer stroke gate is used to receive the output signal of first and the 3rd group of phase inverter, and produces second precharging signal that is used for second group of local input of precharge.
5. semiconductor storage unit comprises:
Last memory block is used for exporting stored data according to first data output mode and second data output mode;
Following memory block is used for exporting stored data according to first data output mode and second data output mode;
First precharge unit is used for the local input of memory block in the precharge;
Second precharge unit is used for the local input of memory block under the precharge; And
The precharge controller is used for controlling first and second precharge unit according to first data output mode or second data output mode,
Wherein said first data output mode is one of 4 Bit data operator schemes and 8 Bit data operator schemes, and described second data output mode is 16 Bit data operator schemes.
6. according to the semiconductor storage unit of claim 5, wherein, described precharge controller optionally activates first precharge unit or second precharge unit for 4 Bit data operator schemes and 8 Bit data operator schemes, and deactivation second precharge unit or first precharge unit.
7. according to the semiconductor storage unit of claim 6, wherein, described precharge controller activates first and second precharge unit for 16 Bit data operator schemes.
8. according to the semiconductor storage unit of claim 7, wherein, described precharge controller comprises:
The signal generation unit is selected in precharge, is used for producing precharge selection signal in response to first data output mode and internal address signal; And
The precharging signal generation unit is used for selecting signal and reset signal in response to corresponding precharge, produces precharging signal, the local input of memory block and following memory block on the described reseting signal reset.
9. according to the semiconductor storage unit of claim 8, wherein, described precharge selects the signal generation unit to comprise:
First rejection gate, the various operator schemes that are used for being received in semiconductor storage unit are used to instruct the signal and being used to of 4 Bit data operator schemes to instruct the signal of 8 Bit data operator schemes;
First phase inverter is used for the output signal of anti-phase first rejection gate;
First Sheffer stroke gate is used to receive the output signal and the internal address signal of first phase inverter, and produces first precharge selection signal that is used to select first precharge unit; And
Second Sheffer stroke gate is used to receive the output signal of first Sheffer stroke gate and the output signal of first phase inverter, and produces second precharge selection signal that is used to select second precharge unit.
10. according to the semiconductor storage unit of claim 9, wherein, described precharging signal generation unit comprises:
First impact damper is used to cushion described reset signal;
Second impact damper is used to cushion described first precharge and selects signal;
The 3rd impact damper is used to cushion second precharge and selects signal;
The 3rd Sheffer stroke gate is used to receive the output signal of first and second impact dampers, and produces first precharging signal of the local input that is used for memory block in the precharge; And
The 4th Sheffer stroke gate is used to receive the output signal of the first and the 3rd impact damper, and produces second precharging signal of the local input that is used for memory block under the precharge.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR90841/05 | 2005-09-28 | ||
| KR20050090841 | 2005-09-28 | ||
| KR1020060037512A KR100772708B1 (en) | 2005-09-28 | 2006-04-26 | Semiconductor memory device |
| KR37512/06 | 2006-04-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1941181A CN1941181A (en) | 2007-04-04 |
| CN1941181B true CN1941181B (en) | 2010-12-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101412288A Expired - Fee Related CN1941181B (en) | 2005-09-28 | 2006-09-28 | Semiconductor memory device |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR100772708B1 (en) |
| CN (1) | CN1941181B (en) |
| TW (1) | TWI319880B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101274204B1 (en) * | 2007-08-08 | 2013-06-17 | 삼성전자주식회사 | Precharge method of local input output line and semiconductor memory device for using the method |
| KR100893576B1 (en) * | 2007-08-29 | 2009-04-17 | 주식회사 하이닉스반도체 | Semiconductor memory device |
| KR101311455B1 (en) * | 2007-08-31 | 2013-09-25 | 삼성전자주식회사 | Semiconductor memory device and the method for layout thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1154561A (en) * | 1995-10-16 | 1997-07-16 | 精工爱普生株式会社 | Semiconductor storage device and electronic equipment using the same |
| US6205069B1 (en) * | 1999-02-05 | 2001-03-20 | Samsung Electronics Co., Ltd. | Semiconductor memory device with fast input/output line precharge scheme and method of precharging input/output lines thereof |
| US6661721B2 (en) * | 2001-12-13 | 2003-12-09 | Infineon Technologies Ag | Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits |
| US6788599B2 (en) * | 2001-06-29 | 2004-09-07 | Hynix Semiconductor Inc. | Auto precharge apparatus having autoprecharge gapless function protecting circuit in semiconductor memory device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828610A (en) * | 1997-03-31 | 1998-10-27 | Seiko Epson Corporation | Low power memory including selective precharge circuit |
| KR100333642B1 (en) * | 1999-06-30 | 2002-04-24 | 박종섭 | Local databus precharge method for high speed operation of semiconductor memory device |
| KR100939116B1 (en) * | 2003-07-23 | 2010-01-28 | 주식회사 하이닉스반도체 | Semiconductor memory device for reducing current consumption during precharge operation |
-
2006
- 2006-04-26 KR KR1020060037512A patent/KR100772708B1/en active IP Right Grant
- 2006-09-20 TW TW095134776A patent/TWI319880B/en not_active IP Right Cessation
- 2006-09-28 CN CN2006101412288A patent/CN1941181B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1154561A (en) * | 1995-10-16 | 1997-07-16 | 精工爱普生株式会社 | Semiconductor storage device and electronic equipment using the same |
| US6205069B1 (en) * | 1999-02-05 | 2001-03-20 | Samsung Electronics Co., Ltd. | Semiconductor memory device with fast input/output line precharge scheme and method of precharging input/output lines thereof |
| US6788599B2 (en) * | 2001-06-29 | 2004-09-07 | Hynix Semiconductor Inc. | Auto precharge apparatus having autoprecharge gapless function protecting circuit in semiconductor memory device |
| US6661721B2 (en) * | 2001-12-13 | 2003-12-09 | Infineon Technologies Ag | Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200729224A (en) | 2007-08-01 |
| KR20070035937A (en) | 2007-04-02 |
| KR100772708B1 (en) | 2007-11-02 |
| CN1941181A (en) | 2007-04-04 |
| TWI319880B (en) | 2010-01-21 |
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