CN1947251A - 具有表面下台阶式浮栅的双电可擦可编程只读存储器型存储晶体管 - Google Patents

具有表面下台阶式浮栅的双电可擦可编程只读存储器型存储晶体管 Download PDF

Info

Publication number
CN1947251A
CN1947251A CNA2005800123759A CN200580012375A CN1947251A CN 1947251 A CN1947251 A CN 1947251A CN A2005800123759 A CNA2005800123759 A CN A2005800123759A CN 200580012375 A CN200580012375 A CN 200580012375A CN 1947251 A CN1947251 A CN 1947251A
Authority
CN
China
Prior art keywords
array
electrode
common substrate
memory cell
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2005800123759A
Other languages
English (en)
Inventor
B·洛耶克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of CN1947251A publication Critical patent/CN1947251A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/10—Floating gate memory cells with a single polysilicon layer

Abstract

一种具有成行成列地设置的存储单元(13)的存储器数组(10)，每一存储单元具有双EEPROM(15，115)，其特征在于具有用于集中电场的表面下台阶(53，54)式浮栅。EEPROM只使用一单多晶硅层，其的一部分为每一EEPROM的浮栅(82，84)，而另一部分则为字线(WL1，WL2)。双EEPROM通过具有的扩散的控制线(62，64)和扩散的位线(BL1)共享一表面下的共电极(92)。所述双EEPROM对称于该共电极。

Description

具有表面下台阶式浮栅的双电可擦可编程只读存储器型存储晶体管
技术领域
本发明涉及非易失性存储晶体管，尤其涉及一种由这样的适用于一数组的存储单元构成的紧密结构及所述存储单元的制造方法。
背景技术
在皆已转让给本发明的专利受让人的题为“Mirror Image Memory CellTransistor Pairs Featuring Poly Floating Spacers”的在先美国专利申请第10/423.637号和题为“Mirror Image Non-Volatile Memory Cell TransistorPairs with Single Poly Layer”的在先美国专利申请第10/465.718号中，B.Lojek叙述了一种适用于一存储器数组的非易失性MOS存储晶体管的结构，其中在一存储器数组中设置对称的晶体管对。晶体管对共享一在一共阱中的电极，诸如一漏电极，而除此外则是完全独立的。该晶体管对在一对隔离区之间制造并共享同一衬底区，几乎与在其处构建一单一晶体管一样。
在现有技术中，业已有人发明可存储两个数据位的单一MOS浮栅晶体管以作为一种达致高紧密度的方法。因为在一非易失性存储器数组中往往存储数百万的数据位，因此小小的空间节省通过数组都会按比例大大地放大。在已转让给本发明的专利受让人的题为“Multi-Level Memory Cell withLateral Floating Spacers”的美国专利中，B.Lojek叙述了两个在一导电栅极的对侧的隔离层如何作用为用于分离的二进制数据的独立电荷存储区，从而使一单一非易失性MOS晶体管可存储两个二进制数据位。每一存储单元皆与两位线和一字线连接。该些位线分相工作，以致于在一单时钟周期中，可先使第一位线工作，随后再使另一位线工作，而字线则在整个时钟周期中都工作。通过这种方式，就可以在一单时钟周期中存取该两个存储区域以进行一读出或写入操作。
在授予M.Chang的美国专利6,043,530中，示出了一种使用带一带隧穿的MOS存储晶体管结构。在授予F.Gonzalez等人的美国专利6,323,088中，示出了一种具有分相位线的多位电荷存储晶体管寻址方案。
在现有技术中，已知有多种多位电荷存储结构，其可在一存储数组中获得良好的数据密度而不放弃任何宝贵的芯片空间。随着密度的增加，所遇到的问题之一是在存储位置之间的串扰数量的增加。由于电荷存储器结构是如此之小，所以一电荷存储位置有时会影响另一位置。另一方面，电荷存储位置的分隔物会放弃芯片空间。每一数据位的基本分隔物为一专用晶体管。因此，本发明的一个目的在于提供良好的由专用晶体管所提供的数据位分隔物，同时又可使适用于一非易失性存储器数组的多位电荷存储结构的密度高。
发明内容
上述目的通过一种具有一些带双EEPROM(电可擦可编程只读存储器)存储晶体管的存储单元的存储器数组来实现，所述双EEPROM存储晶体管所占用的空间几乎与一单EEPROM存储晶体管相同。每一所述单元的双晶体管对称地设置于一共衬底以及其特征在于一单多晶硅层，该多晶硅层的部分用作为在衬底表面的水平下形成台阶的浮栅，幷通过薄的氧化物与衬底绝缘。该浮栅与一表面下的电极电连接，该表面下的电极参与向该浮栅的电荷转移。常用的EEPROM控制极可由一第一电容器替代，其中用于形成浮栅的所述多晶硅层的部分延伸以形成该第一电容器的一第二极板。该第一电容器的第一极板为一与一相控信号源连接的控制线；藉此该些双单元的极板的相位调整使每一晶体管可独立地作用。每一晶体管的漏极与一第二电容器的一个极板和一位线连接，而第二极板则与字线连接。
通过使浮栅进入到衬底中并在该衬底中形成一浮栅角，自一表面下的电极的电场强度会增大和提高隧道效应。
附图说明
图1是形成本发明的存储器数组的核心的存储单元的电示意图。
图2是用于图1所示的存储单元中的存储晶体管的在早期制造阶段的侧视图。
图3是用于制成图2的侧视图所示的衬底台阶的掩模的俯视图。
图4是图1所示的双存储器单元在早期制造阶段的布置的俯视图。
图5是沿图4所示的5-5线所取的侧面剖面图。
图6是沿图4所示的6-6线所取的侧面剖面图。
图7是图1所示的双存储器单元在中期制造阶段的布置的俯视图。。
图8是沿图7所示的8-8线所取的侧面剖面图。
图9是继图8之后的在后期制造阶段的侧面剖面图。
图10是迭加在图7所示的俯视图上的接触式掩模的俯视图，图中示出了单多晶硅层的导体阴影。
图11是图1所示双对称存储单元的电示意图，用于与图10进行比较，幷包括了图10所示的触点的位置。
具体实施方式
参照图1，可见一在一存储器数组10中的存储单元13分别具有第一和第二非易失性存储晶体管15和115。第一存储晶体管15具有一连接着选择电容器19的漏极21，一连接着控制电容器29的浮栅23和一连接着源极触点27的源极25。
选择电容器19具有一连接着第一存储晶体管15的漏极21和第一位线BL1的第一电极31。选择电容器19的第二电极33连接着字线WL1。字线WL1从第一电极31沿着线35延伸进入另一单元。存储晶体管15的浮栅23连接着控制电容器29的一第一电极37，而第二电极39连接着第一控制线端点41。一在控制线端点41上的脉冲对第二电极39充电，使感应电荷出现在第一电极37上，其与电极23一起形成一浮栅。这是使电荷出现在浮栅23上的两种方式的其中之一。使电荷出现的另一种方法是通过隧道效应或是从源极或漏极21和25注入电子。当将一电压施加在位线BL1和将另一电压施加在源极触点27时，电荷就可以通过隧道电荷输送机制输送到浮栅23上。和字线WL1沿着沿线35延伸进入同一列中的另一存储单元一样，位线BL1也沿着线43延伸进入一在同一行中的存储单元。
第二存储晶体管115与第一存储晶体管15相对于源极触点27呈对称。第二存储晶体管115具有一可由控制电容器129充电的浮栅123。存储晶体管115具有一连接着选择电容器119的第一极板131的漏极电极121和一连接着源极触点27的源极电极125。第一极板131也连接着位线BL1。电容器119的第二极板连接着字线WL2。该字线WL2从第一电极131沿着通往一控制电容器(图中未示)的线135延伸进入一在相同列中邻接单元。位线43同样从选择电容器119的第一电极延伸进入一在相同行中的邻接单元。
存储单元13是存储器数组10中的典型存储单元。每一单元都可见具有一双相对于一源极触点，诸如源极触点27呈对称的非易失性存储晶体管。两个存储晶体管一方面具有与两个控制电容器相关联的浮栅以及在另一方面具有与两个选择电容器相关联的漏极或源极电极。与该些控制电容器相关联的两个控制线端点41和141使该两个存储晶体管可以编程以致于每一晶体管彼此可相互独立，即使其共享一在触点27处的共源电极和共享位线BL1。存储单元13与两个字线WL1和WL2以及一个位线BL1相关联。
参照图2，一P型硅晶圆提供一掺杂成具有一带有一表面54的P阱的衬底，一层薄的氧化物层57在该表面上生长。该氧化层的厚度大约为100埃。氧化层可覆盖一层厚的光刻胶层51，然后以一如图3所示的掩模52形成图案。该掩模接近正方形，其尺寸接近光刻技术的分辨率下限。随后，对光刻胶进行蚀刻以使轮廓分明的台阶53和54形成一凹部58，其具有的在衬底表面56下的顶角和底角的深度约为500埃。台阶53和54的对向角将增强该些延伸至圆片的平面表面的双存储晶体管的浮栅附近的电场强度。每一台阶的顶部和底部的角对于增加电场强度以提高隧道效应是十分重要的。该些浮栅建立于台阶上但通过栅极氧化层57与衬底绝缘。
参照图4，所示为一限定两个存储单元的有源区的一掩模块。该掩模块包括限定双EEPROM的共源极电极的掩模52和55，以及限定控制线的掩模62和64以及掩模66和68。两个线型掩模限定平行的位线BL1和BL2。掩模周围的区域可通过一如图5所示的浅沟槽隔离来隔离。在一P型硅圆片衬底的P阱或P衬底50中的沟槽(见图6)可充填介电绝缘材料72、74、76、78和80(见图5)，诸如二氧化硅。非电介质材料的区域可通过扩散或注入的方式进行掺杂。这使存储单元具有扩散的位线BL1和BL2。
参照图6，当完成表面下的区域的掺杂时，衬底上可覆盖氧化层，正如先前在图2中所述但图6中则未示，并且在P阱或P衬底50的表面56下面形成凹部58。该凹部58具有会形成存储晶体管中的浮栅的一部分的台阶或角53和54。在图4中也见该些台阶或角53或54。
参照图7，可见该些在先前参照图4所述的扩散区。该些扩散区包括源极掩模52和55以及控制线扩散62、64、66和68。还可见扩散的位线BL1和BL2。所有这些结构，包括台阶或角53和54都在P阱或P衬底的表面之下。
在衬底的表面沉积一层多晶硅，然后进行蚀刻，留下浮件82、84、86和88。该些浮件的一部分会变成双EEPROM晶体管的浮栅。该些浮件具有在控制线扩散62和64以及控制线扩散66和68上的延伸部分。部分浮件还在源极掩模区52和55上延伸。该多晶硅层还用于限定该些定距相隔且位于存储单元核心的外侧的字线WL1和WL2。
在图8中，可见该P阱衬底50与栅极氧化层57，其在该衬底表面包括该凹部58之上。沉积在该衬底上的多晶硅层具有限定浮栅82和84的部分以及沿着台阶或角53和54的轮廓的部分。在浮栅区82和84的外面为多晶硅字线WL1及WL2。
图9接着图8为制造过程中的另一个点。在P阱衬底50中已进行了表面下的注入，具体地说，是源极注入92以及漏极注入94和96。还可见到该表面下的位线扩散BL1。该多晶硅浮栅82和84具有侧壁隔离层，例如，围绕浮栅82的侧壁隔离层83和85。同样地，字线WL1和WL2具有侧壁隔离层，诸如与字线WL1相关联的隔离层87和89。在构成隔离层以后，一电介质间层101沉积在该多晶硅层上。该电介质间层101被掩模幷加以蚀刻以构成使金属触点102、104和106可以插入的通孔。该些导电金属触点与表面下的区域相连。金属触点102和106与扩散的位线BL1相连。金属触点104与一表面下的共电极92相连。图10显示了金属触点与图7俯视图的关系。
在图10中，可见金属触点102、104和106的位置，还可见与控制线扩散62和64相关联的触点112和114。触点104位于该限定一用于幷排的双存储晶体管的共电极的掩模52的中心。换句话说，触点104是位于双EEPROM晶体管的一对称平面中。在图10中，该单多晶硅层被画上阴影，而该层的形成多晶硅件82和84的部分，限定该些成型浮栅，其与该些向着该共源极的表面下的台阶相关联。该多晶硅层的其它部分限定该些字线WL1和WL2，正如图中阴影所示。应该注意，该些多晶硅件82和84在控制线扩散62和64上延伸。该些控制线扩散分别具有金属触点112和114。
在图11中，其相对于图1所示的存储单元的电示意图标出了图10所示的俯视图中的存储单元触点的位置。每一存储单元总共用了5个触点，而两个触点102和106是在位线BL1上。触点104与在对称的双存储晶体管之间的共源极相关联。触点112和114与电容器29和129相关联。图11可投射到图10之上，以便对各种不同电路组件做一粗略的比较。在图10中，可见字线WL1重迭在位线BL1上面，但彼此通过绝缘材料定距相隔，从而构成图11中的电容器19。同样地，可见一部分的多晶硅件82重迭在控制线扩散62之上，从而构成图11中的电容器29。

Claims (11)

1.一种具有多行和多列存储单元的非易失性存储器数组，每一存储单元包括：
对称地设置在一具有一平面表面的共衬底上并共享一共电极的第一和第二非易失性存储晶体管，每一所述非易失性存储晶体管具有：一在所述共衬底上电浮动的单多晶硅层，所述单多晶硅层的一第一部分呈一具有一台阶的结构，所述台阶在所述共衬底的所述平面表面下延伸并通过一氧化层与所述共衬底相隔开，从而使电浮动的所述单多晶硅层作用为一浮栅；以及具有一与所述浮栅连接的配置成作用为一控制电极的电容器，所述浮栅通过所述氧化层可与一表面下的电极电连接；
分别设置在所述第一和第二非易失性存储晶体管的外侧的第一和第二字线，所述字线由在同一列中的多个存储单元共享，一横过所述字线的位线与所述字线成电容关系以及也与所述第一和第二非易失性存储晶体管的所述浮栅成电容关系；以及
第一和第二控制线，每一控制线为与每一所述非易失性存储晶体管相关联的所述电容器的一极板。
2.如权利要求1所述的数组，其特征在于，所述共电极为一表面下的源极或漏极电极，所述存储单元相对于所述共电极对称地排列。
3.如权利要求1所述的数组，其特征在于，所述第一和第二控制线分相工作，从而使所述共电极可由所述存储单元中的其中一个作瞬时的专有使用。
4.如权利要求1所述的数组，其特征在于，所述位线扩散入所述共衬底内。
5.如权利要求1所述的数组，其特征在于，所述字线设置于所述共衬底上并通过一氧化层与所述共衬底相隔开。
6.如权利要求1所述的数组，其特征在于，所述第一和第二控制线定距相隔并且为共线。
7.如权利要求5所述的数组，其特征在于，所述第一和第二字线为所述单多晶硅层的第二部分。
8.如权利要求1所述的数组，其特征在于，所述台阶在所述共衬底的所述平面表面下延伸至一相等于400至600埃的深度。
9.如权利要求1所述的数组，其特征在于，所述台阶具有顶角和底角。
10.如权利要求6所述的数组，其特征在于，共线的所述第一和第二控制线与在同一列中的邻接存储单元的位线通过一由浅沟槽隔离沟槽所占的间距相隔开。
11.如权利要求6所述的数组，其特征在于，共线的所述第一和第二控制线扩散入所述共衬底内。
CNA2005800123759A 2004-02-23 2005-02-10 具有表面下台阶式浮栅的双电可擦可编程只读存储器型存储晶体管 Pending CN1947251A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/785,160 US6998670B2 (en) 2003-04-25 2004-02-23 Twin EEPROM memory transistors with subsurface stepped floating gates
US10/785,160 2004-02-23

Publications (1)

Publication Number Publication Date
CN1947251A true CN1947251A (zh) 2007-04-11

Family

ID=34911439

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2005800123759A Pending CN1947251A (zh) 2004-02-23 2005-02-10 具有表面下台阶式浮栅的双电可擦可编程只读存储器型存储晶体管

Country Status (5)

Country Link
US (3) US6998670B2 (zh)
EP (1) EP1721336A2 (zh)
CN (1) CN1947251A (zh)
TW (1) TW200532758A (zh)
WO (1) WO2005081798A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934432A (zh) * 2014-03-21 2015-09-23 爱思开海力士有限公司 具有单层浮栅的非易失性存储器件
CN114464526A (zh) * 2022-04-12 2022-05-10 晶芯成(北京)科技有限公司 多次可编程存储器及其制备方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6998670B2 (en) * 2003-04-25 2006-02-14 Atmel Corporation Twin EEPROM memory transistors with subsurface stepped floating gates
US6888192B2 (en) * 2003-04-25 2005-05-03 Atmel Corporation Mirror image non-volatile memory cell transistor pairs with single poly layer
KR100468787B1 (ko) * 2003-05-02 2005-01-29 삼성전자주식회사 래치-업(Ｌａｔｃｈ-ｕｐ)에 의한 전류 흐름을 방지할 수있는 반도체 장치
US7102188B1 (en) * 2005-04-05 2006-09-05 Ami Semiconductor, Inc. High reliability electrically erasable and programmable read-only memory (EEPROM)
US8997255B2 (en) 2006-07-31 2015-03-31 Inside Secure Verifying data integrity in a data storage device
US7439567B2 (en) * 2006-08-09 2008-10-21 Atmel Corporation Contactless nonvolatile memory array
US8352752B2 (en) * 2006-09-01 2013-01-08 Inside Secure Detecting radiation-based attacks
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US7868370B2 (en) * 2008-04-14 2011-01-11 Macronix International Co., Ltd. Single gate nonvolatile memory cell with transistor and capacitor
US7999296B2 (en) 2008-04-14 2011-08-16 Macronix International Co., Ltd. Single gate nonvolatile memory cell with transistor and capacitor
CN116114394A (zh) * 2020-09-17 2023-05-12 铠侠股份有限公司 半导体存储装置

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814594A (en) * 1982-11-22 1989-03-21 Drexler Technology Corporation Updatable micrographic pocket data card
US4649520A (en) * 1984-11-07 1987-03-10 Waferscale Integration Inc. Single layer polycrystalline floating gate
IT1191566B (it) * 1986-06-27 1988-03-23 Sgs Microelettronica Spa Dispositivo di memoria non labile a semiconduttore del tipo a porta non connessa (floating gate) alterabile elettricamente con area di tunnel ridotta e procedimento di fabbricazione
US5067002A (en) * 1987-01-30 1991-11-19 Motorola, Inc. Integrated circuit structures having polycrystalline electrode contacts
IT1214246B (it) * 1987-05-27 1990-01-10 Sgs Microelettronica Spa Dispositivo di memoria non volatile ad elevato numero di cicli di modifica.
KR0185375B1 (ko) * 1989-05-23 1999-03-20 엔. 라이스 머레트 분리 금속 플레이트 캐패시터 및 이의 제조 방법
US5026663A (en) * 1989-07-21 1991-06-25 Motorola, Inc. Method of fabricating a structure having self-aligned diffused junctions
DE58909837D1 (de) * 1989-09-22 1998-09-17 Siemens Ag Verfahren zur Herstellung eines Bipolartransistors mit verminderter Basis/Kollektor-Kapazität
JP2563683B2 (ja) * 1990-03-08 1996-12-11 松下電子工業株式会社 不揮発性半導体記憶装置およびその製造方法
US5021848A (en) * 1990-03-13 1991-06-04 Chiu Te Long Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
US5108939A (en) * 1990-10-16 1992-04-28 National Semiconductor Corp. Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region
US5196722A (en) * 1992-03-12 1993-03-23 International Business Machines Corporation Shadow ram cell having a shallow trench eeprom
JP3229012B2 (ja) * 1992-05-21 2001-11-12 株式会社東芝 半導体装置の製造方法
US5301150A (en) * 1992-06-22 1994-04-05 Intel Corporation Flash erasable single poly EPROM device
JP2541087B2 (ja) * 1992-10-30 1996-10-09 日本電気株式会社 不揮発性半導体記憶装置のデ―タ消去方法
JP2725564B2 (ja) * 1993-09-27 1998-03-11 日本電気株式会社 半導体記憶装置及びそのデータ書込み方法
US5424233A (en) * 1994-05-06 1995-06-13 United Microflectronics Corporation Method of making electrically programmable and erasable memory device with a depression
US5808338A (en) * 1994-11-11 1998-09-15 Nkk Corporation Nonvolatile semiconductor memory
US5512785A (en) * 1994-11-30 1996-04-30 Motorola, Inc. Semiconducter device having an emitter terminal separated from a base terminal by a composite nitride/oxide layer
US6965142B2 (en) * 1995-03-07 2005-11-15 Impinj, Inc. Floating-gate semiconductor structures
KR0144895B1 (ko) * 1995-04-27 1998-07-01 김광호 불휘발성 기억장치의 제조방법
DE69521203T2 (de) * 1995-07-31 2006-01-12 Stmicroelectronics S.R.L., Agrate Brianza Flash-EEPROM mit gesteuerter Entladungszeit der Wortleitungs- und Sourcespannungen nach der Löschung
US5942780A (en) * 1996-08-09 1999-08-24 Advanced Micro Devices, Inc. Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate
US5780341A (en) * 1996-12-06 1998-07-14 Halo Lsi Design & Device Technology, Inc. Low voltage EEPROM/NVRAM transistors and making method
US5761126A (en) * 1997-02-07 1998-06-02 National Semiconductor Corporation Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell
US20010017392A1 (en) * 1997-05-19 2001-08-30 International Business Machines Corporation. Vertical transport MOSFETs and method for making the same
KR100243294B1 (ko) * 1997-06-09 2000-02-01 윤종용 반도체장치의 강유전체 메모리 셀 및 어레이
US6420753B1 (en) * 1997-06-30 2002-07-16 Winbond Memory Laboratory Electrically selectable and alterable memory cells
US5895240A (en) * 1997-06-30 1999-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making stepped edge structure of an EEPROM tunneling window
US5812452A (en) * 1997-06-30 1998-09-22 Winbond Memory Laboratory Electrically byte-selectable and byte-alterable memory arrays
US6051465A (en) * 1997-07-30 2000-04-18 Matsushita Electronics Corporation Method for fabricating nonvolatile semiconductor memory device
JP3474758B2 (ja) * 1998-02-16 2003-12-08 株式会社東芝 不揮発性半導体記憶装置
US6243289B1 (en) * 1998-04-08 2001-06-05 Micron Technology Inc. Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
US6043530A (en) * 1998-04-15 2000-03-28 Chang; Ming-Bing Flash EEPROM device employing polysilicon sidewall spacer as an erase gate
US6180461B1 (en) * 1998-08-03 2001-01-30 Halo Lsi Design & Device Technology, Inc. Double sidewall short channel split gate flash memory
US6160287A (en) * 1998-12-08 2000-12-12 United Microelectronics Corp. Flash memory
US6392271B1 (en) * 1999-06-28 2002-05-21 Intel Corporation Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US6597047B2 (en) * 2000-03-22 2003-07-22 Matsushita Electric Industrial Co., Ltd. Method for fabricating a nonvolatile semiconductor device
EP1172861A3 (en) * 2000-07-12 2003-11-05 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for fabricating the same
JP3699886B2 (ja) * 2000-07-14 2005-09-28 沖電気工業株式会社 半導体記憶回路
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6664143B2 (en) * 2000-11-22 2003-12-16 North Carolina State University Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls
US6465306B1 (en) * 2000-11-28 2002-10-15 Advanced Micro Devices, Inc. Simultaneous formation of charge storage and bitline to wordline isolation
US6479351B1 (en) * 2000-11-30 2002-11-12 Atmel Corporation Method of fabricating a self-aligned non-volatile memory cell
JP2002184877A (ja) * 2000-12-15 2002-06-28 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置及びその製造方法
US6468863B2 (en) * 2001-01-16 2002-10-22 Taiwan Semiconductor Manufacturing Co., Ltd Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof
US6757196B1 (en) * 2001-03-22 2004-06-29 Aplus Flash Technology, Inc. Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device
US6563733B2 (en) * 2001-05-24 2003-05-13 Winbond Electronics Corporation Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell
US6661705B1 (en) * 2001-09-20 2003-12-09 Agere Systems Inc. Low voltage flash EEPROM memory cell with improved data retention
TW513759B (en) * 2001-12-28 2002-12-11 Nanya Technology Corp Manufacturing method of floating gate and control gate of flash memory
TWI267980B (en) * 2002-04-16 2006-12-01 Macronix Int Co Ltd Method for fabricating non-volatile memory having P-type floating gate
US6818936B2 (en) * 2002-11-05 2004-11-16 Taiwan Semiconductor Manufacturing Company Scaled EEPROM cell by metal-insulator-metal (MIM) coupling
US6998670B2 (en) * 2003-04-25 2006-02-14 Atmel Corporation Twin EEPROM memory transistors with subsurface stepped floating gates
US7232732B2 (en) * 2003-10-06 2007-06-19 Atmel Corporation Semiconductor device with a toroidal-like junction
US6919242B2 (en) * 2003-04-25 2005-07-19 Atmel Corporation Mirror image memory cell transistor pairs featuring poly floating spacers
US6888192B2 (en) * 2003-04-25 2005-05-03 Atmel Corporation Mirror image non-volatile memory cell transistor pairs with single poly layer
US7169660B2 (en) * 2003-10-06 2007-01-30 Atmel Corporation Lithography-independent fabrication of small openings for forming vertical mos transistor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934432A (zh) * 2014-03-21 2015-09-23 爱思开海力士有限公司 具有单层浮栅的非易失性存储器件
CN104934432B (zh) * 2014-03-21 2019-05-07 爱思开海力士有限公司 具有单层浮栅的非易失性存储器件
CN114464526A (zh) * 2022-04-12 2022-05-10 晶芯成(北京)科技有限公司 多次可编程存储器及其制备方法
CN114464526B (zh) * 2022-04-12 2022-06-17 晶芯成(北京)科技有限公司 多次可编程存储器及其制备方法

Also Published As

Publication number Publication date
US6998670B2 (en) 2006-02-14
EP1721336A2 (en) 2006-11-15
US20060113583A1 (en) 2006-06-01
WO2005081798A2 (en) 2005-09-09
TW200532758A (en) 2005-10-01
US20040212005A1 (en) 2004-10-28
WO2005081798A3 (en) 2005-11-24
US20060118856A1 (en) 2006-06-08

Similar Documents

Publication Publication Date Title
CN1947251A (zh) 具有表面下台阶式浮栅的双电可擦可编程只读存储器型存储晶体管
US8114737B2 (en) Methods of forming memory cells on pillars and memories with memory cells on pillars
US5012309A (en) Semiconductor memory device comprising capacitor portions having stacked structures
US20070134875A1 (en) Multi-level memory cell array with lateral floating spacers
KR20180096877A (ko) 3차원 반도체 메모리 장치 및 그 동작 방법
US6479348B1 (en) Method of making memory wordline hard mask extension
CN1315180C (zh) 具有位线隔离的内存制造方法
KR100543471B1 (ko) 노어형 플래시 메모리 셀의 콘택 구조 형성방법
US11812609B2 (en) Three-dimensional semiconductor device having a first main separation structure and a second main separation structure on a lower structure
US10636812B1 (en) Reducing word line capacitance in 3D memory
US20220059566A1 (en) Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
CN114649340A (zh) 三维存储器元件及其制造方法
CN1992235A (zh) Nor型闪存单元阵列及其制造方法
US20210313340A1 (en) Memory device
KR19980055726A (ko) 플래쉬 메모리 소자 및 이를 이용한 프로그램, 소거 및 독출방법
US20220285372A1 (en) Semiconductor memory device and method of manufacturing the semiconductor memory device
US20240023335A1 (en) Memory device
US20240074196A1 (en) Memory device
US20230067598A1 (en) Three-dimensional flash memory supporting hole injection erase technique and method for manufacturing same
US20230217655A1 (en) 3d and flash memory device
JPS63166A (ja) 不揮発性半導体記憶装置
KR20220142314A (ko) 3차원 가상 접지 메모리 및 그 제조 방법들
US7439567B2 (en) Contactless nonvolatile memory array
CN114188320A (zh) 半导体结构和半导体结构的制造方法
WO2023101753A1 (en) Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
AD01 Patent right deemed abandoned
C20 Patent right or utility model deemed to be abandoned or is abandoned