CN1957462A - 竖直堆叠的半导体器件 - Google Patents

竖直堆叠的半导体器件 Download PDF

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Publication number
CN1957462A
CN1957462A CNA2005800165291A CN200580016529A CN1957462A CN 1957462 A CN1957462 A CN 1957462A CN A2005800165291 A CNA2005800165291 A CN A2005800165291A CN 200580016529 A CN200580016529 A CN 200580016529A CN 1957462 A CN1957462 A CN 1957462A
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China
Prior art keywords
chip
semiconductor device
island
substrate
metal
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CNA2005800165291A
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English (en)
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K·C·切鲁库瑞
W·J·维格斯
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN1957462A publication Critical patent/CN1957462A/zh
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Abstract

本发明描述了一种半导体器件40，其包括互连在一个衬底上的半导体芯片401、402的竖直组件，所述衬底具有一个或多个金属支座41，金属支座41在每个支撑芯片401和下一个相继的竖直堆叠芯片402之间提供了固定间距。该器件的制造是通过在每个支撑芯片的钝化层顶上图案化铝岛，并同时进行加工以形成接合垫帽来实现的。该制造工艺不需要额外的成本，并具有以晶片形式进行加工以为多个芯片提供支座的优点，从而避免了额外的组装成本。此外，这些支座改善了器件的散热，并且提供了均匀稳定的接合表面，以便使每个所述芯片被引线接合到所述衬底。

Description

竖直堆叠的半导体器件
技术领域
【0001】本发明涉及一种半导体电路器件；更具体地是涉及一种竖直堆叠的半导体芯片器件及其制造方法。
背景技术
【0002】在为了支持系统级需求而针对较高电路集成度进行的研究中，已经探索出许多途径。具体而言，芯片特征尺寸已被大大减小；晶片加工技术已被改变，从而允许不同类型的电路处于同一芯片上；并且封装尺寸和占用面积(foot print)已被减至最小。每种方法都受限于器件制造商和终端用户的技术水平和成本约束。
【0003】一种用来集成功能和减小器件尺寸(其有利于更小型和较高性能的系统)的方法是将多个芯片组装在单个封装件内。相同或不同器件技术的多个芯片被包含在提供了到下一级互连的接触件的互连衬底上和/或单个封装件中。
【0004】同一封装件中多个芯片的集成在水平和竖直平面中都已开发出。历史上，存储器电路的竖直集成已经以单个器件的形式提供了在相同占用面积之内具有增加的存储容量的堆叠器件10，如图1所示。具有相对较少管脚数的许多类似芯片11被连接到独立的插入器13。这些组件被堆叠在彼此的顶上，并且彼此互连，并且互连到外部接触件12。
【0005】近来，如图2所示，不同类型的多个硅芯片21已经被组装成竖直堆，该竖直堆在每个活动或有效器件21之间具有支座或绝缘体(standoffs)24，以使互连间隔开和允许在衬底23上制造互连。芯片21通过衬底23上的导电迹线互连。通常，每个芯片21通过绝缘材料24与竖直相继的芯片隔开。堆叠的芯片组件对于将集成电路耦合到存储器器件(例如，随机存取存储器、E2PROM、闪存或缓冲存储器)特别重要，其处，芯片间快速的相互作用非常关键。存储器电路的晶片制造并不易于与其它IC晶片制造技术兼容，而且集成起来也很困难且成本较高。因此，提供与功能芯片进行快速相互作用的堆叠芯片组件是节约成本的。
【0006】已用作支座隔开竖直堆叠芯片的材料包括：聚合物膜、叠层材料、粘结剂、裸硅片，和/或这些材料的组合。
【0007】聚合物膜可被应用于晶片，并对聚合物膜进行光图案化以暴露出接合垫(或称焊盘)，从而提供这样的优点：将其作为具有多个芯片的晶片来处理，而不是作为器件最后组装期间的独立芯片来处理。然而，每个额外的加工步骤都会显著增加晶片成本，并且会增加产生缺陷的概率，这造成了代价高昂的成品率损失。组装期间，用作支座的其它类型的材料经常需要插入到独立的封装件中。
【0008】引线接合(或称丝焊)是一种将每个半导体芯片连接到衬底或封装件的广泛使用的方法。接合垫是位于IC表面上的导电金属区域，其处，通常为金质的焊线被连接。将铜代替铝用于集成电路中的某些互连311已日益普遍。然而，由于铜在焊接方面的问题，具有铜互连技术的芯片接合垫31常使用铝层33盖在暴露的铜接合垫31的顶上，如图3中芯片30的一部分的横截面视图所图解说明的。铝帽33覆盖铜接合垫31，并且叠置在钝化层32上，从而允许使用那些与用于具有铝互连技术芯片相同的引线接合工具和工艺。
【0009】众所周知，随着脆性硅芯片的尺寸增加，以及芯片被粘合到不同材料的衬底上时，会产生热应力和机械应力，其可导致成品率和可靠性故障。这些应力不仅会造成机械变形以及芯片、互连或互连界面破裂，而且在高速器件中，芯片的响应时间也可能发生改变，从而影响器件性能。避免包含由膨胀系数不相似的材料制成的厚的连续层，有助于减轻硅芯片上由热产生的应力。
【0010】竖直堆叠芯片的另一个主要考虑是，在增加的加工步骤期间或者在组装工艺本身期间产生的缺陷所导致的成品率损失，其中所述增加的加工步骤对于将芯片准备好以便组装是必须的。由于制造费用和成品率损失，额外加工步骤的成本高昂。
【0011】在小占用面积内对半导体芯片进行可靠的高密度组装的方法是一个重要目标；而一种使用现有技术和设备的、用于低成本地组装这类器件的方法也是受欢迎的。
发明内容
【0012】根据本发明的一个实施例，提供了一种半导体器件，其包括一个互连在衬底上的半导体芯片的竖直组件。在支撑芯片上图案化的金属支座在支撑芯片和相继的竖直堆叠芯片之间提供了一个固定间隔。接合引线或引线结合(wire bond)将每个芯片连接到衬底，并且聚合物粘结剂将第一芯片固定到衬底，将相继的芯片固定到它们各自的支撑芯片。支撑芯片是竖直器件组件中其顶上布置有其它芯片的任何芯片。在一个给定器件中，可以具有一个以上的支撑芯片和一个以上的第二或堆叠芯片。优选地，该器件处于单个半导体封装件的占用面积之内。
【0013】在该优选实施例中，支座是包含铝的图案化的岛，其被沉积和图案化在钝化层的顶上，该钝化层位于每个支撑芯片的活动表面上，所述沉积和图案化与用来形成接合垫帽的加工步骤是同时进行的。该制造过程并没有增加额外的成本，并且具有这样的优点：其通过晶片形式的加工，为多个芯片提供了支座，从而避免了额外的成本。
【0014】具有竖直堆叠芯片的器件不但在器件密度方面具有优点，从而使电路板空间减至最小，而且对于相近放置的相互作用的芯片在加快其操作速度方面也具有优点。使用图案化的铝岛作为堆叠芯片之间的间隔物还提供了额外的优点：其提供了良好的导热性以通过芯片堆散发和传播热量，并避免了额外的处理步骤。此外，由于岛式元件之间不连续，可缓解和减轻半导体芯片和金属岛相异的热膨胀系数所产生的应力。被沉积和蚀刻的岛在整个支撑芯片上具有均匀高度，并提供了一个稳定的引线接合表面。
【0015】本发明的另一个实施例提供了一种半导体芯片，其在钝化层顶上具有一个或多个固定厚度的金属岛。优选地，所述岛包括铝或其它易于通过公知晶片处理技术和设备加工的导热材料。这一实施例的凸起的金属岛作为支座和/或传热器是有用的。
【0016】一种用于以晶片形式在半导体芯片钝化层的顶上制造金属岛的方法，其优选包括沉积一包括铝的金属，同时进行加工以形成接合垫帽。施加光阻材料，对齐包括用于接合垫帽和支座岛的图案的光掩模，以及曝光和显影所述光阻材料。与现有帽的加工相同，不需要的金属是通过蚀刻去除的。一个具有多个芯片的晶片被分成组装到一个封装器件中的独立芯片，所述多个芯片在其钝化层顶上具有图案化的金属岛。该优选方法不会对晶片制造带来任何额外的成本或成品率损失。
【0017】在替换性实施例中，是通过沉积金属、图案化和蚀刻，或者通过掩模(其具有用于岛的开口)进行金属沉积，或者通过电镀来加工芯片的，这些芯片进行了铝互连金属化和/或具有不需要金属帽的接合垫。
【0018】一种用于组装具有图案化金属支座的堆叠芯片器件的优选方法，其包括：将具有金属支座的支撑芯片粘合到互连衬底，将聚合物粘结剂材料施加到支座的顶表面以及支座之间的区域上，在支座的顶上对齐和放置第二芯片。如果该堆中包括两个以上的芯片，就重复该过程。粘结剂(优选为热固性聚合物，例如填充有导热填料的环氧树脂)被固化，并将每个芯片引线接合到所述衬底。该粘结剂在所述支座的顶上形成了一个非常薄的层，从而使得该组件具有良好的导热性和稳定性。
【0019】优选地，堆叠的芯片组件被装在一个BGA封装件或其它在芯片和下一级互连之间具有互连的封装件衬底中。
附图说明
【0020】图1是公知器件，其包括连接到独立插入器的竖直堆叠芯片。
【0021】图2是公知器件，其具有通过绝缘层隔开的竖直堆叠芯片。
【0022】图3是一个公知芯片的一部分的横截面视图，该公知芯片在接合垫的顶上具有金属帽。
【0023】图4是根据本发明的、衬底上的堆叠芯片器件的横截面视图，该堆叠芯片器件具有铝岛分隔器。
【0024】图5a是本发明一个实施例的横截面视图，其包括一对以铝岛作为分隔器的堆叠芯片。
【0025】图5b图解说明了在三个竖直堆叠芯片，这三个竖直堆叠芯片在每个相继的芯片之间具有金属岛式支座。
【0026】图5c是一个堆叠芯片器件的横截面视图，该堆叠芯片器件具有铝岛式支座和并排堆叠的芯片。
【0027】图6a是一个芯片的顶视图，该芯片具有图案化的接合垫帽和岛。
【0028】图6b是一个芯片的横截面，该芯片具有图案化的接合垫帽和岛。
【0029】图7是用于制造根据本发明的具有岛式支座的电路芯片的工艺流程图。
【0030】图8是用于制造根据本发明的堆叠的组件的工艺流程图。
具体实施方式
【0031】图4中，半导体器件40包括衬底44和竖直堆叠芯片401和402，其中多个金属岛式支座41在支撑芯片401的活动前侧和相继或接连的芯片402的非活动背侧之间提供均匀的间隔距离。聚合物材料45将支撑芯片401粘合到衬底44，并且将第二芯片402粘合到支撑芯片401的顶表面。聚合物粘结剂45优选为热固性聚合物，例如填充有导热材料的环氧树脂。粘结剂45在金属岛和第二芯片402的顶上以及之间形成薄的粘合层或接合线(bond line)，从而使引线接合具有良好的导热性，成为稳定组件。接合引线42和43将芯片401和402连接到衬底44上的接合区。衬底44上的导电互连(未示出)，例如BGA(球栅阵列)封装件的基带，提供了芯片间的连接。
【0032】具有竖直堆叠芯片的器件不但在器件密度方面具有优点，从而使电路板空间需求减至最小，而且对于相近放置的相互作用的芯片在加快其操作速度方面也具有优点。用铝或其它金属岛作为间隔器提供了额外的优点：其提供了增加的导热性，以便通过芯片堆来散发和传播热量。对于具有铜互连和带有铝接合垫帽的接合垫的器件，铝岛避免了额外的加工步骤。铝帽便于使用现有的技术和设备对金接合引线进行引线接合。
【0033】此外，由于在大芯片上的岛间隔器优选是不连续的或间断的，因此由活动的半导体部件和金属岛的不相似或相异的热膨胀系数所产生的应力可被缓解和减轻。具有沉积和蚀刻而成的金属岛式支座的堆叠芯片器件在芯片间提供了均匀固定的间隔，并且该组件提供了稳固的接合表面。
【0034】图5是一对竖直堆叠芯片501和502的更详细的横截面视图，其在芯片之间具有图案化的金属岛式支座51。帽52覆盖接合垫53，并且叠置在钝化层511上。支撑芯片501上的金属岛51优选被同时沉积和图案化，因此不需要对现有的晶片制造增加加工步骤或增复杂度。在该优选实施例中，带有金属岛51的支撑芯片501具有包含铜的接合垫53，而接合垫53的帽52包含铝。该芯片顶上的钝化层511典型地为氮化硅、氧氮化硅，或诸如聚酰亚胺族之一的聚合物膜。
【0035】图5a提供了一个竖直堆叠芯片对的实例，但本发明并不限于两个芯片构成的堆，而可包括三个或更多芯片，如在图5b、5c中图解说明的。每个支撑芯片503、504和506分别包括金属支座51、510和516。可以看出，最大的即第一个支撑芯片503具有多个岛式支座51，而较小的支撑芯片504具有单个支座510。在图5c中，两个水平堆叠在支撑芯片506顶上的芯片507优选支撑在间隔开的支座516上。大芯片503上的岛51之间的不连续性允许减少热产生的应力，但较小的芯片505和507可能不需要应力缓解机构。
【0036】堆中最上面的芯片505和507不需要金属岛。然而，为了简化工艺、传热，和/或如果该芯片可能用在需要支座的应用中，也可加上金属岛。
【0037】在另一个实施例中，提供了一个在第一表面上具有金属岛的半导体芯片。图6a和6b是具有多个接合垫63的芯片601的横截面视图，每个接合垫63都被铝帽62覆盖，铝帽62在芯片601的第一表面上的钝化层611上延伸。一个或多个铝岛61被限定在由接合垫界定的区域内。将岛限定在接合垫区域内是为了避免影响竖直堆中支撑芯片上的引线接合工艺，并且是因为电路产生的热量通常分布在中心。
【0038】岛的面积是支撑芯片和堆叠的第二芯片的尺寸的函数。其间间隔开的多个岛优选用于那些可能需要缓解热膨胀不匹配的大芯片中。但对于小芯片，单个岛也是可以接受的。优选地，金属支座足够大，以对第二芯片提供平衡支撑。
【0039】用于制造金属岛以在堆叠芯片之间提供间隔和/或增加半导体器件导热性的优选工艺是在晶片形式中使用现有的金属沉积、光学加工和蚀刻技术。提供一种晶片，其具有包含铜的接合垫，并且具有一个带有用于引线接合的开口的钝化层。在图7中概要性地示出的加工步骤包括：将金属层(优选厚度为5-20kA(千埃)的铝)沉积在晶片的钝化的第一表面上；施加光阻层并将其通过光掩模曝光，该光掩模在每个接合垫的顶上定义了一个帽，并且叠置在所述钝化层上。该掩模在接合垫区域内进一步定义了一个或多个岛。通过蚀刻去除多余的金属，从而留下在钝化表面之上凸起5-20kA范围内的岛。这些加工步骤并没有对具有多个芯片的晶片增加额外的加工成本，并且使成品芯片具有金属岛，这些金属岛可在堆叠芯片组件中作为支座使用，或者改善了集成电路芯片的散热。
【0040】已经对具有铜接合垫和提供适当引线接合表面的铝帽的芯片，描述了相应的器件和制造方法。然而，对于具有铝接合垫或其它不需要帽的接合表面的器件而言，可通过沉积、光图案化和蚀刻，或者可通过经由掩模开口进行沉积，在钝化层的顶上形成金属岛。所沉积的金属可以是铝或具有良好导热性和稳定性的替代的低成本的易沉积金属。
【0041】如图8中概要性地示出的，堆叠芯片器件的组装包括，提供在支撑芯片顶上具有金属岛式支座的集成电路芯片，通过贴片粘结剂将支撑芯片对齐和放置到衬底，将聚合物材料(优选为填充有诸如氧化铝或矾土之类的导热填料的热固性粘结剂)施加到之前描述的支撑芯片上的支座顶上的区域，将第二芯片的背面对齐和放置在所述粘结剂上，并使所有的贴片粘结剂交联。在接下来的步骤中，将每个芯片引线接合到衬底。优选地，通过公知的封装方法为该组件提供机械保护。
【0042】在一个替换性的组装工艺中，在堆叠第二芯片以及接合之前，每个芯片就被引线接合到衬底。
【0043】如果该器件中包括两个以上的竖直堆叠芯片，则将第一芯片和第二芯片以之前所述方式组装，并将粘结剂施加到第二芯片的支座和顶部，使粘结剂固化，从而附连上所述接合引线。
【0044】在那些支撑芯片上具有一个以上并排放置的芯片的器件中，其组装与针对具有两个芯片的堆所描述的相同；即，单次固化和引线接合工艺。
【0045】用于组装支撑芯片上具有金属支座的竖直堆叠芯片器件的每个加工步骤在业内是公知的，并不需要任何额外的设备或工艺过程开发。

Claims (11)

1.一种半导体器件，其包括：
一个具有导电互联的衬底；
位于所述衬底上的两个或多个竖直堆叠的芯片，每个支撑芯片具有位于其上的金属支座，以将该支撑芯片与下一个相继的芯片间隔开；以及
多条接合引线，其将至少一个芯片连接到所述衬底。
2.根据权利要求1所述的半导体器件，其中所述金属支座包括铝岛。
3.根据权利要求1或2所述的半导体器件，其中所述金属支座的厚度为5-20千埃。
4.根据权利要求1-3中任一项所述的半导体器件，其中所述支座被图案化在所述芯片钝化层的上方。
5.根据权利要求1-4中任一项所述的半导体器件，其中所述金属支座是导热的。
6.根据权利要求1-5中任一项所述的半导体器件，其中所述金属支座位于由接合垫包围的区域内。
7.根据权利要求1-6中任一项所述的半导体器件，其中所述第一芯片由一种聚合物粘结剂固定到所述衬底。
8.根据权利要求1-7中任一项所述的半导体器件，其中所述支撑芯片包括具有铝帽的铜接合垫。
9.一种用于制造具有金属岛式支座的半导体芯片的方法，其包括以下步骤：
提供一个半导体晶片，该半导体晶片具有多个覆盖有钝化层的集成电路器件，所述钝化层在顶表面上具有接合垫开口；
将一个包括铝的金属层沉积到所述晶片上；
在所述金属层的顶上形成一层光阻材料；
对齐具有图案的掩模，以便为接合垫加上帽，并且为所述晶片添加岛；
曝光和显影所述光阻材料；
进行蚀刻，以将不需要的金属从所述晶片上去除掉；以及
将所述晶片切割为独立的芯片。
10.一种组装具有竖直堆叠芯片的半导体器件的方法，所述竖直堆叠芯片具有一个或多个固定的金属支座来隔开所述芯片，所述方法包括以下步骤：
提供一个具有接合区和导电互联的衬底；
将聚合物贴片粘结剂施加到所述衬底；
将具有一个或多个金属支座的支撑芯片与所述粘结剂对齐；
在所述支撑芯片上将粘结剂施加到所述岛以及岛间的区域；
在所述支撑芯片上的所述粘结剂的顶上对齐第二芯片；以及
将每个所述芯片引线接合到所述衬底。
11.根据权利要求10所述的方法，进一步包括以下步骤：将粘结剂施加到所述第二芯片上的所述岛，对齐和放置第三芯片，固化所述粘结剂，以及从所述第三芯片至所述衬底进行引线接合。
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