CN1975989B - Polycrystalline silicon film preparation method, polycrystalline silicon and film transistor prepared therefor - Google Patents
Polycrystalline silicon film preparation method, polycrystalline silicon and film transistor prepared therefor Download PDFInfo
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- CN1975989B CN1975989B CN2006101398774A CN200610139877A CN1975989B CN 1975989 B CN1975989 B CN 1975989B CN 2006101398774 A CN2006101398774 A CN 2006101398774A CN 200610139877 A CN200610139877 A CN 200610139877A CN 1975989 B CN1975989 B CN 1975989B
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Abstract
Polycrystalline silicon for use in the fabrication of semiconductor devices is formed by amorphous silicon after metal-induced horizontal crystallization. The present invention related is a technic of using solid-state laser annealed metal-induced crystallization polycrystalline silicon films (including the vertical and horizontal crystallization direction) to fabricate semiconductor devices. A metal-induced polycrystalline silicon thin films is formed throught annealing furnace pipe of amorphous silicon films inducing metal nickel. To improve the quality of the polycrystalline silicon films,solid-state laser is used to execute annealing to the said polycrystalline silicon thin films to reduce the stucture defect of the thin films and the effection of the metal nickel to characters of the thin films, but in the annealing process, the main grain structure of metal-induced polycrystalline silicon is not changed. The solid-state laser is also adopted by the adulteration activation in the devices. Compared with the excimer lasers, the solid-state lasers are relatively inexpensive and have simple operation, and are suitable for industrial production. The polycrystalline silicon materials have a wide range of potential applications, including for example insensors, electronic devices, plane display and three-dimensional circuits, etc.
Description
Technical field
The present invention told about is to use the technology of metal inducing crystallization polycrystalline silicon film (comprise longitudinally with horizontal crystallization direction) the preparation semiconductor device of Solid State Laser annealing.The metal inducement polysilicon membrane is that the amorphous silicon membrane of introducing metallic nickel forms through boiler tube annealing.For improving the quality of this kind polysilicon membrane, use Solid State Laser that above-mentioned polysilicon membrane is carried out annealing in process and be used for reducing the influence of membrane structure defective and metallic nickel element property of thin film, but in the annealing process, do not change the main body grainiess of metal inducement polysilicon.Dopant activation in the device adopts Solid State Laser equally.Compare with excimer laser, solid state laser is relatively cheap and simple to operate, and is suitable for suitability for industrialized production.
This kind polycrystalline silicon material has application fields, as transducer, and electronic device, flat-panel monitor and 3 D stereo circuit etc.
Background technology
Thin-film transistor (TFTs) has been widely used in preparing active-matrix liquid crystal display, active organic LED display, active electronic book and active imageing sensor.
Based on the TFTs of amorphous silicon because switching speed is slow and can not prepare P type device and make and be difficult to realize peripheral circuit.This makes people turn on the amorphous silicon polysilicon that heating obtains through smelting furnace or laser.
Conventional low-pressure chemical vapor deposition prepares polysilicon, processing temperature height (620-650 ℃), and quality of materials is low.Can improve the quality by high annealing (being higher than 1000 ℃), yet can only to be used for substrate be that expensive quartz substrate can not be used for more cheap glass substrate for this.
The technology of another kind of preparation polysilicon is metal-induced crystallization (United States Patent (USP) 5275851,5879977,2001018224 and 6737674).The material grains of making is big and have continuous grain boundary, and the uniformity of material and device and repeatability are better.Yet, just can obtain performance better material and device if can reduce the microdefect of material.
Also having a kind of technology is that amorphous silicon is carried out the excimer laser crystallization, can obtain the higher polysilicon of quality (United States Patent (USP) 535229,6071796 and 2004087116).Yet it exists uniformity and repeatable relatively poor shortcoming, and cost is also higher.
Method that metal-induced crystallization and quasi-molecule laser annealing are combined has been proposed in United States Patent (USP) (5705829,58937730,5869362 and 2003129853).Yet the excimer laser that is adopted is very expensive very complicated.
On amorphous silicon, adopt Nd:YAG laser to add heat-conducting layer and can obtain polysilicon (United States Patent (USP) 6537864).This laser is more cheap comparatively speaking, but this technical finesse temperature is higher, and the quality of making material is also good inadequately.
And the present invention is a technology of amorphous silicon metal-induced crystallization and solid state laser annealed combination being got up to prepare polysilicon membrane.Film quality height, uniformity and the favorable repeatability made.Can make semiconductor device on this film, maximum processing temperature is no more than 590 ℃.The cost of solid state laser is also very low.
Summary of the invention
The present invention is a technology of amorphous silicon metal-induced crystallization and solid state laser annealed combination being got up to prepare polysilicon membrane.Film quality height, uniformity and the favorable repeatability made.Can make semiconductor device on this film, maximum processing temperature is no more than 590 ℃.The cost of solid state laser is also very low.
First innovative point of the present invention is to adopt more cheap solid state laser to reduce the quantity of the material microdefect in the polysilicon that metal-induced crystallization forms.
Second innovative point of the present invention is the laser that adopts the higher frequency multiplication of solid state laser.For Nd:YAG laser, the frequency tripled laser of 335nm is easy to be absorbed by silicon, and two double-frequency lasers of 532nm are then preferentially absorbed by microdefect.The former can be used to reduce volume defect and the latter can be used to reduce local grain boundary defective.
This kind polycrystalline silicon material has application fields, as transducer, and electronic device, flat-panel monitor and 3 D stereo circuit etc.
A kind of method for preparing polysilicon membrane of the present invention is characterized in that comprising the following step:
1) forms one deck amorphous silicon membrane;
2) deposition skim nickel on described amorphous silicon membrane;
3) described amorphous silicon and nickel film are annealed under 420 ℃ of-620 ℃ of temperature together, the duration is 0.5-5 hour;
4) film of Sheng Chenging shines simultaneously through two frequencys multiplication and frequency tripling pulse laser, and the wavelength of pulse laser is between 0.9 micron to 1.2 microns.
Described amorphous silicon membrane is to adopt but be not limited to the low-pressure chemical vapor deposition process to form.
Described amorphous silicon membrane thickness is the 10-100 nanometer;
Described nickel film is the 0.1-0.01% of silicon amount in the amorphous silicon;
Described nickel film thickness is the 1-10 nanometer;
Described pulse laser can be a Nd:YAG laser;
Described pulse laser can be a Nd:Glass laser;
Described pulse laser can be an Alexandrite laser;
The described pulse laser duration is 5-30 nanosecond;
The substrate of described polysilicon film device can be glass, polymer, insulation stainless steel, polysilicon or the monocrystalline silicon that contains prefabricated custom integrated circuit.
Adopt the thin-film transistor of the polysilicon preparation that described method makes, it is characterized in that thin-film transistor is a top gate type, or bottom gate type, or have the double grid type of top grid and bottom gate simultaneously, or the double grid type of a direct current bottom gate type of top grid.
The polysilicon that adopts described method to make is characterized in that, described polysilicon is used for the preparation temperature transducer.
The polysilicon that adopts described method to make is characterized in that, described polysilicon can be used for preparing micro mechanical system.
The polysilicon that adopts described method to make is characterized in that, described polysilicon is used for preparing imageing sensor.
The polysilicon that adopts described method to make is characterized in that, described polysilicon is used for preparing infrared sensor.
The polysilicon that adopts described technology to make is characterized in that, described polysilicon is used for preparing the pixel capacitors in the display.
Described thin-film transistor is used for preparing the active base plate and the peripheral drive circuit of flat-panel monitor.
Described thin-film transistor is used for preparing the active base plate and the peripheral drive circuit of imageing sensor.
Described thin-film transistor is used for preparing digital circuit, analog circuit and memory cell.
Above-mentioned detailed description is relevant of the present invention specifying, and does not allly break away from the equivalence that spirit of the present invention does and implements or change, all belongs to context of the present invention.
Description of drawings
Fig. 1: be deposited on the schematic cross-section that the mask in district and non-selection district is selected in the thin and definition of amorphous silicon on the substrate that is covered with insulating barrier.
Fig. 2: at the schematic cross-section of amorphous silicon surfaces deposition micro-nickel.
Fig. 3: at the vertical and schematic cross-section of metal-induced crystallization in a lateral direction.
Fig. 4: the schematic cross-section on the active island that metal-induced crystallization and metal-induced lateral crystallization form on substrate.
Fig. 5: the schematic cross-section that the laser that adopts solid state laser frequency tripling or frequency tripling and two frequencys multiplication to mix shines metal inducing crystallization polycrystalline silicon.
Fig. 6: the schematic diagram of solid state laser " n " frequency multiplication and " m " double-frequency laser mixed exposure.
Fig. 7: form the gate electrode of thin-film transistor and the schematic cross-section that the source and drain areas ion injects.
Fig. 8: the schematic cross-section that adopts thermal annealing or Nd:YAG frequency tripled laser that thin-film transistor is mixed and activates.
Fig. 9: the schematic cross-section of the thin-film transistor that employing metal-induced crystallization and solid state laser annealing technology are made.
Embodiment
Details are as follows with reference to accompanying drawing in the present invention:
Use the metal inducing crystallization polycrystalline silicon methods of making semiconductor devices of solid state laser annealing to be described below, referring to Fig. 1-9.
Fig. 1: be deposited on the amorphous silicon membrane 103 on the substrate 101 that is covered with insulating barrier 102 and the schematic cross-section of mask layer 104.
Substrate can be a high temperature polymer, glass, stainless steel, polysilicon or contain a kind of in the monocrystalline silicon of prefabricated custom integrated circuit.
Transition zone can bear the processing that is higher than 650 ℃ processing temperature of long period, includes but are not limited to silica, silicon oxynitride, silicon nitride.
Under 150 ℃-600 ℃ low temperature, form the amorphous silicon membrane 103 of 10 nanometers to 3 micron thickness.The technology that adopts includes but are not limited to sputter, evaporation or low pressure and plasma-enhanced chemical vapor deposition PECVD.
After forming amorphous silicon membrane 103, form the mask layer 104 (including but are not limited to silica, silicon oxynitride, silicon nitride) of a 100-200 nanometer thickness again.This one deck can bear the processing that is higher than 650 ℃ processing temperature of long period.
Fig. 2: at the schematic cross-section of the nickel 201 of the exposed region of amorphous silicon membrane 103 deposition.The method of introducing nickel includes but not limited to electron beam evaporation, sputter, and chemical vapour deposition (CVD), ion injects or the substrate immersion is contained the solution of nickel ion.
Fig. 3: the schematic cross-section of the polysilicons that under 420 ℃ to 620 ℃, form in the conventional annealing stove of amorphous silicon under nitrogen atmosphere.301 zones that are positioned under the nickel dam are " vertically " crystallization, and 302 zones that covered by mask layer 104 are transverse crystallizations.
After crystallization is finished, remaining nickel and mask layer will be removed.Chemical wet etching technology by routine defines active island.
Fig. 4: respectively at the active island 401 of polysilicon of 301 and 302 zone formation and 402 schematic cross-section.
Fig. 5: the schematic diagram of insulating barrier 501 (including but are not limited to silica).See through 501 layers, adopt monotype or multimodal solid state laser that active island 401 or 402 is shone.
Fig. 6: the laser of two single-modes is irradiation alternately.Each pattern of irradiation time, wavelength, energy all carry out optimization.
Fig. 7: the schematic cross-section of on active island 401 and 402, realizing thin-film transistor.703 is gate electrode.Source-drain electrode on the active island 401 and 402 marks with 701 and 702 respectively.
Fig. 8: adopt the Solid State Laser radiation, with the source and drain areas hot activation.Perhaps adopt in conventional annealing note the method for annealing under 420 ℃ to the 620 ℃ temperature.
Fig. 9: the schematic cross-section of two thin-film transistors.Depositing insulating layer 901.Contact hole is opened to grid, source and drain electrode.Metal connecting line 902 depositions and typing.
The concrete preparation method that implements is:
1: on the healthy and free from worry 1737F glass 101 of 1.1 millimeters thick, PECVD deposits 200 nanometer low temperature silicon nitrides, and 100 nanometer cryogenic oxidation silicons (LTO) 102 adopt the method for LPCVD afterwards.Amorphous silicon 103 as deposition 50 nanometers on last substrate.
2: at the surface deposition 150 nanometer LTO layers 104 of amorphous silicon, photoetching forms selects district's (amorphous silicon exposed area) and non-selection district (LTO covered area).
3: above-mentioned sample, by the nisiloy hybrid target, the nickel of argon oxygen atmosphere sputtering sedimentation trace adheres to its surface.The nickel amount is the 0.1-0.01% of silicon amount in the amorphous silicon.
4: adhere to the samples of amorphous silicon of micro-nickel, under 590 ℃ of temperature, annealed 3 hours in the conventional annealing stove under nitrogen atmosphere, form metal inducement interval 301 and metal-induced lateral crystallization interval 302.
5: after crystallization is finished, remove remaining nickel and mask layer with the hydrofluoric acid (5%) of dilution.
6: between different crystallization regions, photoetching forms the active island of TFT.
The 7:LPCVD method deposits the LTO layer of 100 nanometers, covers on the active silicon island 401,402.
8: adopt YAG frequency tripling and two double-frequency lasers 502,503 (energy was than 10: 1) to shine sample surfaces simultaneously.30 nanoseconds of pulse duration, laser energy 120 milli Jiao/square the insides, sweep speed 0.5 cel.
9: prepare TFT with above-mentioned polysilicon, gate insulation layer is 100 nanometer thickness LTO layers, 501, the 280 nm polysilicon grid electrode 703 of LPCVD deposition, the source-drain electrode 701,702 that ion injects.
10: adopt 801 irradiations of TAG two frequencys multiplication (532 nanometer) laser, heat-activated doped polycrystalline silicon source, grid, drain electrode.
11.LPCVD deposit 500 nanometer LTO electrode dielectric layers 901, opening contact hole forms metal extraction electrode 902, after the alloying, promptly finishes preparation of devices.
Claims (18)
1. method for preparing polysilicon membrane is characterized in that comprising the following step:
1) forms one deck amorphous silicon membrane;
2) deposition skim nickel on described amorphous silicon membrane;
3) described amorphous silicon and nickel film are annealed under 420 ℃ of-620 ℃ of temperature together, the duration is 0.5-5 hour;
4) film of Sheng Chenging shines simultaneously through two frequencys multiplication and frequency tripling pulse laser, and the wavelength of pulse laser is between 0.9 micron to 1.2 microns.
2. the method described in the claim 1, described amorphous silicon membrane forms by the low-pressure chemical vapor deposition process.
3. the method described in the claim 1, described amorphous silicon membrane thickness is the 10-100 nanometer.
4. the method described in the claim 1, described nickel film thickness is the 1-10 nanometer.
5. the method described in the claim 1, described pulse laser is a Nd:YAG laser.
6. the method described in the claim 1, described pulse laser is a Nd:Glass laser.
7. the method described in the claim 1, described pulse laser is an Alexandrite laser.
8. the method described in the claim 1, the described pulse laser duration is 5-30 nanosecond.
9. the method described in the claim 1, the substrate of the device that described polysilicon membrane constitutes is glass, polymer, insulation stainless steel, polysilicon or the monocrystalline silicon that contains prefabricated custom integrated circuit.
10. the thin-film transistor that the polysilicon that adopts the method described in one of claim 1-8 to make prepares, it is characterized in that thin-film transistor is a top gate type, or bottom gate type, or have the double grid type of top grid and bottom gate simultaneously, or the double grid type of top grid and a direct current bottom gate.
11. the thin-film transistor according to described in the claim 10 is characterized in that, described thin-film transistor is used for preparing the active base plate and the peripheral drive circuit of flat-panel monitor.
12. the thin-film transistor according to described in the claim 10 is characterized in that, described thin-film transistor is used for preparing the active base plate and the peripheral drive circuit of imageing sensor.
13. the thin-film transistor according to described in the claim 10 is characterized in that, described thin-film transistor is used for preparing digital circuit, analog circuit and memory cell.
14. the polysilicon that adopts the method described in one of claim 1-8 to make is characterized in that, described polysilicon is used for the preparation temperature transducer.
15. the polysilicon that adopts the method described in one of claim 1-8 to make is characterized in that, described polysilicon can be used for preparing micro mechanical system.
16. the polysilicon that adopts the method described in one of claim 1-8 to make is characterized in that described polysilicon is used for preparing imageing sensor.
17. the polysilicon that adopts the method described in one of claim 1-8 to make is characterized in that described polysilicon is used for preparing infrared sensor.
18. the polysilicon that adopts the method described in one of claim 1-8 to make is characterized in that described polysilicon is used for preparing the pixel capacitors in the display.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/292257 | 2005-12-01 | ||
| US11/292,257 US7381600B2 (en) | 2004-12-02 | 2005-12-01 | Method of annealing polycrystalline silicon using solid-state laser and devices built thereon |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1975989A CN1975989A (en) | 2007-06-06 |
| CN1975989B true CN1975989B (en) | 2010-09-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101398774A Expired - Fee Related CN1975989B (en) | 2005-12-01 | 2006-09-20 | Polycrystalline silicon film preparation method, polycrystalline silicon and film transistor prepared therefor |
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| Country | Link |
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| CN (1) | CN1975989B (en) |
| HK (1) | HK1105483A1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854096A (en) * | 1994-06-02 | 1998-12-29 | Semiconductor Energy Laboratory Co., Ltd. | Process for fabricating semiconductor device |
| US6319761B1 (en) * | 1993-06-22 | 2001-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
| CN1407603A (en) * | 2001-08-25 | 2003-04-02 | 日立电线株式会社 | Crystal silicon film semiconductor device and its manufacture, and photoelectric device |
-
2006
- 2006-09-20 CN CN2006101398774A patent/CN1975989B/en not_active Expired - Fee Related
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2007
- 2007-09-28 HK HK07110570.0A patent/HK1105483A1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6319761B1 (en) * | 1993-06-22 | 2001-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
| US5854096A (en) * | 1994-06-02 | 1998-12-29 | Semiconductor Energy Laboratory Co., Ltd. | Process for fabricating semiconductor device |
| CN1407603A (en) * | 2001-08-25 | 2003-04-02 | 日立电线株式会社 | Crystal silicon film semiconductor device and its manufacture, and photoelectric device |
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| Publication number | Publication date |
|---|---|
| CN1975989A (en) | 2007-06-06 |
| HK1105483A1 (en) | 2008-02-15 |
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