DE10084500T1 - Frequenzvervielfachende Delay Locked Loop - Google Patents

Frequenzvervielfachende Delay Locked Loop

Info

Publication number
DE10084500T1
DE10084500T1 DE2000184500 DE10084500T DE10084500T1 DE 10084500 T1 DE10084500 T1 DE 10084500T1 DE 2000184500 DE2000184500 DE 2000184500 DE 10084500 T DE10084500 T DE 10084500T DE 10084500 T1 DE10084500 T1 DE 10084500T1
Authority
DE
Germany
Prior art keywords
locked loop
delay locked
frequency multiplying
multiplying delay
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE2000184500
Other languages
English (en)
Other versions
DE10084500B3 (de
Inventor
Paul Demone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of DE10084500T1 publication Critical patent/DE10084500T1/de
Application granted granted Critical
Publication of DE10084500B3 publication Critical patent/DE10084500B3/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/15046—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a tapped delay line
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
DE10084500.2T 1999-04-30 2000-05-01 Frequenzvervielfachende Delay Locked Loop Expired - Fee Related DE10084500B3 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA002270516A CA2270516C (en) 1999-04-30 1999-04-30 Frequency-doubling delay locked loop
CA2,270,516 1999-04-30
PCT/CA2000/000468 WO2000067381A1 (en) 1999-04-30 2000-05-01 Frequency-multiplying delay locked loop

Publications (2)

Publication Number Publication Date
DE10084500T1 true DE10084500T1 (de) 2002-06-27
DE10084500B3 DE10084500B3 (de) 2014-02-13

Family

ID=4163496

Family Applications (2)

Application Number Title Priority Date Filing Date
DE10084500.2T Expired - Fee Related DE10084500B3 (de) 1999-04-30 2000-05-01 Frequenzvervielfachende Delay Locked Loop
DE2000185617 Pending DE10085617A5 (de) 1999-04-30 2000-05-01 Frequenzvervielfachende Delay Locked Loop (DLL)

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE2000185617 Pending DE10085617A5 (de) 1999-04-30 2000-05-01 Frequenzvervielfachende Delay Locked Loop (DLL)

Country Status (9)

Country Link
US (7) US6441659B1 (de)
JP (3) JP2002543732A (de)
KR (1) KR100811766B1 (de)
CN (1) CN1190012C (de)
AU (1) AU4280300A (de)
CA (1) CA2270516C (de)
DE (2) DE10084500B3 (de)
GB (1) GB2363684B (de)
WO (1) WO2000067381A1 (de)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10249886A1 (de) * 2002-10-25 2004-05-13 Sp3D Chip Design Gmbh Verfahren und Vorrichtung zum Erzeugen eines Taktsignals mit vorbestimmten Taktsingaleigenschaften
DE10249886B4 (de) * 2002-10-25 2005-02-10 Sp3D Chip Design Gmbh Verfahren und Vorrichtung zum Erzeugen eines Taktsignals mit vorbestimmten Taktsingaleigenschaften

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DE10084500B3 (de) 2014-02-13
JP2002543732A (ja) 2002-12-17
CN1349683A (zh) 2002-05-15
JP2011019281A (ja) 2011-01-27
US7116141B2 (en) 2006-10-03
US8754687B2 (en) 2014-06-17
WO2000067381A1 (en) 2000-11-09
GB0125097D0 (en) 2001-12-12
US6441659B1 (en) 2002-08-27
KR20020018660A (ko) 2002-03-08
US8558593B2 (en) 2013-10-15
AU4280300A (en) 2000-11-17
US20130015898A1 (en) 2013-01-17
KR100811766B1 (ko) 2008-03-10
US20090039931A1 (en) 2009-02-12
US20100225370A1 (en) 2010-09-09
US7746136B2 (en) 2010-06-29
US8283959B2 (en) 2012-10-09
US20060261866A1 (en) 2006-11-23
JP4619446B2 (ja) 2011-01-26
CN1190012C (zh) 2005-02-16
GB2363684B (en) 2003-07-16
DE10085617A5 (de) 2014-04-03
US20140009196A1 (en) 2014-01-09
US7456666B2 (en) 2008-11-25
JP2010074859A (ja) 2010-04-02
US20030042947A1 (en) 2003-03-06
CA2270516C (en) 2009-11-17
CA2270516A1 (en) 2000-10-30

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