DE10123464B4 - Method, computer program and computer program product for testing layout structures of integrated electrical circuits - Google Patents

Abstract

Method for testing layout structures of integrated electrical circuits for implementation with a computer program on a computer system having at least one memory area,
wherein at least one layout file (26) present as a file or part of a file is loadable into the working memory area, wherein the layout structure (26) is subdivided into one or more layout levels (33, 34, 35), wherein within the layout structure (26) numerous structural elements (14, 17, 21, 27, 28, 29) are provided,
wherein at least one pattern (11, 25) stored in a database can be loaded into the working memory, which represents an allowed structural element (14, 17, 21, 27, 28, 29) of an integrated electrical circuit,
wherein layout structures (26) can be checked for matches and / or deviations by comparisons with patterns (11, 25), the method comprising the following steps:
1) selection of at least one layout level to be checked (33, 34, 35),
2) Selection of at least one pattern to be used for a check (11, 25), ...

Description

method Computer program and computer program product for testing Layout structures of integrated electrical circuits as well as data carriers with this computer program or computer program product.

The The invention relates to a method for checking layout structures of integrated electrical circuits, in which layout structures by comparison with defined patterns to match and / or on Deviations testable are.

in the State of the art for testing of layout structures of integrated electrical circuits especially layout verification programs known the basis of standard operations such as distance measurements or Boolean links from layout or mask layers derive new levels and create these levels with rigid rules, mostly check with identical values for all structures. The review of Layout structures are usually done by combining a variety from standard operations.

at the manufacture of integrated electrical circuits occur Deviations on both tolerances in the chemical manufacturing processes as well as by deviations in the projection of masks the lacquer layer of the semiconductor blank arise and due to interference due to the very small structural dimensions lying in the range of the light wavelength are conditional.

The The effects of interference on a particular structure are dependent on this always from the respective environment. To take account of interference effects None are sufficient in the design of integrated electrical circuits rigid spacing rules, instead structure distances and - Adhere to values that are dependent on the respective environment.

at the known method for testing Layout structures of integrated electrical circuits is of Disadvantage that complex Rules described by combinations of many individual operations become difficult to understand and are difficult to maintain. Furthermore, combinations are many Operations are much more ineffective than any corresponding one Special operation could be. Accordingly requires such an examination of Layout structures have a lot of runtime and a lot of space.

Furthermore has a disadvantageous effect that a exact replica of a to be tested Usually by the available Operations not always possible is. Moreover, it is never quite sure if the description of a rule all possibilities covered in the design data. This allows correct layout structures be reported as faulty or existing errors on the Layout structures are overlooked, which leads to defective circuits.

moreover are the known test methods only conditionally able, structure distances and structure widths with umgebungsbhängigen To check values.

The US 54 52 224 A shows a method for extracting capacitances from an integrated circuit layout. In this case, a so-called "timing verification" is performed with which the influence of the capacitances on the signal propagation times of the integrated circuit shown in the layout is checked. The layout is verified by surveying steps. For this purpose, the layout is cut into so-called "Manhattan-oriented rectangles" or at least triangles. Then, using the cut-out rectangles or triangles, the area from which a capacitor results is determined. From this the capacitance of the capacitor can be calculated.

In the US 57 40 071 A are described a so-called "Schematic Modifier Editor" and a so-called "Shape Modifier Editor", which work together so that changes in the layout data of an electrical circuit in the schematic representation or in the "Schematic" reflected. In this case, a file with an altered schematic representation and another file with a changed state or with a modified form are generated, which can be compared by means of conventional verification programs to ensure that the file with the changed state implements the desired circuit.

The US 54 50 331 A describes the checking of the minimum path lengths of layout polygons in integrated circuits, with the aid of the steps of "labeling" and sorting individual layout pieces. In this case, a line piece is broken down into individual polygons, which are provided with "labels" a, b, c, d, e and f and so on. These polygons are sorted by size using a fast method. In order to check whether the line section in question corresponds to layout specifications, the smallest polygons are then examined whether they have a certain minimum required width. If this is the case for the smallest polygons, then all sections of the relevant trace have the required minimum width.

The US 60 09 251 A discloses a method for the hierarchical verification of integrated circuits. Circuit parts that are used multiple times are indexed in a database and checked only once. The identification takes place by means of a "label". In the US 60 09 251 A For example, a layout structure is provided in a file that has numerous structural elements. These structural elements are checked for the presence of identical structural elements, which reduces the size of the file representing the layout structure by checking only one of matching structural elements.

In the DE 100 04 599 A1 An apparatus for designing semiconductor integrated circuits that performs transistor layout and wiring processes in the design phase of the semiconductor integrated circuit is described. This apparatus comprises a three-dimensional area setting section, a priority determining section, a total wiring capacity determining section, a wiring implementing section, and a wiring evaluator. One of the DE 100 04 599 A1 The pursued goal is to determine the completeness of wire connections.

The DE 100 40 392 A1 describes a pattern data density inspection apparatus and a pattern data density inspection method which are to improve the detection accuracy of the pattern data density error area and output the detection results to a developer so as to efficiently perform a correction operation without detecting pattern data density error areas. The pattern data density inspection apparatus has, for this purpose, a pattern data density calculating means, a temporary error area detecting means and an error area detecting means.

It The object of the invention is a method for testing layout structures of to provide integrated electrical circuits with the design rules be checked effectively and accurately in the design data.

These The object is solved by the subject matter of the independent claims. Advantageous embodiments emerge from the respective subclaims.

The The invention relates to a method for checking layout structures of integrated electrical circuits. This examination procedure is by means of a computer program performed on a computer system. The Computer system has this at least one memory area, at least one permanent storage area and at least one data processing unit on.

According to the invention allowed structure elements of layout structures of integrated predetermined electrical circuits in a pattern database. By means of the method according to the invention for exam of integrated electrical circuits are the ones to be studied Layout structures by matching these given patterns to matches and / or checked for deviations.

layout structures lie for this as a file or part of a file preferably as a GDSII file before and can loaded into the memory area. Every layout structure is divided into one or more layout levels. Within each one Layout level are many structural element areas as geometric Figures and position elements assigned to the individual structural element areas and orientation information provided. Structure elements result themselves out of a lot of structural element areas and can several layout levels.

One Pattern represents an allowed structural element of a layout structure of an integrated electrical Circuit and is divided into at least one pattern level. template can in the GDSII file format and stored in a database be. At least one pattern stored in a database is loadable into the main memory.

In a first step of the method according to the invention for testing Layout structures is a selection of at least one to be checked layout level a layout structure. This selection is automatic or by a user. Subsequently the selection of at least one pattern to be used for the check is made. This selection is done automatically or by a user. After that a review of the Structure element areas within the selected layout layer with the selected pattern. In this case, each structural element area is associated with the selected pattern (s) and those structural element areas that match and / or deviations are noted and output.

By means of the invention, environment-dependent structure spacings and / or structure widths including rules for the design and construction of structural elements can be described very simply, preferably in a single instruction. This results in a very good readability and maintainability of the database for the review of layout structures of integrated electrical circuits. The invention is suitable for the examination of layout structures having structure dimensions below the wavelength of light.

By the specification of patterns is clearly recognizable, which structural elements or structure element areas are allowed and which structural elements or structure element areas are not permitted. Thus is through the inventive method a particularly advantageous transparency and traceability the review of Given layout structures.

Certain Structural elements, such as a fuse structure, which have a well-defined shape have to have are by the method according to the invention particularly advantageous verifiable.

Furthermore The invention provides a high performance of the review. The inventive method runs very fast and memory efficient.

Farther guaranteed the invention a high flexibility, since the parameters for the examination of the layout structures be easily extended or changed.

In an embodiment The invention provides the permitted structural elements of layout structures predetermined by integrated electrical circuits in the form of patterns, where each pattern is associated with a base polygon and one or more Polygons divided.

each Pattern extends on one or more pattern planes. each Sample level contains either a base polygon or one or more associated polygons.

One Layout feature has one or more feature regions on different layout levels.

According to one embodiment In accordance with the invention, one or more patterns may be selected for review of the layout structures.

First becomes a selected one considered first layout level. All structural element areas of the selected first Layout level are determined and matched to the or the base polygons of the selected pattern (s). Those Structure element areas are noted, the agreement with or have the base polygons.

in the Case of a match of a base polygon, the associated polygons become a match check used.

For each Structure element area in which a match with a base polygon has been found, those structural element areas become on further layout levels determines which match for a check be used with the associated polygons of the pattern. These are all structural element areas on the associated polygons corresponding layout levels whose distance from the considered structure element area is less than the maximum extent of all selected patterns.

The thus determined structural element areas of the memorized structural elements the layout structure will be on matches with the associated polygons of the patterns on the respective layout levels checked.

In Deviation from the above-described review of the layout structure 26 "level by level" is also a "structural element" review conceivable.

To will be first each tree element area of a first selected layout layer with all adjacent structural element areas of all other relevant for the examination Layout levels combined to form a structure element. When adjacent thereto apply structure element areas whose distance is smaller is the maximum extent of all patterns.

After that is selected by a first layout level. For every structural element becomes the associated one Structure element area of the selected first layout level to match with the base polygon (s) of the selected pattern (s) checked. In case of a match will be afterwards all structural element areas of the considered structural element the other selected Layout levels to match checked with the associated polygon (s) on the corresponding pattern planes. The review will with the next structure element area continued.

Finally done the output of those structural elements that match both the base polygons as well as the associated polygons Have patterns on the respective layout levels, or it will be the mismatched Structural elements reported as faulty.

In this embodiment, it is advantageous that rules for the design and for the construction of structural elements, the environment-dependent Struk include turabstände and structure widths are described very simple and very transparent and a review of the layout structure is very beneficial.

Furthermore a very advantageous two-stage process of verification is ensured, which in a first Step through basic polygons of specific structural element areas such as For example, checking contacts for exact match and the in a second step, using associated polygons Checked environment of the considered structure element area.

Accordingly is achieved by this embodiment The invention provides a high flexibility of checking the layout structure.

According to one another embodiment The invention is a pattern in two or more basic polygons and articulated into one or more associated polygons.

All Structure element areas of the selected layout levels are determined and on agreement with the base polygon (s) of the selected pattern (s) checked. Structure element areas that match with the base polygons the selected one Have patterns are noted.

Then be Further structure element areas on further layout levels that correspond to the noted Structural element areas are assigned to match the other Basic polygons the selected one Sample checked. matches having structural element areas are noted.

After that become further structural element areas of the memorized structural elements on the respective layout levels on agreement with or the associated polygons of the selected pattern (s). If there is a match the output of these structure elements, or if they do not match these structure elements are reported as faulty.

By this idea of the invention can complex structural elements are deposited as a pattern. complicated Rules for the design and construction of structural elements, as well as structure distances and structure widths can very beneficial in the review of Layout structure included and very simple and very transparent to be discribed.

Furthermore becomes a very memory and speed efficient review of Guaranteed layout structures.

According to one another embodiment The invention is the comparison of each structural element area with the base polygon to be checked in that trying goes through the base polygon a transformation with the structural element area to cover bring. This transformation can be considered a shift, as a Rotation, as a reflection or as a combination of these transformations accomplished become. A reflection can be done by a coordinate axis is used as a mirror axis. A rotation can be at an angle of 45 degrees, of 90 degrees and multiples of these angles.

By this embodiment The invention achieves an advantageous implementation of the verification, which is independent of the orientation and the rotational position of the structural elements or the structural element areas is.

According to one another embodiment The invention is the verification of compliance each structural element area with an associated polygon thereby, by subjecting the associated polygon to the same transformation that was performed with the base polygon associated with that Polygon is assigned. This transformation can be considered a shift, as a rotation, as a reflection, or as a combination executed these transformations become.

at this review will determines whether the structural element area associated with the Polygon matches or between the structural element region and the associated one Polygon has a defined relationship, e.g. that the structural element area includes the associated polygon.

By this embodiment the invention is an advantageous comparison of the structural elements or the structure element regions with the associated polygon independent of the rotational position of the layout structure possible.

According to one another embodiment According to the invention, the layout structures become within the selected layout levels so tested that systematically one after the other all possible ones Cutouts are formed from the layout levels. About the complete Layout structure is moved to a "window", the Windows one after another all sorts Clippings from the layout structure detected. These cutouts will be with the patterns or with the base polygons to match checked.

By this embodiment The invention is a complete and very reliable review of integrated electrical circuit allows.

According to one another embodiment The invention is prior to the review of Layout structure a preselection of the structural elements to be tested or the one to be tested Structural areas made.

there are structural elements or structural element areas selectable, the similarities with the patterns or with the base polygons. Furthermore are Structure elements or structure element areas selectable, the by their function or by their nature for a match with the patterns for a check in Question come. Further criteria for the selection of the structural elements to be reviewed or structure element areas are conceivable.

Just these preselected structural elements or these preselected Structural element regions become with the patterns or with the basic polygons on agreement checked.

By this embodiment The invention can be a very individual and speed-optimal review of integrated electrical circuit can be achieved.

According to one another embodiment The invention relates to a method for checking and modifying structural elements the layout structure provided. Here are structural element areas a structural element having one or more base polygons of a chosen Pattern compared. In the case of a defined match of a structural element with the sample to be tested the structural element concerned is replaced by the pattern.

The The principle underlying the invention of pattern recognition can accordingly also be used for "layout post-processing".

By this embodiment The invention becomes a very user-friendly option the review and immediate change provided by examined layout structures.

The Invention is also in a computer program for the verification of Realizes layout structures. The computer program is like that trained that after Input of the layout structures to be checked and the pattern to be checked inventive method executable is, as a result of the method, the matching structural elements be issued or not consistent with a pattern structural elements be reported as an error.

The Invention also relates a disk with such a computer program and a method in which Such a computer program from an electronic data network such as from the Internet to a connected to the data network Computer is downloaded.

According to the invention for consideration of interference effects in the design of integrated electrical Circuits context-dependent design rules considered and checked. By the invention is contextual Design rules in the design data effectively and error-free verifiable.

Context-dependent design rules show a high complexity on. There are only a limited number of different layout data Situations to which the rules apply. By the Invention become allowed structures in a pattern database and the design rules by comparing the layout data checked with the allowed structures.

According to one Embodiment of the invention is any pattern as a GDSII structure or GDSII cell before. The base polygons and the associated polygons are each in separate GDSII levels described. The association between the layout levels and the levels in the file where the patterns are present is in a rules file Are defined. The pattern file has a grid that matches the layout grid is compatible. In the case of such compatibility points the quotient that can be formed from the layout grid and the pattern grid an integer value.

According to the invention for the same Structure element of a layout structure several patterns provided become. In this case, all patterns will match one after the other checked with the relevant structure element until a match was found or until all patterns were compared without success.

A high performance of the computer system is for the inventive review of conducive to integrated electrical circuits. By the following properties of the invention the performance of the computer system is increased.

The Pattern-based rules are constructed in such a way that they are independent of the hierarchical structure the layout data can be applied.

If several patterns for the review of a Layout structure are specified, these are custom Go through the sequence. So can by the user the patterns for the most likely structural elements are picked out to a rule with as possible to check a few comparisons.

symmetries for base polygons and associated polygons are considered. For a square base polygon, for example, a Contact describes, lead all possible transformations to an identical result. That's why in such a case only one comparison per structural element or per structural element area necessary.

Template, have the same basic polygons and are associated only by the ones Polygons are different, are checked together.

According to a further embodiment of the invention, a control file for checking integrated electrical circuits can be constructed as follows:
outLayer = ifxCheckEnvironment (inLayer, refLayer, patFile "patFile", patLay1, patLay2, patCell "patCell"["patCell" ...] [reverse])

in this connection is "outLayer" the output level, which is created by the rules file. All base polygons of the Input level "in-layer", which is not the rule fulfill, are copied to the output layer "outLayer". "inLayer" represents the input level to be checked which exists as a polygon layer. "refLayer" represents a second input level which exists as a polygon layer. "patFile" contains the name of the GDSII file, which contains all the patterns. "PatLay1" represents the pattern level representing the base polygons corresponding to the in-layer layer. "PatLay2" represents the pattern level representing the associated environment or associated polygons which corresponds to the level "refLayer". "patCell" describes the name a pattern cell in the pattern file. Any number of Cell name is specifiable. Patterns are given in the given Order checked. The Indicator "reverse" specifies that instead the base polygons that the rule checked do not fulfill, all entered structural elements or structural element regions, that satisfy the rule, copied to the output layer "outLayer".

According to one embodiment of the invention have all the sample cells contained under "patCell" exactly one base polygon at the pattern level "patLay1" and an associated polygon at the Pattern level "patLay1". complex Patterns that have different base polygons and different associated ones Polygons on different pattern levels and on different ones Reference pattern levels can be realized by the invention.

For each Structural element or for Each structure element area of the input layer "inLayer" searches the rule file for matches having specified pattern cells at the pattern level "patLay1" and checking that the associated polygon is enclosed at the pattern level "patLay1" by the input layer "refLayer", after being transformed to the correct position. Input polygons which do not correspond to any pattern and pattern environment copied to the output layer "outLayer".

By The invention will be any forms of basic polygons and associated Polygons supported.

The inventive review of Integrated electrical circuits can be extended to custom relationships between the associated environment of a base polygon and a reference plane verifiable to do.

Farther is in the inventive review of integrated electrical circuits, the rule to be checked by the user selectable, for example exact match, leg position, Exclusion.

The The invention is illustrated in more detail in the drawing with reference to embodiments.

1 shows a schematic geometric representation of the layout data of a first interconnect of an integrated circuit according to a first embodiment,

2 shows a schematic plan view of a second interconnect of an integrated electrical circuit according to the first embodiment,

3 shows a schematic geometric representation of a first pattern for testing layout structures of integrated electrical circuits,

4 shows a schematic geometric representation of a first structural element according to a second embodiment,

5 shows a schematic geometric representation of a comparison of a second structural element with the first pattern 3 according to a third embodiment,

6 shows a schematic geometric representation of a comparison of a third structural element with the first pattern 3 according to a fourth embodiment,

7 shows a schematic perspective view of a pattern and a schematic perspective plan view of a layout structure according to a fifth embodiment and according to a sixth embodiment.

1 shows a schematic geometric representation of the layout data of a first conductor connecting piece 1 an integrated electrical circuit of a first embodiment.

In the first embodiment according to 1 illustrates the problem that is solved by the invention. In 1 No solution of the problem underlying the invention is explained.

This in 1 shown first trace connector 1 is part of a layout structure of an integrated electrical circuit.

The first trace connector 1 divided into a first trace 2 , in a second track 3 , in a first contact piece 4 and in a second contact piece 5 ,

This in 1 illustrated first trace connector 1 with the first trace 2 , with the second trace 3 , with the first contact piece 4 and with the second contact piece 5 FIG. 12 illustrates a geometric map of layout data. This layout data serves as a basis for fabricating a corresponding trace connector of an integrated electrical circuit from a semiconductor wafer.

This in 1 illustrated first trace connector 1 has three superimposed levels, which are divided into a lower level, a middle level and an upper level.

In a cross section through the first interconnect connector 1 is the second trace 3 on the lower level, the first contact piece 4 and the second contact piece 5 are arranged on the middle level, and the first trace 2 is on the upper level.

The first trace 2 and the second trace 3 are provided for connection of circuit elements of the integrated electrical circuit by means of current flow.

About the first contact piece 4 and over the second contact piece 5 Current flows within the integrated electrical circuit from the first trace 2 on the second track 3 and from the second track 3 on the first track 2 transfer.

to Clarification of the effects of inaccuracies in the individual Manufacturing steps on the shape and function of integrated electrical Circuits are two in the embodiment different contact pieces intended. In practical application is the connection of two tracks often by means of exactly one contact piece intended.

The first trace 2 runs in a straight line horizontally and is provided as a narrow and flat conductor layer, which is in the region of the connection to the second conductor track 3 is designed widened as a rectangle.

The second track 3 runs in a straight line vertically and is designed as a narrow and flat conductor layer, which is in the area of the connection to the first conductor track 2 is designed widened as a rectangle.

The first contact piece 4 and the second contact piece 5 are called square flat layers for connecting the first trace 2 with the second trace 3 formed, wherein the edge length of the width of the first conductor track 2 or the second conductor track 3 equivalent.

The lateral boundaries of the first trace 2 , the second track 3 , the first contact piece 4 and the second contact piece 5 are in the layout of the layout data according to 1 intended as straight lines.

In the layout data of the first trace connector 1 according to 1 are the first contact piece 4 and the second contact piece 5 arranged so that they both from the first trace 2 as well as from the second track 3 be completely enclosed.

In the embodiment according to 1 is the first contact piece 4 centered with respect to the first trace 2 as well as with respect to the second conductor track 3 arranged and located at the optimal location for the connection of the first conductor 2 with the second trace 3 ,

The distance of the lower edge of the first contact piece 4 from the bottom of the first trace 2 and the distance of the upper edge of the first contact piece 4 from the top of the first trace 2 and the distance of the left edge of the first contact piece 4 from the left edge of the second trace 3 and the distance of the right edge of the first contact piece 4 from the right edge of the second conductor track 3 are trained as big enough.

In the embodiment according to 1 is this second contact piece 5 in the lower right area of the connection of the first trace 2 with the second trace 3 arranged. The location of the second contact piece 5 deviates from the optimal position.

The distance of the lower edge of the second contact piece 5 from the bottom of the first trace 2 and the distance of the right edge of the second contact piece 5 from the right edge of the second trace 3 are designed as very low. The distance of the upper edge of the second contact piece 5 from the top of the first trace 2 and the distance of the left edge of the second contact piece 5 from the left edge of the second trace 3 are trained as big enough.

2 shows a schematic plan view of a second conductor connecting piece 6 an integrated electrical circuit of a first embodiment.

In the first embodiment according to 2 illustrates the problem that is solved by the invention. In 2 No solution of the problem underlying the invention is explained.

The second trace connector 6 is using the geometric layout data of the first trace connector 1 out 1 made on a semiconductor wafer. The second trace connector 6 In terms of structure and structure, this corresponds to the first trace connector 1 out 1 ,

The second trace connector 6 is divided into a third track 7 , in a fourth track 8th , in a third contact piece 9 and in a fourth contact piece 10 ,

The third track 7 , the fourth track 8th , the third contact piece 9 and the fourth contact piece 10 have conductive material, in particular a metal or a metal alloy, and they correspond in structure each of the first conductor track 2 , the second track 3 , the first contact piece 4 and the second contact piece 5 ,

The third track 7 and the fourth track 8th are provided for receiving and conducting a current flow for connection of circuit elements of the integrated electrical circuit.

About the third contact piece 9 and over the fourth contact piece 10 Current flows within the integrated electrical circuit from the third trace 7 on the fourth track 8th and from the fourth track 8th on the third track 7 transfer.

The third track 7 is rectilinear horizontally and is formed as a narrow and flat conductor layer, which in the region of the connection to the fourth interconnect 8th is designed widened as a rectangle.

The fourth trace 8th runs in a straight line vertically and is formed as a narrow and flat conductor layer, which is in the area of the connection to the third conductor track 8th is formed greatly widened.

The third contact piece 9 and the fourth contact piece 10 are formed as flat layers. They connect the third track 7 with the fourth trace 8th ,

The lateral boundaries of the third trace 7 , the fourth track 8th , the third contact piece 9 and the fourth contact piece 10 have production-related curvatures.

In the embodiment according to 2 is the third contact piece 9 arranged such that the distance of the lower edge from the lower edge of the third conductor track 7 and the distance of the upper edge from the upper edge of the third trace 7 and the distance of the left edge from the left edge of the fourth conductor track 8th and the distance of the right edge from the right edge of the fourth trace 8th is designed as large enough.

In the embodiment according to 2 is the fourth contact piece 10 arranged so that it passes over the lower edge of the third track 7 and over the right edge of the fourth trace 8th herauslappt. The distance of the upper edge of the fourth contact piece 10 from the top of the third track 7 and the distance of the left edge of the fourth contact piece 10 from the left edge of the fourth trace 8th are trained as big enough.

Accordingly, the contact surface between the third conductor track 7 and the fourth contact piece 10 and the contact surface between the fourth contact piece 10 and the fourth trace 8th smaller than through the geometric layout data in 1 certainly.

following is based on the first embodiment illustrates the problem that is solved by the invention.

For the production of integrated electrical circuits, geometric layout data are generated and converted into corresponding masks. Subsequently, semiconductor wafers are exposed with the masks thus created. Finally, the exposed parts of the photoresist are removed on the semiconductor wafer and by means of chemical processes ge Wanted to produce structures in the semiconductor.

In the first embodiment, the geometrical layout data of the first trace connector is 1 according to 1 specified.

Based on these layout data, an in 2 shown second trace connector 6 an integrated electrical circuit fabricated on a semiconductor wafer.

From the layout data of the first trace 2 becomes the third track 7 produced. From the layout data of the second trace 3 becomes the fourth trace 8th manufactured. From the layout data of the first contact piece 4 becomes the third contact piece 9 produced. From the layout data of the second contact piece 5 becomes the fourth contact piece 10 manufactured.

By Inaccuracies in the chemical manufacturing processes and by Interference phenomena due to the very low lying in the range of the light wavelength Structural dimensions cause deviations of the manufactured structures from the geometric layout data. Accordingly, the correspond on the Semiconductor wafer resulting structures never exactly the originally designed Geometry.

The deviations from the inaccuracies in the individual production steps from those in 1 Layout data shown are in 2 recognizable.

The forms of the third trace 7 , the fourth track 8th , the third contact piece 9 and the fourth contact piece 10 deviate from the shapes of the first trace predetermined by the layout data 2 , the second track 3 , the first contact piece 4 and the second contact piece 5 from.

Particularly evident is the deviation of the fabricated structure from the geometric layout data in the fourth contact piece 10 , This fourth contact piece 10 is arranged so that it over the lower edge of the third conductor track 7 and over the right edge of the fourth trace 8th overlaps. Thus, the contact surface between the third conductor track 7 and the fourth contact piece 10 and the contact surface between the fourth contact piece 10 and the fourth trace 8th smaller than determined by the geometric layout data.

The missing fit of the fourth contact piece 10 causes a change in the electrical resistance of the contact piece 10 , The second trace connector 6 thus has an error and thus causes uselessness of the entire electrical circuit.

By such deviations from components of the manufactured integrated electrical circuit from the underlying layout data can the entire integrated electrical circuit error during operation and unusable in the worst case.

The first embodiment is hereby completed.

3 shows a schematic geometric representation of a first pattern 11 for testing layout structures of integrated electrical circuits.

According to the invention are patterns for reviewing Layout structures of integrated electrical circuits are provided.

template are described as program code in a database. she are described in the same format as the layout structures of integrated ones electrical circuits, for example in GDSII file format. Each pattern is common described in a separate cell and selectable via the cell name.

at the inventive review of Layout structures of integrated electrical circuits will be Check layout structures based on comparisons with stored patterns.

each Layout structure of an integrated electrical circuit has several Layout levels on. There are several structure element areas at each layout level arranged. Several structure element areas can be combined to form structural elements. Structure elements can Consequently, they extend to several layout levels.

each Pattern is divided into one or more base polygons on one or more pattern planes and other associated polygons one or more pattern levels. Patterns can be considered complex data types be defined.

This in 3 shown first patterns 11 is divided into a first basic polygon 12 and in a first associated polygon 13 , The first pattern 11 includes two sample levels. The first basic polygon 12 is on an upper pattern level. The first associated polygon 13 lies on a lower pattern level, which is arranged as a neighboring plane with respect to the upper pattern plane.

The first basic polygon 12 represents a desired contact surface. The first basic polygon 12 is to be brought to coincide with contacts of the respective structural element regions to be tested of the layout structure of the respective electrical circuit. The first associated polygon 13 represents a minimum environment of the trace, which must be maintained on the integrated electrical circuit around the contact surface.

The first associated polygon 13 is formed as a horizontally oriented rectangle whose width is approximately twice its height. Depending on the middle of the right and left sides of the first associated polygon 13 each outwardly directed and rectangular shaped bulges are arranged, which has a height of one third of the total height of the first associated polygon 13 and a width of one third of the total width of the associated polygon 13 exhibit.

The first basic polygon 12 in plan view of the first associated polygon 13 vertically and horizontally centered within the first associated polygon 13 arranged. The first basic polygon 12 has a height of one third of the total height of the first associated polygon 13 and a width of one third of the total width of the first associated polygon 13 on.

4 shows a schematic geometric representation of a first structural element 14 a second embodiment.

This exemplary first structural element 14 is part of a layout structure of an integrated electrical circuit. The first structural element 14 is available as part of layout data of an integrated electrical circuit, for example in GDSII file format.

The first structural element 14 is divided into a first contact area 15 and in a first contact surface environment 16 , The first structural element 14 includes two layout levels of the entire layout structure of the integrated electric circuit. The first contact surface 15 is arranged on an upper layout level. The first contact surface environment 16 is on a lower layout layer that is adjacent to the upper layout layer.

The first contact surface environment 16 corresponds in shape and size exactly to the first associated polygon 13 ,

The first contact surface 15 is square in shape and has an edge length that is one third of the height of the first associated polygon 13 equivalent. Regarding the first contact surface environment 16 is the first contact surface 15 Vertically centered in plan view and arranged horizontally starting from the center about half its base area shifted to the right.

The first contact surface 15 does not match shape and size with the first base polygon 12 match.

The first contact surface environment 16 of the first structural element 14 corresponds in shape and size exactly to the first associated polygon 13 ,

According to the invention are layout structures of an integrated electrical circuit Can be checked by means of patterns.

On the basis of several embodiments of the invention is subsequently using the first pattern 11 for an integrated electrical circuit examines whether a contact of a structural element of a layout structure of an integrated electrical circuit with that through the first base polygon 12 of the first pattern 11 given contact and whether this contact sufficiently from a means of the first associated polygon 13 certain minimum environment of a trace is enclosed.

For the implementation of inventive review of Layout structures are defined rules.

The Rules include those to be tested Layout levels, additional if necessary Reference layout levels, a list of valid patterns, and an association from layout levels to pattern levels.

Those layout levels of the layout structure of the integrated electric circuit, on which structural element areas with basic polygons 12 of patterns are determinable.

The Reference layout levels represent those layout levels whose Structure elements on matches be checked with the associated polygons. Which reference layout levels are checked and with which pattern levels these are to be compared, is specified in the rule description.

In the practical implementation the review of Layout structures with patterns each become a layout layer of a layout structure considered an integrated electrical circuit. Be first all structural element areas of the considered layout level determined.

One after the other, all structural element areas of this layout plane are checked for conformity by comparison with the base polygons of the patterns. In this case, it is checked whether the basic polygons by a transformation such as by a shift and / or by a rotation and / or by a reflection with to bring to be examined structural element area to coincide.

in the Trap of agreement the corresponding reference layout levels are considered and the Structure element areas determined on the reference layout levels, that are associated with the structural element regions of the layout layer, the matches having the base polygons. Subsequently, the associated polygons for one Comparison with these structural element areas used, wherein the associated polygons undergo the same transformations Be that with the associated Basic polygons performed were.

accordance Patterned feature areas are noted.

Subsequently, will this verification process for the repeated layout levels.

For checking for compliance is a function "match" definable, the if the comparison is successful, the respective structural element area remembers and after processing all Strukturelementbereiche with match the patterns Outputs structure elements as the result, or the non-matching ones Structural elements reports as errors.

The execution Review by a gradual processing of the entire layout level by comparisons a variety of cutouts from the layout level is conceivable. All structure element areas of the layout structure are considered here.

Farther a preselection of structural elements can be made. So may be similar for a match eligible structural elements or structural element areas the layout level for preselected a check and only these structural elements or structural element regions are checked. For example, you can in a review of contact pieces only the structural element areas "contact pieces" are examined.

In the following exemplary embodiments of the invention, two layout levels of a layout structure of an integrated electrical circuit are considered in each case. At the top layout level, all are using the first base polygon 12 searched for matching contact surfaces. At the adjacent lower layout level, thereafter, the corresponding minimum environments of traces are matched to the associated polygon 13 checked.

The only valid pattern is the first pattern 11 established.

The first structural element becomes the only structural element of the layout level of the layout structure investigated in the second exemplary embodiment 14 examined.

In this first structural element 14 is using the first pattern 11 out 3 examines whether the first contact surface 15 with the first base polygon 12 matches.

The first contact surface 15 is neither through a permissible transformation such as by a shift, by a rotation or by a reflection, nor by a combination of these transformations with the first base polygon 12 to bring to cover. The first contact surface 15 is smaller than the first base polygon 12 and also has a different shape. Accordingly, the comparison of the first contact surface 15 with the first base polygon 12 no agreement.

in the Case of congruence of a base polygon with a structure the integrated electrical circuit are in a second Step the associated polygons associated with the base polygon considered.

Since here no congruence of the first contact surface 15 with the first base polygon 12 was found, the check for the first structure element ends 14 at this point.

Accordingly, the first structural element 14 according to the second embodiment 4 no match with the first pattern 11 out 3 on and is reported as faulty.

The second embodiment is hereby completed.

5 shows a schematic geometric representation of a comparison of a second structural element 17 with the first pattern 11 out 3 a third embodiment.

The exemplary second structural element 17 is part of a layout structure of an integrated electrical circuit. It is in the form of layout data, for example in GDSII file format.

The second structural element 17 is divided into a second contact surface 18 and in a second contact surface environment 19 , The second structural element 17 includes two layout levels of the entire layout structure of the integrated electric circuit. The second contact surface 18 is on an upper one Layout level arranged. The second contact surface environment 19 is on a lower layout layer that is adjacent to the upper layout layer.

The second contact surface 18 corresponds in shape and size to the first base polygon rotated by 90 degrees 12 ,

The second contact surface environment 19 is formed as a vertically oriented rectangle whose height is approximately twice its width. At the center of the lower side of the second contact surface environment 19 is arranged a downward and rectangular shaped bulge, the contact surface surrounding a height of one third of the total height of the second Kon 19 and a width of one third of the total width of the second contact surface environment 19 having.

A first differential area 20 is on the middle of the upper side of the second contact surface environment 19 arranged centrally and formed as an upwardly directed and rectangular shaped bulge, which forms one of the second contact surface 18 corresponding height and a width of one third of the total width of the second contact surface environment 19 having.

The first difference surface 20 represents the area difference between the second contact surface environment 19 and the first associated polygon 13 , The first associated polygon 13 has a larger area than the second pad area environment 19 ,

In the third embodiment according to 5 for the inventive review of layout structures of integrated electrical circuits is hereinafter the second structural element 17 with the first pattern 11 out 3 compared.

Here, first, the second contact surface 18 with the first base polygon 12 compared.

The second contact surface 18 is rotated by 90 degrees with the first base polygon 12 brought to cover. Accordingly, the comparison between the second contact surface 18 and the first base polygon 12 an exact match.

in the Trap of agreement the investigated contact surface the base polygon then becomes the base polygon associated polygons subjected to the same transformation, the at the corresponding base polygons carried out have been. Subsequently becomes the structure under investigation of the integrated electric Circuit of a defined test with the associated Pattern subjected to one or more base polygons and associated polygons having.

In the third embodiment according to 5 a comparison of the second contact surface environment is made 19 with the first associated polygon 13 , The second contact surface environment 19 is subjected to the same transformation as that at the second contact surface 18 was applied.

By superimposing the thus transformed second contact surface environment 19 and the first associated polygon 13 results in a 5 dashed shown first differential area 20 ,

This difference surface 20 states that the polygon associated by the first 13 illustrated minimum environment of the second contact surface environment 19 is not fulfilled. As a result, the comparison of the second contact surface environment 19 with the first associated polygon 13 of the first pattern 11 out 3 no agreement.

The second structural element 17 of the third embodiment 5 does not match the first pattern 11 out 3 on and is thus reported as an error.

The third embodiment is hereby completed.

6 shows a schematic geometric representation of a comparison of a third structural element 21 with the first pattern 11 out 3 a fourth embodiment.

The exemplary third structural element 21 is part of a layout structure of an integrated electrical circuit. It is in the form of layout data, for example in GDSII file format.

The third structural element 21 is divided into a third contact area 22 and in a third contact surface environment 23 , The third structural element 21 includes two layout levels of the entire layout structure of the integrated electric circuit. The third contact surface 22 is arranged on an upper layout level. The third contact surface environment 23 is on a lower layout layer that is adjacent to the upper layout layer.

The third contact surface 22 corresponds in shape and size to the first base polygon 12 ,

The third contact surface environment 23 is formed as a horizontally oriented rectangle whose width of the width of the widened around the right bulge base of the first associated Polygons 13 equivalent. In the middle of the left side of the third contact surface environment 23 an outwardly directed and rectangular shaped bulge is arranged which is one third of the total height of the first associated polygon 13 and a width equal to the width of the first base polygon 12 equivalent.

A second difference surface 24 has two separate rectangular surface sections of the same shape and the same surface area.

The first surface portion of the second differential surface 24 is in the upper right area of the third contact surface environment 23 has a height of one third of the total height of the third contact surface environment 23 and one of the bulge on the left side of the third contact surface environment 23 corresponding width.

The second surface portion of the second differential surface 24 is in the lower right area of the third contact surface environment 23 has a height of one third of the total height of the third contact surface environment 23 and one of the bulge on the left side of the third contact surface environment 23 corresponding width.

In the fourth embodiment according to 6 for the inventive review of layout structures of integrated electrical circuits is hereinafter the third structural element 21 with the first pattern 11 out 3 compared.

Here, first, the third contact surface 22 with the first base polygon 12 of the first pattern 11 out 3 compared by trying the third contact surface 22 and the first base polygon 12 to coincide with each other.

In the fourth embodiment according to 6 gives this comparison between the third contact surface 22 and the first base polygon 12 an exact match.

Accordingly, this is followed by a comparison of the third contact surface environment 23 with the first associated polygon 13 of the first pattern 11 out 3 , By overlaying the third contact surface environment 23 and the first associated polygon 13 results in a 6 dashed shown second differential area 24 , This second differential area 24 illustrates that the third contact surface environment 23 is greater than the first associated polygon 13 of the first pattern 11 out 3 , The first associated polygon 13 is completely in the third contact surface environment 23 contain.

Accordingly, the third structural element 21 of the fourth embodiment 6 a match with the first pattern 11 out 3 on and is not reported as an error.

The fourth embodiment is hereby completed.

7 shows a second pattern 25 and a first layout structure 26 with a fourth structural element 27 , with a fifth structural element 28 and with a sixth structural element 29 according to a fifth and a sixth embodiment.

The second pattern 25 has a top pattern plane, a middle pattern plane, and a bottom pattern plane. In the upper pattern layer is a second base polygon 30 arranged in the middle pattern level is a third base polygon 31 and in the bottom pattern layer is a second associated polygon 32 arranged.

The second basic polygon 30 has a rectangular shape, the third base polygon 31 has an isosceles triangular shape and the second associated polygon 32 has a right triangular shape.

Accordingly, the second pattern includes 25 a second basic polygon 30 , a third base polygon 31 and a second associated polygon 32 ,

The layout structure 26 the integrated electrical circuit has an upper layout plane 33 , a middle layout level 34 and a lower layout level 35 on.

On the layout structure 26 are the fourth structural element 27 , the fifth structural element 28 and the sixth structural element 29 arranged.

The fourth structural element 27 , the fifth structural element 28 and the sixth structural element 29 extend to all three layout levels.

The fourth structural element 27 is divided into a first structure element area 36 into a second structural element area 37 and in a third structural element area 38 ,

The first structure element area 36 has a rectangular shape and is at the top layout level 33 arranged. The second structure element area 37 has an isosceles triangular shape and is on the middle layout level 34 , The third structural element area 38 has a right triangular shape and is at the bottom layout level 35 arranged.

The fifth structural element 28 is divided into a fourth structural element area 39 into a fifth structural element area 40 and in a sixth structural element area 41 ,

The fourth structural element area 39 has a rectangular shape and is at the top layout level 33 arranged. The fifth structural element area 40 has a right angle triangular shape and is on the middle layout level 34 , The sixth structural element area 41 has an isosceles triangular shape and is at the bottom layout level 35 arranged.

The sixth structural element 29 is divided into a seventh structural element area 42 , in an eighth structural element area 43 and in a ninth structural element area 44 ,

The seventh structural element area 42 has a rectangular shape and is at the top layout level 33 arranged. The eighth structural element area 43 has an isosceles triangular shape and is on the middle layout level 34 , The ninth structural element area 44 has an isosceles triangular shape and is at the bottom layout level 35 arranged.

In the fifth embodiment according to 7 for the inventive review of layout structures of integrated electrical circuits become the fourth structural element 27 , the fifth structural element 28 and the sixth structural element 29 to match the second pattern 25 checked.

In a first step, the complete data of the geometric figures of the first layout structure will be used 26 Structure element areas determined.

In the upper layout level 33 the first layout structure 26 become the first structural element area 36 , the fourth structural element area 39 and the seventh structural element region 42 found.

In the middle layout level 34 result in the second structural element area 37 , the fifth structural element area 40 and the eighth structural element area 43 ,

In the lower layout level 35 become the third structural element area 38 , the sixth structural element area 41 and the ninth structural element area 44 calculated.

Next to it are in the upper layout level 33 , in the middle layout level 34 and in the lower layout level 35 contain further, not shown here structural element areas.

Subsequently, for each determined structure element area in the upper layout level 33 the adjacent feature areas in the middle layout layer 34 and in the lower layout level 35 determined. Associated structural element areas are combined to form structural elements.

The first structure element area 36 , the second structural element area 37 and the third structural element area 38 become the fourth structural element 27 summarized.

The fourth structural element area 39 , the fifth structural element area 40 and the sixth structural element area 41 form the fifth structural element 28 ,

The seventh structural element area 42 , the eighth structural element area 43 and the ninth structural element area 44 become the sixth structural element 29 combined.

In a second step, the upper layout level becomes 33 and matches to the second base polygon 30 of the second pattern 25 checked.

The first structure element area 36 of the fourth structural element 27 , the fourth structural element area 39 of the fifth structural element 28 and the seventh structural element region 42 of the sixth structural element 29 have matches to the second base polygon 30 on. These structural element areas are consequently noted. In addition there are further structural element regions (not shown here) which are not noticed, in which no matches occur in this step.

In a third step, for the structural elements of the memorized structural element regions, the check is made for conformity with the third basic polygon 31 on the middle layout level 34 continued. In the second pattern 25 is the third basic polygon 31 arranged on the middle pattern level, ie on the pattern level below the upper pattern level, on which the second base polygon 30 is located. That is why the check becomes the middle layout level 34 that are below the upper layout level 33 is considered next considered. The middle layout level 34 will match the third base polygon 31 checked, starting from the structural elements noted in the previous step.

For the fourth structural element 27 will be on the middle layout level 34 the second structural element area 37 found. This second structural element area 37 has agreement with the third ten basic polygon 31 of the second pattern 25 on.

For the fifth structural element 28 will be on the middle layout level 34 the fifth structural element area 4Q found. This fifth structural element area 40 does not match the third base polygon 31 of the second pattern 25 match.

For the sixth structural element 29 will be on the middle layout level 34 the eighth structural element area 43 found. This eighth structural element area 37 has agreement with the third base polygon 31 of the second pattern 25 on.

Accordingly, the fourth structural element 27 and the sixth structural element 29 noted that on the upper layout level 33 with the second base polygon 30 and at the middle layout level 34 with the third base polygon 31 Match. The fifth structural element 28 is not noticed.

In a fourth step, the checking of the structural elements of the memorized structural element regions is checked for agreement with the second associated polygon 32 on the lower layout level 35 continued.

In the second pattern 25 is the second associated polygon 32 arranged on the lower pattern plane, that is, on the pattern plane below the middle pattern plane on which the third base polygon 31 located. Therefore, the lower layout level becomes 35 that are below the middle layout level 34 is arranged, used for further verification and matches with the second associated polygon 32 checked, starting from the structural elements noted in the previous step.

For the fourth structural element 27 will be on the lower layout level 35 the third structural element area 38 found. This third structural element area 38 has agreement with the second associated polygon 32 of the second pattern 25 on.

For the sixth structural element 29 will be on the lower layout level 35 the ninth structural element area 44 found. This ninth structural element area 44 does not match the second associated polygon 32 of the second pattern 25 and is not included in this.

Accordingly, no further structural elements are found that match the second pattern 25 exhibit.

The fourth structural element 27 has as the only structural element of the first layout structure 26 the integrated electrical circuit in accordance with the second pattern 25 on.

Accordingly, the fourth structural element becomes 27 as a result of the check issued, or that do not match de fifth structural element 28 and the mismatching sixth feature 29 noted as a mistake.

Notwithstanding the review of the first layout structure described above 26 " Level by level "is also a" structural element "review conceivable.

Of the First step of the "structurally elementary" verification, which is the determination of the Structural element areas and the determination of the structural elements from the associated Structural element areas is identical to the first Step of checking "level by level".

After that a structural element area of the selected first layout level is matched with the base polygon (s) the one chosen Sample checked. In case of a match will be afterwards the structure element areas on the other selected layout levels determines the tree element area of the selected first Correspond to the layout level.

These Structural element areas are aligned with others Basic polygons and with the associated polygons on the corresponding ones Sample levels tested. The review will with the review of next Structure element area of the first layout level continued.

In the exemplary embodiment, from the selected upper layout level 33 went out. The first structure element area 36 becomes with the second base polygon 30 compared, where there is agreement. Subsequently, the second structural element area 37 on the middle layout level 34 with the third base polygon 31 checked for conformity. This also results in a match. As a result, the third feature area becomes 38 on the lower layout level 35 for comparison with the second associated polygon 32 used. This comparison also gives a match. Thus, the fourth structural element becomes 27 as a result.

This "structural element-by-element" check is performed with the fifth structural element 28 and then with the sixth structural element 29 continued.

The check according to the fifth embodiment is finished.

in the The following is the use of a sixth embodiment the invention for modification of structural elements or for "postprocessing" set forth.

In "postprocessing" structural elements, the defined matches with a fixed pattern, by a particular pattern replaced.

In the sixth embodiment, all the structure elements of the first layout structure 26 that are on the upper layout level 33 Matches with the second base polygon 30 and at the middle layout level 34 Matches with the third base polygon 31 but at the lower layout level 35 from the second associated polygon 32 deviate, through the second pattern 25 replaced.

Of the first step of the "post Processing "includes the determination the structural element areas and the determination of the structural elements from each belonging together Structural element areas according to the im fifth embodiment explained procedure.

In the exemplary embodiment, from the selected upper layout level 33 went out. The first structure element area 36 , the fourth structural element area 39 and the seventh structural element region 42 will match the second base polygon 30 checked. All three structure element areas match.

Subsequently, the structure element areas become the middle layout level 34 that are associated with the structural element areas having the match found in the previous step, with the third basic polygon 31 compared. This results in matches in the second structural element area 37 and at the eighth structural element area 43 , The fifth structural element area 40 does not match the third base polygon 31 on.

Consequently, both have the fourth structural element 27 as well as the sixth structural element 29 Matches with the second base polygon 30 as well as the third basic polygon 31 on.

Thereafter, the structure element areas become the lower layout level 35 that are associated with the structural element regions having the match found in the previous step, with the second associated polygon 32 compared.

The third structural element area 38 agrees with the second associated polygon 32 match, the ninth structural element area 44 deviates from the shape of the second associated polygon 32 from.

Consequently, the fourth structural element 27 with the second pattern 25 identical.

The sixth structural element 29 matches the second pattern 25 with respect to the second basic polygon 32 and regarding the third base polygon 31 but gives way to the lower layout level 35 from the shape of the second associated polygon 32 from.

Accordingly, the sixth structural element becomes 29 in the first layout structure 26 through the second pattern 25 replaced.

In deviation from the above described implementation of the "postprocessing" of the first layout structure 26 According to a "level-by-level" approach, a "structurally elementary" implementation is also conceivable.

The sixth embodiment is finished at this point.

1

first Interconnect connector

2

first conductor path

3

second conductor path

4

first contact piece

5

second contact piece

6

second Interconnect connector

7

third conductor path

8th

fourth conductor path

9

third contact piece

10

fourth contact piece

11

first template

12

first Basic polygon

13

first associated polygon

14

first structural element

15

first contact area

16

first Contact surface area

17

second structural element

18

second contact area

19

second Contact surface area

20

first differential area

21

third structural element

22

third contact area

23

third Contact surface area

24

second differential area

25

second template

26

first layout structure

27

fourth structural element

28

fifth structural element

29

sixth structural element

30

second Basic polygon

31

third Basic polygon

32

second associated polygon

33

upper layout level

34

middle layout level

35

lower layout level

36

first Structural element area

37

second Structural element area

38

third Structural element area

39

fourth Structural element area

40

fifth structure element area

41

sixth Structural element area

42

seventh Structural element area

43

eight Structural element area

44

ninth Structural element area

Claims (11)

Method for testing layout structures of integrated electrical circuits for carrying out with a computer program on a computer system having at least one working memory area, wherein at least one layout structure (file or part of a file) is provided 26 ) is loadable into the memory area, the layout structure ( 26 ) into one or more layout levels ( 33 . 34 . 35 ), whereby within the layout structure ( 26 ) numerous structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ), wherein at least one pattern stored in a database ( 11 . 25 ) is loadable into the main memory, which is a permitted structural element ( 14 . 17 . 21 . 27 . 28 . 29 ) of an integrated electrical circuit, wherein layout structures ( 26 ) by comparisons with patterns ( 11 . 25 ) can be checked for matches and / or deviations, the method comprising the following steps: 1) selecting at least one layout level to be checked ( 33 . 34 . 35 2) Selection of at least one pattern to be used for a check ( 11 . 25 ), 3) checking the layout structures ( 26 ) within the selected layout level ( 33 . 34 . 35 ) with the selected pattern (s) ( 11 . 25 ), the structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) of the layout structure ( 26 ), each structural element ( 14 . 17 . 21 . 27 . 28 . 29 ) with the selected pattern (s) ( 11 . 25 ) and wherein those structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) that have matches and / or deviations, are noted and output. Method according to claim 1, characterized in that each pattern ( 11 . 25 ) into a basic polygon ( 12 . 30 . 31 ) and one or more associated polygons ( 13 . 32 ), wherein a structural element ( 14 . 17 . 21 . 27 . 28 . 29 ) into one or more structural element areas ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) on one or more layout levels ( 33 . 34 . 35 ), wherein instead of step 3) the following steps are carried out: 3a) checking the selected layout levels ( 33 . 34 . 35 ) of the layout structure ( 26 ) to match the base polygon ( 12 . 30 . 31 ) of the selected pattern (s) ( 11 . 25 ), where associated structural element areas ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) to structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ), the structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) of the structural element areas having matches ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ), 4) checking further structural element areas ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) in step 3a ) structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) to match the associated polygon (s) ( 13 . 32 ) of the selected pattern (s) ( 11 . 25 ) on the respective layout levels ( 33 . 34 . 35 ), 5) output of those structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ), the matches to both the base polygon (s) ( 12 . 30 . 31 ) as well as with the associated polygon (s) ( 13 . 32 ) of the patterns ( 11 . 25 ) on the respective layout levels ( 33 . 34 . 35 ) or those structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) that have no such matches. Method according to claim 2, characterized in that each pattern ( 11 . 25 ) into two or more basic polygons ( 12 . 30 . 31 ) and one or more associated polygons ( 13 . 32 ), wherein instead of steps 3a) and 4) the following steps are carried out: 3b) checking the selected layout levels ( 33 . 34 . 35 ) of the layout structure ( 26 ) match the base polygons ( 12 . 30 . 31 ) of the selected pattern (s) ( 11 . 25 ), where associated structural element areas ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) to structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ), the structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) of the structural element areas having matches ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 3c) checking further structural element areas ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) in step 3b ) structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) on further layout levels ( 33 . 34 . 35 ) to match the other base polygons ( 12 . 30 . 31 ) of the selected pattern (s) ( 11 . 25 ), the structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) of the matches on pointing structure element areas ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 4a) check further structural element areas ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) in step 3c ) structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) on the respective layout levels ( 33 . 34 . 35 ) to match the associated polygon (s) ( 13 . 32 ) of the selected pattern (s) ( 11 . 25 ). Method according to one of the preceding claims, characterized in that a comparison of each structural element region ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) with the base polygon ( 12 . 30 . 31 ) of the respective sample ( 11 . 25 ) is done by trying the base polygon ( 12 . 30 . 31 ) by a transformation such as by a displacement, by a rotation, by a mirroring or by a combination of these transformations with the structural element region ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ). Method according to Claim 4, characterized in that, for checking for conformity of a structural element ( 14 . 17 . 21 . 27 . 28 . 29 ) with an associated polygon ( 13 . 32 ) the associated polygon ( 13 . 32 ) is subjected to the same transformation as the base polygon ( 12 . 30 . 31 ) associated with the associated polygon ( 13 . 32 ), wherein it is checked whether the structure element area ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) of the structural element ( 14 . 17 . 21 . 27 . 28 . 29 ) with the associated polygon ( 13 . 32 ) or whether the structure element area ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) the associated polygon ( 13 . 32 ) includes. Method according to one of the preceding claims, characterized in that the layout structures within the selected layout levels ( 33 . 34 . 35 ) are checked in such a way that all possible sections from the layout levels ( 33 . 34 . 35 ) and these formed sections with the patterns ( 11 . 25 ) are checked for conformity. Method according to one of claims 1 to 5, characterized in that by a preselection structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) or structural element areas ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ), which are either similar to the patterns ( 11 . 25 ) or with the basic polygons ( 12 . 30 . 31 ) or by their function or by their nature for conformity with the samples ( 11 . 25 ) are eligible for verification, these preselected structural elements ( 14 . 17 . 21 . 27 . 28 . 29 ) or these preselected structural element regions ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) with the patterns ( 11 . 25 ) or with the basic polygons ( 12 . 30 . 31 ) are checked for conformity. Method according to one of the preceding claims, characterized in that, if one or more structural element regions ( 36 . 37 . 38 . 39 . 40 . 41 . 42 . 43 . 44 ) of a structure ( 14 . 17 . 21 . 27 . 28 . 29 ) with one or more base polygons ( 12 . 30 . 31 ) of a sample to be tested ( 11 . 25 ) the structural element in question ( 14 . 17 . 21 . 27 . 28 . 29 ) through the pattern ( 11 . 25 ) is replaced. Computer program product and computer program for exam of layout structures, which is designed such that after input of the layout structures to be checked and the pattern to be checked a method according to a of the preceding claims executable is. disk with a computer program product or computer program as claimed 9th Method in which the computer program product or the computer program according to claim 9 from an electronic data network such as from the Internet to a connected to the data network Computer is downloaded.