DE10137457B4 - Procedure for polynomial calculation with 1-bit coefficients - Google Patents

Abstract

Method for polynomial calculation with 1-bit coefficients, the calculation in a multiplier (MAC) of a processor with an arithmetic unit, which is fractionated into slices, with data paths implemented therein in which a switchable 1-bit shift function is present is carried out, characterized in that the polynomial calculation is carried out together with the associated 1-bit coefficients in cross-slice data word width in parallel in the data paths, this calculation within a first processing stage in which a 1-bit shift of the entire data word in the direction high-order bits of the data word is executed, and a second processing stage, which comprises a bit-wise multiplication of the data word with the present 1-bit coefficients and subsequently the accumulation of the product to the previously stored value in the accumulator.

Description

The invention relates to a method for polynomial calculation with 1-bit coefficients, the calculation in a multiziplier accumulator (MAC) of a processor with an arithmetic unit which fractionates into slices is, with data paths implemented therein, in which a switchable 1-bit shift function is available.

The polynomial calculations with 1-bit coefficients are preferred when implementing the algorithms of finite impulse response filters (FIR) applied.

Such a filter algorithm finds most frequently in hardware encoders with polynomeric division use. This use case is with Most well known in the art. The algorithm creates one systematic code by adding n-k parity check symbols to the sequence of data symbols.

The polynomial spelling of the code word c (x) is therefore: c (x) = p (x) + x nk d (x) where the data symbols d0, d1, ... dk-1 are regarded as coefficients of a polynomial. The parity symbols are shifted by nk places compared to the data word.

p (x) is precalculated in that a generated polynomial g (x) divides the code word c (x) so that no remainder remains (remainder class 0):

The polynomial calculations after State of the art takes place in the processors, which are data paths have a certain word width and that as a multi-multiplier accumulator (MAC) are configured in slices. It contains these slices with the implemented data paths logical shift registers (shifters), Adders and multipliers, the latter either in integers Operating mode or an operating mode with detachable carry work.

The operating mode with detachable carry is in the prior art for the multipliers contained in the data paths preferred applied to speed up the calculation processes and savings to achieve in hardware. This means that in the Data paths set operating mode with detachable transfer the multiplier and adder in the computing path the carry information of the individual data paths need not be evaluated.

Data words for fast polynomial calculation with big Bit widths must be processed when using such slices, in which the data paths in certain fixed processing widths are configured, one divided into sequential arithmetic steps Polynomial calculation can be made. This proves to be absolutely necessary if the size of the too processing bit width of the data word the processing width of the Slices exceeds.

These parallel in independent slices organized sequential, each within the slices Part processing of the data words requires a lot of control power from the processor when managing and assigning each slice processed and merged below Parts of the word.

This turns out to be the case at the stand the fundamental disadvantage of technology, which is essential for the implementation of the Polynomial calculation in the processor using coefficients with lower Bit width, e.g. 1-bit coefficient is severe. This results, that the processing speed is limited and limited, the effort of hardware and software.

Although in the prior art by the US patent US 6,140,839 a solution for the technology area of (complex) field programmable architecture (CFPA, FPA) is known, in which the CLB (Configurable Logic Block) necessary in this technology embody special PASM (partial add subtract multiply).

This allows computing-intensive hardware areas relative to circuits within this technology area area efficient will be realized.

However, this special solution cannot be generalized and it is the many times higher Requirements for component density and processing speed e.g. not growing in VLSI design of processor circuits.

Another solution, as in the patent WO 01/39378 A1 is disclosed, can be independent of the circuit technology Hardware and software resources can be saved.

This disclosed in the publication Circuit arrangement only affects the type of decoder for block-based Error correction codes and here in particular the Reed-Solomon error correction technology. The particular arrangement presented is for general polynomial computation not usable.

So now there is the task at the polynomial calculation using 1-bit coefficients of data words with great Bit width to increase the processing speed in the processor and to reduce the necessary hardware and software effort.

The procedural solution to this task provides that the polynomial calculation together with the associated 1-bit coefficients in parallel slice-wide data word width in the Data paths are done. This calculation is initiated within a first processing stage, in which a 1-bit shift of the entire data word in the direction of the most significant bits of the data word is carried out. This is followed by a second processing stage, which comprises a bit-wise multiplication of the data word with the present 1-bit coefficient and subsequently the accumulation of the product to the previously stored value in the accumulator.

With this solution it becomes clear that, deviating from the prior art, the data words by slice-spanning and thus simultaneous, parallel processing in the MAC representing data paths is made.

An extension of the procedural solution to the Task provides that the data paths, which each belong to a slice, optionally in an operating mode with detachable carry, without evaluation of carry Multipliers / Adders, or in an integer mode with carry evaluation of the multiplier / adder can be configured.

This extension leads to a Programmability of the data paths. So the hardware can be optimal exploited and to solve the calculation task be adjusted.

An advantageous procedural solution to this Task provides that the existing in the data paths Switchable 1-bit shift function thanks to additional switchable cross-slice Interconnections are expanded. from the exits of the Slices by the associated each of the highest order Data path to be realized, to the inputs of the respectively agreed least significant Data paths of the at least indirectly neighboring higher-order ones These switchable additional connections are introduced into slices.

The solution to the task is aimed depends on the fact that the 1-bit shift function available within the slices between adjacent data paths through additional switchable connections between the slices in the form of multiplexers to ensure the cross-slice 1-bit shift function from the low-order slices to the at least indirectly neighboring ones high-order Slices is expanded.

Exploitation of within the Slice's existing 1-bit shift function contributes the desired hardware effort minimization and also for Cycle minimization in the software.

A variant of the procedural solution to the task provides that the two-stage polynomial calculation with 1-bit coefficients in the data paths of a slice is started so that the first processing stage corresponds to a basic position of the first and second multiplexers. A first Tor1MUX1 and Tor1MUX2 input of the first and a second multiplexer are switched through ( 1 ). Thus, on the one hand, the output value of the accumulator is applied to the first input of the multiplier, and on the other hand, via the interconnection, the multiplier output value is applied to the first input of the adder of an at least indirectly adjacent least significant data path of a more significant slice m. A first Tor2MUX1 and Tor2MUX2 input of the first and of the second multiplexer is also also switched through, so that the arithmetic value ONE is present at the second input of the multiplier ( 1 ).

In addition, with the first switched through Tor2MUX2 input of the second multiplexer at the second input of the Add an arithmetic zero. It will continue to be realized that the second Tor1MUX1 and Tor1MUX2 inputs as well as the second Tor2MUX1 and Tor2MUX2 inputs of the first and second multiplexers are blocked antivalent.

The first processing stage is followed by a second processing stage. The settings correspond of the first and second multiplexers with a subsequent position. The bit-wise multiplication is started by the one provided 1-bit coefficient over the second Tor1MUX1 input to the first input of the multiplier is created and on the other hand the data word bit applied via the CBUS via the second Tor2MUX1 input to the second input of the multiplier arrives. The multiplier is a multiplication of the 1-bit coefficient executed with the entered data word bits.

This will be shown at the exit of the Multiplier generated product by the second connected Tor2MUX2 input of the second multiplexer also in the following position applied to the second input of the adder belonging to the MAC. Furthermore, the second Tor1MUX2 input is in the following position the arithmetic value provided at the output of the accumulator previous polynomial calculation to the first input of the adder created and it is now, after the addition in the adder, over the Input of the accumulator, the new calculated value is stored in the accumulator.

It is also realized that the first Tor1MUX1 and Tor1MUX2 inputs and the first Tor2MUX1 and Tor2MUX2 input in the following position are equivalent to the switching states the basic position are locked.

Another procedural solution to the problem stipulates that the polynomial calculation only with a part of the available slices accomplished becomes.

A special further procedural solution to the task provides that the polynomial calculation only with a part of the processing width of the slice with a certain number of data paths.

An execution of the further procedural solution of the The task envisages a partial processing width logic Overflows occurring during the polynomial calculation over the intended processing range recognizes and further processing in the polynomial calculation in the permissible Guaranteed slices in the intended processing areas.

The invention is based on the following of an embodiment are explained in more detail. In the associated Shows drawings

1 a substructure of the multiplier accumulator in the processor

2 a block diagram of an area of the multiplier accumulator with implemented partial processing width logic

In 1 a partial structure of the multiplier accumulator (MAC) present in the processor is shown, the fractionation into slices being exemplified by the representation of slice m 23 and Slice m-1 24 is made clear.

These slices are in turn in data paths that are represented by the least significant bit strips of the slice m 4 and agreed the most significant bit stripe of the slice m-1 5 be represented, organized.

The optional setting of the operating mode with detachable carry or the integer mode of the multiplier / adder is by the respective processing of their carry outputs for Entry in the carry inputs of Multiplier / adder of the next higher order Data path of the slice preset. In the present integer mode the carry output multiplexers for the carry output signals connected through.

With pre-selected operating mode with detachable carry are the carry output multiplexers instead of the interconnections for the carry output signals the multiplier / adder is locked and it is instead instead switched through a zero signal, i.e. further processing of the carry outputs of the Multiplier / adder is avoided.

At the in 1 Substructure of the multiplier accumulator shown in the processor is the operating mode with detachable carry. This is the multiplier and adder carry output MUx, respectively 25 . 26 switched in such a way that the NULL applied to the carry inputs of the multiplier 1 and adders 2 be created.

The individual bit positions of the 1-bit coefficient and the data word to be processed are provided at the inputs of the first multiplexers of the bit strips. So in the slice m-1 24 the 2 ^15- bit position of the 1-bit coefficient, the 2 ^15- bit position of the 1-bit coefficient for slice m-1 19 , at the second Tor1MUX1 input 14 and the 2 ¹⁵ bit position of the data word for slice m-1, the data value of the 2 ¹⁵ bit position of the data word for slice m-1 21 , at the second Tor2MUX1 input 15 each created. The two-stage polynomial calculation of the data word with the 1-bit coefficient in the data paths of a slice is carried out with a first processing stage, which involves a basic position of the first multiplexer 6 and the second multiplexer 7 corresponds, started.

Here, a first Tor1MUX1 and Tor1MUX2 input 10 . 12 of the first and second multiplexers 6 . 7 switched through. On the one hand, this makes the output value of the accumulator 3 to the first input of the multiplier 1 created. On the other hand, the interconnection 27 the output value of the multiplier 1 to the first input of the adder of the at least indirectly adjacent least significant data path of a more significant slice m 23 created.

There will still be a first Tor2MUX1 and Tor2MUX2 input 11 . 13 of the first and second multiplexers 6 . 7 also switched through, so that on the one hand at the second input of the multiplier 1 the arithmetic value ONE is present. On the other hand, with the first Tor2MUX2 input switched through 13 of the second multiplexer 7 at the second entrance of the adder 2 created an arithmetic zero.

Furthermore, in the first processing state, the basic state of the first and second multiplexers set for this purpose 6 . 7 ensures that the second Tor1MUX1 and Tor1MUX2 inputs 14 . 16 and second Tor2MUX1 and Tor2MUX2 inputs 15 . 17 is antivalent locked.

In a second processing stage following the first processing stage, which has a subsequent position of the respective first and second multiplexer which is antivalent to the basic state 6 . 7 corresponds, the bit-wise multiplication of the 1-bit coefficient with the entered data word bit is carried out, here for the slice m-1.

This is done on the one hand by entering the 2 ^15- bit position of the 1-bit coefficient for slice m-1 19 via the now connected second Tor1MUX1 input 14 to the first input of the multiplier 1 , On the other hand, the input of the CBUS 22 provided 2 ¹⁵ bit position for slice m-1 of the data word, the data value of the 2 ¹⁵ bit position of the data word for slice m-1 21 , via the connected second Tor2MUX1 input 15 to the second entrance of the multiplier 1 executed.

This is what happens at the output of the multiplier 1 generated product through the connected second Tor2MUX2 input 17 of the second multiplexer also in the following position 7 into the second input of the adder belonging to the MAC 2 created and it is through the second Tor1MUX2 input in the following position 16 the one at the output of the accumulator 3 provided calculation value of a previous polynomial calculation to the first input of the adder 2 created.

After the addition in the adder 2 is via the input of the accumulator 3 the new calculation value in the accumulator 3 stored.

Furthermore, the first and second multiplexers 6 . 7 ensures that the respective first Tor1MUX1 and Tor1MUX2 inputs 10 . 12 as well as the first Tor2MUX1 and the Tor2MUX2 input 11 . 13 each takes the locked switching state. These switching states are antivalent to the switching states of the basic position in accordance with the subsequent position assumed.

In the in 2 block diagram of an area of the multiplier accumulator with implemented partial processing width logic 36 is a substructure of a MAC, consisting of the slice k 30 , Slice k-1 31 , Slice 0 and the associated coefficient register k 33 , Coefficient register k-1 34 , Coefficient register 0 35 , shown.

The assignment values of the individual bit positions of the respective 1-bit coefficients are stored one by one in the associated coefficient registers and lie together with those from the CBUS 22 provided assignment values of the bit positions of the data word for processing at the respective slices.

Processing with the polynomial calculation is made in the slices so that they have such a processing range in which not all of the data paths associated with the slices are used for the calculation be used.

Also, not all slices are used in the processing by the interconnection 27 bypasses neighboring slices. The part processing width logic 36 detects overflows and directs them via the bus control signal 37 the pre-selected processing range on the CBUS 22 on.

1

multipliers

2

adder

3

Accumulator

4

of lowest Bit strips of the slice m

5

agreed most significant Bit strips of the slice m-1

6

first multiplexer

7

second multiplexer

8th

first MUX1 Gate

9

second Mux1 Gate

10

first Tor1MUX1 input

11

first Tor2MUX1 input

12

first Tor1MUX2 input

13

first Tor2MUX2 input

14

second Tor1MUX1 input

15

second Tor2MUX1 input

16

second Tor1MUX2 input

17

second Tor2MUX2 input

18

2 ^0- bit position of the 1-bit coefficient for slice m

19

2 ^15- bit digit of the 1-bit coefficient for slice m-1

20

Data value of the 2 ⁰ bit position of the data word for slice m

21

Data value of the 2 ¹⁵ bit position of the data word for slice m-1

22

CBUS

23

Slice m

24

Slice m-1

25

Multiply the carry output MUX

26

Adder carry output MUX

27

intercommunication

28

first MUX2-TOR

29

second MUX2-TOR

30

Slice k

31

Slice k-1

32

Slice 0

33

coefficients Register k

34

coefficients Register k-1

35

coefficients Register 0

36

Part processing widths logic

37

Bus control signal

Claims (7)

Method for polynomial calculation with 1-bit coefficients, the calculation in a multiplier (MAC) of a processor with an arithmetic unit, which is fractionated into slices, with data paths implemented therein in which a switchable 1-bit shift function is present is, is carried out, characterized in that the polynomial computation is carried out together with the corresponding 1-bit coefficient in slice border data word width parallel in the data paths, wherein this calculation is within a first processing stage, in which a 1-bit shift of the entire data word in the direction high-order bits of the data word is executed, and a second processing stage, which comprises a bit-wise multiplication of the data word with the present 1-bit coefficients and subsequently the accumulation of the product to the previously stored value in the accumulator. A method according to claim 1, characterized in that the data paths that each belong to a slice are optional in an operating mode with detachable carry without evaluating the carry of the multiplier or in an integer mode with carry evaluation of the multiplier can be configured. Method according to Claims 1 and 2, characterized in that the switchable 1-bit shift function present in the data paths is provided by an additional cross-slice function switchable interconnection ( 27 ), is expanded, whereby the switchable interconnections (from the output of each slice, which is implemented by the output of the associated most significant data path, to the input of the least significant data path agreed for each slice) 27 ) is performed, and thereby the 1-bit shift function is guaranteed at least to indirectly neighboring higher-value slices. Method according to Claims 1 to 3, characterized in that the two-stage polynomial calculation of the data word with the 1-bit coefficient in the data paths of a slice is started by the first processing stage having a basic position of the first multiplexer ( 6 ) and second multiplexer ( 7 ) corresponds to a first Tor1MUX1 and Tor1MUX2 input ( 10 ); ( 12 ) of the first and second multiplexer ( 6 ); ( 7 ) are switched through and thus on the one hand the output value of the accumulator ( 3 ) to the first input of the multiplier ( 1 ) and on the other hand via the intermediate connection ( 27 ) the output value of the multiplier ( 1 ) to the first input of the adder of the at least indirectly adjacent least significant data path of a more significant slice m ( 23 ) that a first Tor2MUX1 and Tor2MUX2 input ( 11 ); ( 13 ) of the first and second multiplexer ( 6 ); ( 7 ) is also switched through, so that at the second input of the multiplier ( 1 ) the arithmetic value ONE is present and also with the switched through first Tor2MUX2 input ( 13 ) of the second multiplexer ( 7 ) at the second entrance of the Addiere ( 2 ) an arithmetic ZERO is created so that the second Tor1MUX1 and Tor1MUX2 inputs ( 14 ); ( 16 ) and second Tor2MUX1 and Tor2MUX2 input ( 15 ); ( 17 ) of the first and second multiplexers ( 6 ); ( 7 ) is blocked in an equivalent way that in a second processing stage following the first processing stage, which is followed by the respective first and second multiplexers ( 6 ); ( 7 ) corresponds to the bitwise multiplication by entering the 1-bit coefficient provided via the second Tor1MUX1 input ( 14 ) to the first input of the multiplier ( 1 ) as well as via the CBUS ( 22 ) Data word bit present via the second Tor2MUX1 input ( 15 ) into the second input of the multiplier ( 1 ) that in the multiplier ( 1 ) A multiplication of the 1-bit coefficient with the entered data word bit is carried out, that in this case at the output of the multiplier ( 1 ) the generated product subsequently through the connected second Tor2MUX2 input ( 17 ) of the second multiplexer, which is also in the following position ( 7 ) into the second input of the adder belonging to the MAC ( 2 ) and that the second Tor1MUX2 input in the following position ( 16 ) at the output of the accumulator ( 3 ) provided calculation value of a preceding polynomial calculation at the first input of the adder ( 2 ) is created and now subsequently, after addition in the adder ( 2 ), via the input of the accumulator ( 3 ) the new calculation value in the accumulator ( 3 ) is saved that the respective first Tor1MUX1 and Tor1MUX2 input ( 10 ); ( 12 ) and first Tor2MUX1 and Tor2MUX2 input ( 11 ); ( 13 ) are blocked in the following position, equivalent to the switching states of the basic position. Method according to claims 1 to 4, characterized in that the polynomial computation with part of the slices, these Selection of slices are grouped variably, is executed. Method according to claims 1 to 5, characterized in that that the polynomial calculation is only part of the processing range of the slice and is executed with a certain number of data paths. A method according to claim 6, characterized in that a partial processing width logic ( 36 ) recognizes overflows occurring during the polynomial calculation over the intended processing width and that the further processing during the polynomial calculation in the permitted slices in their processing areas by a bus control signal 37 is guaranteed.