DE102004005123B4 - Arrangement for the translation of virtual instructions in a data processing unit - Google Patents

Abstract

Arrangement for the translation of virtual instructions in a data processing unit having a processor core (3), a first instruction memory (2), a second instruction memory (7, 70) and a memory access unit (6, 60), all of which are accessible via a first address and data bus ( 11, 12) are interconnected, wherein the processor core (3) and the memory access unit (6, 60) via the first address and data bus (11, 12) can get an instruction from the first instruction memory (2),
characterized,
In that the instruction fetched from the first instruction memory (2) by the memory access unit (60) is a virtual instruction which the memory access unit (60) converts to a memory address of the second instruction memory (70), the conversion of the virtual instruction to the memory address of the memory second instruction memory (70) is effected in that the bits of the virtual instruction (D7 - D0) are applied directly to a corresponding number of address lines (A12 - A5) of a further address bus (23rd to 23rd) between the memory access unit (60) and the second instruction memory (70) ) are given,...

Description

The The invention relates to an arrangement for the translation of virtual instructions in a data processing unit with a processor core, a first instruction memory, a second instruction memory and a Memory access unit, all via a first address and Data bus are interconnected, with the processor core as well the memory access unit via the address and data bus an instruction from the first instruction memory can get.

A such basic circuit structure forms the central unit a known data processing unit, said central unit is implemented as a custom, integrated component (ASIC). The first instruction memory is outside the ASIC as external RAM while the second instruction memory within the ASIC is implemented as internal RAM. The main processor fetches the program to be executed from the external RAM in the form of machine instructions and uses the internal RAM for caching. The memory access unit, for example a graphics controller, also accesses the external RAM and shares the Address and data bus with the main processor. To this known data processing unit belong Furthermore, acoustic and graphic interfaces as well as interfaces to Mass storage devices, such as hard disks and DVDs. The data processing unit is preferably in today navigation devices used in motor vehicles.

ever according to the desired Application, the central unit can also be combined with other hardware components and be used in other electronic devices, such as for example, in audio and multimedia devices in motor vehicles or in portable telecommunications equipment. By the execution as ASIC the central unit is very compact and requires less power than one commercial Microprocessor unit, which is why the central unit preferably at so-called embedded systems is used.

In the known design processes the arithmetic unit belonging to the central unit exclusively in this way said machine instructions, i. such commands directly from the understood and executed in the arithmetic unit integrated processor core can. The processor core can be a CISC or a RISC processor. The machine commands are usually through the translation of a computer program written in a high level language Machine program generates, for what a specific to the target hardware and thus the executing Processor core adapted translator (Compiler) must be used.

There the machine programs that can not be transferred to other types of processors the flexibility To limit the development of new systems, one goes today more and more about, Programs to use when using translation tools from different processors can be understood. This will be a so-called virtual machine - so a virtual processor - defines which understands virtual machine instructions, in short virtual instructions and executes. The high-level computer programs are now in such a virtual Machine program translated and stored in a read-only memory. At runtime then have to the individual virtual commands into executable by the processor core Machine instructions translated become.

A meanwhile in the Embedded area very widespread programming language is Java. Java became a virtual machine called Java Virtual Machine (JVM) defines its associated virtual commands Java Be called bytecodes. Java bytecodes become offline from one Java computer program generated by compilation. To the bytecodes executable To make various technical solutions are known. At a first solution The bytecodes are written by means of a special, on the target hardware running software program, i. the program (the Interpreter) loads the bytecodes and leads they out on the processor core. A second solution is close to the first one connected, only the bytecodes are not interpreted there but by means of a just-in-time compiler shortly before execution in Machine instructions translated. The translated Machine commands are then in the form of several kilobytes to megabytes in memory.

In order to reduce the increased memory requirements for the interpreter or compiler as well as for the intermediate results of the translation in both solutions, hardware compilers were further developed. These are in the simplest form additional processors, which are in addition to the actual processing unit that contains the main processor, and which are the translation of the bytecodes in Maschinenbe each time the next virtual command is called. The translation that takes place directly when the virtual command is called significantly reduces the storage space requirement because only the few machine instructions belonging to the virtual command need to be cached.

Out EP-950216-B1 is one such additional processor in the form of a JAVA preprocessor known, which in addition to the actual main processor access to has an external instruction store in which the virtual instructions (Bytecodes) and possibly also machine instructions are stored directly. The preprocessor has a translation unit, in the translation table is stored, the corresponding to the virtual commands sequence of machine commands. Furthermore, in the preprocessor existing translation unit a special internal register RSP (register stack pointer) for Storage of the currently current number of the main processor register, which the last occupied position of the memory stack (top of contains memory stack), intended.

If the main processor receives an instruction from the external instruction memory request, then recognizes the preprocessor based on the associated Command address, whether it is a virtual command, the first translated into machine instructions or whether it is a machine command that is unchanged the main processor can be passed. Unless a virtual Command was requested, this is from the preprocessor from the external Command memory retrieved using the associated entry in the translation table as well as the current contents of the register RSP and the resulting Sequence of machine commands is the main processor via a Cache, a so-called Feeding Memory, provided.

The in the translation table filed entries to the virtual commands included depending on the complexity of the command different number of machine commands required to execute it are. Because the entries stored in direct succession in the memory of the translation unit are needed the preprocessor an additional Indexing Table, which corresponds to each virtual Command contains the respective starting point from the translation table.

Out the published on the Internet PhD Thesis "Microarchitectural Techniques to Enable Efficient Java Execution "by Ramesh Radhakrishnan is a hardware translation unit for Java bytecode known, which cooperates with a common processor. The hardware translation unit get the translation Bytecode from the instruction cache, preprocessed and translated him using a contained in the hardware translation unit ROM storage unit in the associated Machine instruction.

The US-4587612 discloses a so-called emulator auxiliary processor, which interacts with a standard CPU and between instructions Cache and data cache is switched. The auxiliary processor converts a source command into a machine command by a so-called Micro command is loaded, which is composed of a scaffolding part for forming machine command and a control part. The framework part becomes now according to the information in the control section based on data the source command to translate filled, where parts are copied or converted from the source command. This results in the associated Machine instruction.

task It is the object of the present invention to provide the known ASIC arrangement to extend so that with the extended arrangement also an execution of virtual Be missing possible becomes. The application-specific boundary conditions of the embedded systems in terms of preferably low unit costs and a small footprint should be taken into account.

The Task is by an arrangement described above with the characterizing features of claim 1 solved.

The arrangement according to the invention has a further address bus between the memory access unit and the second instruction memory. In the first instruction memory, virtual commands are now stored in addition to the machine instructions. Accesses the main processor to such a virtual command, the access is no longer directly, but is redirected through the memory access unit by the main processor responds to the corresponding allocated address range. When a virtual instruction is fetched, the memory access unit converts it into a memory address of the second instruction memory and then accesses the second instruction memory via the further address bus. At the Spei second instruction memory is stored a machine instruction, which belongs to a sequence of machine instructions that correspond to a translation of the virtual instruction in executable by the processor core program code. The machine instruction is then transferred in the usual manner from the second instruction memory via the first data bus to the processor core.

The Conversion of a virtual command into a memory address of the second instruction memory is done by directing the instruction is placed on the further address bus, d. H. the bit sequence of the virtual command is placed on an equal number of address lines. At a virtual command, which consists of 8 bits, will pay attention accordingly Address lines addressed. This special design reduces the amount of intelligent logic within the storage access unit, there is no active conversion or conversion of the virtual command in the memory address, but the first or second Data bus incoming voltage signals directly as voltage signals be output to the other address bus.

The inventive arrangement allows the extension of a known, to execute machine commands designed ASIC to an ASIC with integrated hardware compiler for virtual Commands. This extension requires only a small number of additional ones Gates, because the memory access unit already present in the ASIC just needs to be extended a bit and just another address bus in the form of a few data lines between memory access unit and second instruction memory. The cost and also the additional one Space required for the extension is so minimal, which is in marked contrast to the known versions stands where an additional preprocessor is introduced with its own memory and its own data processing. A preprocessor corresponds to a complete computing unit, what the ASIC design several thousand gates needed become.

In addition, will in contrast to the known embodiments in the inventive arrangement the translation not active by an additional But it is in the process of command access embedded on the first instruction memory. The picked up virtual Command takes only one on the way to the second instruction memory small "detour" via the memory access unit, where it is converted to a memory address of the second instruction memory becomes. The translation the virtual command in machine commands is as a result of it too not in the memory of the extra preprocessor but stored in the internal RAM of the main processor, the internal RAM just corresponds to the second instruction memory.

In A preferred embodiment of the invention is still a second Address and data bus present, the memory access unit connects to the first instruction memory. About this second address and Data bus is the memory access unit capable of requesting through the processor core to a direct memory access (DMA) to perform the first instruction store to a virtual instruction pick up while For example, the processor core over the first address and Data bus accesses the second instruction memory.

In A further embodiment of the invention contains the second instruction memory a table in which a fixed default to each virtual command Number of machine commands is stored. This eliminates the need an additional one Indexing table as described in EP-950216-B1, i.e. It is no longer necessary to join any virtual command to remember the respective starting point in the table. Rather, it is enough, the To know the address of the very first table entry, as this results in the Addresses of all other entries calculated can be.

The Calculation takes place in an advantageous embodiment indirectly via the Design of the address lines. That's because it's made of the virtual Command obtained memory address together from a number of upper Address bits corresponding to the virtual instruction, and one Number of lower address bits, determined by the number of machine commands per virtual command is set in the table, so must the Memory access unit only take care that the lower address lines according to the currently requested subentry of the respective be addressed correctly.

In a further simplification of the access to the second memory unit, the lower address bits of the further address bus correspond to the lower address bits of the first address bus. The memory access unit then does not require any intelligent logic for calculating the table entry currently to be read. In such an arrangement, the processor core requests a first instruction, which is read as a virtual instruction from the first instruction memory and output via the memory access unit to the upper lines of the further address bus. The lower address lines are not used, ie there is a logical zero. In the next step, the processor core requests a second command, ie he jumps in the command address one step further. The corresponding logical one on the lowest address line of the first address bus is di rectly passed to the associated lowest address line of the further address bus and thus read the second entry of the translation of the virtual command from the table.

There the translations belonging to different virtual commands in general consist of a different number of machine commands, Corresponding remedies are provided in further embodiments. Thus, when a table entry is less than the default Number of machine instructions introduced an additional jump function, which to a skip the unused, empty memory locations leads.

exceeds the at the translation number of machine instructions resulting from a virtual instruction the intended length of a table entry, this becomes a part of these machine commands stored in the first instruction memory and then the table contains a jump function on this part of the machine commands. alternative it is also possible to provide a third instruction memory configured as another internal RAM, which the additional Contains machine instructions and with the jump function then to this further internal instruction memory to branch.

at Another embodiment of the invention fetches the memory access unit direct memory access not just a virtual command from the first instruction memory, but multiple virtual instructions at once. This is also known as DMA burst read access. The virtual Commands are in addition to one cached existing internal buffer. The number of Access to the first instruction memory is thus reduced, which positively to the total computing speed of the arithmetic unit effect.

at another embodiment of the invention become the operand (s) belonging to a virtual instruction stored at a specified address. The addresses of these operands have to then not be calculated by the processor core, so the total executed Number of machine commands and thus the memory required by the program code is reduced.

The Invention will be described below with reference to an embodiment and the drawing and in further subclaims clarified. Show it:

1 a known ASIC;

2 a known arrangement for the translation of virtual commands;

3 a first embodiment of an inventive arrangement;

4 a second embodiment of an arrangement according to the invention.

1 shows a known arithmetic unit 1 with an externally arranged, first instruction memory 2 , as it is used today in navigation devices. The arithmetic unit 1 is executed as an ASIC. To the arithmetic unit 1 belong to a processor core 3 Among other things, a command cache 4 (Instruction cache) and a data cache 5 (Data Cache), a memory access unit 6 , a second internally-arranged instruction memory 7 and a bus interface 8th , Via the bus interface 8th is the arithmetic unit 1 with an external address bus 9 and an external data bus 10 connected to which in turn the first instruction memory 2 connected. The processor core 3 , the memory access unit 6 and the second instruction memory 7 all hang on a first address bus 11 and a first data bus 12 and are over these two buses with the bus interface 8th and thus with the first instruction memory 2 connected. The address busses are shown in white in the figures and the data buses are grayed out. The processor core 3 as well as the memory access unit 6 can over the first address and data bus 11 / 12 a bytewise read access to the first instruction memory 2 carry out. Since the two units have the first address and data bus 11 / 12 they may have to wait for each other.

In 2 the embodiment of a hardware translation unit known from EP-950216-B1 for the translation of virtual instructions, more specifically Java bytecodes, is shown. The basic structure of main arithmetic unit 15 and external instruction memory 16 that have an external address and data bus 17 are connected to each other, is similar to the arrangement of 1 , In addition, there is a preprocessor 18 in front which is a translation unit 19 contains, in which a translation table 20 and a register 21 are stored. The registry 21 contains the number of the register of the main processing unit, which stores the most recently occupied position of the memory stack (top of stack). Demands the main ruler 15 a next command to be executed, the preprocessor fetches 18 from the external instruction memory 16 the next Java bytecode and translate it using the translation table 20 and the entries in the register 21 in machine commands. The registry 21 makes it possible to find the required to certain bytecodes on the memory stack (stack) stored operands that are required, for example, to perform an arithmetic operation. The machine instructions resulting from the translation are stored in an intermediate buffer 22 (Feeding Memory) cached and from there to the main computing unit 15 transfer.

In 3 a first arrangement according to the invention is shown. From the in 1 illustrated arithmetic unit 1 with external, first instruction memory 2 It only differs in that the bus interface 8th has been omitted since the invention has both first and second internally, within an ASIC, arranged first instruction memory 2 is applicable. The processor core still exists 3 with the instruction cache 4 and the data cache 5 and the first address and data bus 11 / 12 , The first address and data bus 11 / 12 is both above and below the memory access unit 60 arranged to illustrate the process of translating virtual instructions.

From the construction opposite 1 the memory access unit was changed slightly 60 and the second instruction memory 70 , between which another address bus 23 was introduced. Due to the small modification of the ASIC 1 A very cost-effective hardware solution for translating virtual instructions was found. Only a few additional gates in the ASIC are required to integrate this additional functionality.

The operation of the modified memory access unit 60 and the interaction between the processor core 3 , Memory access unit 60 and second instruction memory 70 while translating a virtual command go off 3 and the tables below.

In the embodiment, it is the translation of Java virtual commands, so Java bytecodes. In the second instruction memory 70 a translation table is stored which contains a fixed number of eight machine commands for each bytecode. To the translation table in the second instruction memory 70 to be able to load, the connections 24 and 26 to the first address and data bus 11 / 12 needed.

The processor core 3 is a 32-bit processor, for example, a MIPS R 3000. So a machine command has a length of 32 bits (4 bytes). Per Java bytecode, therefore, 32 bytes of machine instructions are stored in the translation table due to the fixed number of eight machine instructions per table entry.

in the The following example shows the short Java shown in Table 1 Program for adding two integers and creating a new one Translated object. The bytecodes resulting from the Java program are in the second Column entered. To better understand the meaning of bytecodes serves column 3.

Table 1: Bytecodes of a Java program

The device address of the memory access unit 60 is the 0xFF000000, ie the memory access unit 60 gets over the eight upper bits of the first address bus 11 addressed. This will be in 3 thereby making clear that the address lines A31 to A24 for the activation of the memory access unit 60 (device select) are responsible.

So the processor core wants 3 a Java command from the first instruction store 2 fetch, it accesses the address area above the 0xFF000000, whereby access with the help of the memory access unit 60 he follows. For direct access to the first instruction memory 2 For example, to store data to be stored, the processor core calls 3 an address at which the memory access unit 60 is not activated via the address lines A31 to A24. Then the communication between the processor core takes place 3 and the first instruction memory 2 at the memory access unit 60 past what's in 3 through the bus lines shown interrupted 11 and 12 is illustrated. They are interrupted here because of that 3 exactly the case of access to a Java command is supposed to represent.

To explain the functional example, further preliminary remarks are required. Thus, the most recently stored entry of the Java memory stack (Top of Java Stack) is in the register 22 of the processor core 3 and is not yet in the first instruction memory 2 stored. The pointer to the address of the next free entry in the memory stack (Java Stack Pointer) is in register 23 ,

The base address of the Java bytecode in the first instruction memory 2 is the 0x87F80000. This value is in registers 21 Based on this base address, the Java address entered in Table 1 in the first column corresponds to an offset in order to arrive at the respective byte code.

The offset of the first Java bytecode, which is 0x10, is at offset 0x200 of the address range of the processor core 3 is mapped, ie the respective Java address is shifted by 5 bits to the left, in order therefrom the associated instruction address for the processor core 3 to create. The value 5 is in register 20 stored.

Conversely, the assigned address ranges mean the following: Tries the processor core 3 To read a next Java command to execute, it addresses an address above the 0xFF000000. This address must then be shifted 5 bits to the right and the base address of the first instruction memory 2 be logically ORed to the address of the first instruction memory 2 to receive Java bytecodes to be fetched. In 3 this is indicated by the memory access unit 60 the upper 13 bits of the base address 0x87F80000 (A31 - A19) directly on the first address bus 11 sets and the remaining 19 bits A18 - A0 from the 5 bits to the right shifted address bits A23 - A5 of the first address bus 13 wins. To store the base address in the memory access unit 60 serves the connection 25 to the first data bus 12 ,

The tab still appearing in the tables 1 serves for intermediate storage of values.

Table 2 illustrates the translation of the first Java bytecode 0x04 (iconst 1). The processor core 3 caused on the first address bus 11 an access to the address 0xFF000200. This is from the memory access unit 60 in the address 0x87F80010 of the first instruction memory 2 converted and from there the bytecode 0x04 is fetched. This is then on the first data bus 12 at.

Table 2: Translation of iconst 1

To translate bytecode 0x04 into a machine instruction, the "detour" via the second instruction memory now takes place 70 , How out 3 indicates that they correspond to the first data bus 12 lying data D7 - D0 the upper eight address bits A12 - A5 of the further address bus 23 over which the instruction memory 70 is addressed. This again corresponds to a shifting operation by 5 bits to the left. The middle address bits A4 - A2 are directly from the first address bus 11 passed through and the lower two bits A1 - A0 are not set.

Bits A4 - A0 correspond to the offset within an entry in the translation table. As with the second from the processor core 3 generated address, which can detect 0xFF000204, requests the processor core 3 the commands word by word, ie he jumps each by a word length of 32 bits on. The lower two bits, which are 4 bytes in memory, will never be occupied for this reason. For each Java bytecode, eight entries are stored in the translation table, which is why, starting from the first offset with the value 0, it must be continued seven times by 0x04 (32 bits). The last offset is therefore the 0x1C, which corresponds to an assignment of bit positions A4 to A2.

The conversion of the data 0x04 into the corresponding address in the translation table thus results in the value 0x0080. There is the first entry belonging to the translation for bytecode 0x04. This first entry ("sw r22, (r23)") is about the connection 26 to the first data bus 12 to the processor core 3 transfer.

This then requests the next command to be executed, ie it jumps in the command address by one word length. The storage access unit 60 accesses the first instruction memory 2 and retrieves there at address 0x87F80010 the byte code 0x04 (the lower 5 bits belonging to the offset are disregarded due to the shift operation). By subsequently adding the lower 5 bits (A1 and A0 as zero and address lines A4-A2) to the address of the second instruction memory 70 then the second entry in the translation table associated with bytecode 0x04 is accessed, at address 0x0084.

The translation of the bytecode 0x04 consists of three machine instructions, namely "sw r22, (r23)", "addiu r23, r23, 4" and "addiu r22, r0, 1", however, since each bytecode entry has a memory space of eight machine instructions If there are five places to skip, the corresponding branch instruction appears in Table 2 in line 3 ("beq r0, r0, 0x14"). A jump of 0x14 bytes corresponds to exactly one jump by 5 word lengths. The jump command in this example was before the last machine command to be executed set as the used processor core 3 has a pipeline architecture. The instruction pipeline is not completely emptied after a jump instruction, but the machine instruction in the pipeline after the jump is always executed as well. In order to optimally use this peculiarity, in all tables 2 to 5 the jump instructions are set before the last machine instruction to be executed.

table 3 contains a description of the translation the next Java bytecodes, 0x10 0x78 (bipush 120). The 0x78 is the operand of the bipush command.

The processor core 3 has previously made a last jump of 5 word lengths and therefore requests an instruction from address 0xFF000220 next. The conversion of the addresses and the access to the second instruction memory 70 done in the usual way.

The operand of the bipush instruction, number 120, is taken from the first instruction memory 2 fetched, for which the corresponding program counter of the processor core 3 from register 31 fetched and into an address of the first instruction memory 2 must be converted (second to fifth line of Table 3).

Table 3: Translation of bipush 120

When Next Java bytecode, the addition instruction 0x60 is translated (Table 4). This Command causes the two integers placed on the stack to be fetched as well as their addition. Because of that Only three machine commands are required, again a jump function before the last for translation belonging Machine command inserted.

Table 4: Translation of iadd

Lastly, a new object will be in the first instruction store 2 generated. This operation requires more than the maximum eight machine instructions, which is why the memory access unit 60 to one in the first instruction memory 2 stored external routine of machine commands must branch. The first command in Table 5 stores the stacked object, the top of stack. The next three machine instructions are to load the address 0x80001000 of the external routine into register R1 and to jump to this routine. Next, the java stack pointer is out of register 23 in the register 4 moved, where it is kept as an operand of the routine to be executed ("add r4, r0, r23") .This command is executed like all other jump instructions before the actual jump.

The following command ("add r23, r0, r2") is then executed after returning from the external routine 2 The return value of the external routine is stored as a new Java Stack Pointer after register 23 postponed. Finally, the new top of stack at this address is loaded ("lw r22, (r23)").

Table 5: Translation of new

4 shows a second embodiment according to the invention, in which the memory access unit 60 additionally via a second address bus 13 and a second data bus 14 to the first instruction memory 2 is connected. About this second address and data bus 13 / 14 can the memory access unit 60 on request by the processor core 3 direct memory access to the first instruction memory 2 perform while the processor core 3 simultaneously via the first address and data bus 11 / 12 to the second instruction memory 70 can access. However, nothing changes with regard to the execution of the translation of virtual commands.

Claims (12)

Arrangement for the translation of virtual instructions in a data processing unit with a processor core ( 3 ), a first instruction memory ( 2 ), a second instruction memory ( 7 . 70 ) and a memory access unit ( 6 . 60 ), all via a first address and data bus ( 11 . 12 ), wherein the processor core ( 3 ) as well as the memory access unit ( 6 . 60 ) over the first address and data bus ( 11 . 12 ) a command from the first instruction memory ( 2 ), characterized in that - that of the memory access unit ( 60 ) from the first instruction memory ( 2 ) command is a virtual command to which the memory access unit ( 60 ) in a memory address of the second instruction memory ( 70 ), wherein the conversion of the virtual instruction to the memory address of the second instruction memory ( 70 ) is performed in that the bits of the virtual instruction (D7 - D0) directly to a corresponding number of address lines (A12 - A5) of a between the memory access unit ( 60 ) and the second instruction memory ( 70 ) existing further address bus ( 23 ), and - that the memory access unit ( 60 ) via the further address bus ( 23 ) accesses the memory address of the second instruction memory ( 70 ), wherein at this memory address a machine instruction is stored, which belongs to a sequence of machine instructions which a translation of the virtual instruction in by the processor core ( 3 ) correspond to executable program code. Arrangement according to claim 1, characterized in that the memory access unit ( 60 ) via a second address and data bus ( 13 / 14 ) with the first instruction memory ( 2 ) and upon request from the processor core ( 3 ) via this second address and data bus ( 13 / 14 ) a direct memory access for transmitting a command from the first instruction memory ( 2 ) into the second instruction memory ( 70 ). Arrangement according to one of the preceding claims, characterized in that the second instruction memory ( 70 ) contains a table in each of which a virtual command is assigned a fixed number of machine commands. Arrangement according to one of the preceding claims, characterized characterized in that the recovered from the virtual command Memory address is composed of a number of upper address bits (A12 - A5), which correspond to the virtual instruction (D7 - D0), and a number of lower ones Address bits (A4 - A0) which by the number of machine instructions per virtual instruction in the Table is set. Arrangement according to one of the preceding claims, characterized in that the lower address bits (A4 - A0) of the further address bus ( 23 ) the lower address bits (A4 - A0) of the first address bus ( 11 ) correspond. Arrangement according to one of the preceding claims, characterized indicates that for a virtual command that is less than the fixed number of machine commands required, additionally a jump function to skip the empty memory locations are stored in the table. Arrangement according to one of the preceding claims, characterized characterized in that the jump function before the last actually to the translation belonging to the virtual command Machine command is stored. Arrangement according to one of the preceding claims, characterized in that, in the case of a virtual instruction which requires more than the fixed number of machine instructions, one of the machine instructions stored in the table is a jump function which is based on one in the first instruction memory ( 2 ) stored sequence of machine commands branched. Arrangement according to one of the preceding claims, characterized characterized in that in the table eight machine instructions per virtual Command are filed. Arrangement according to one of the preceding claims, characterized in that the memory access unit ( 60 ) several virtual instructions with a single direct memory access from the first instruction memory ( 2 ) and cache in a buffer. Arrangement according to one of the preceding claims, characterized characterized in that an operand associated with a virtual instruction is stored in a memory at a fixed address. Arrangement according to one of the preceding claims, characterized characterized in that the virtual instruction is a Java bytecode.