DE102004011458B4 - Circuit arrangement for providing a regulated operating voltage for a data carrier and method for driving a NMOS longitudinal control transistor - Google Patents

Abstract

Circuit arrangement (1) for providing a regulated operating voltage for a data carrier with
An input (2) for an input voltage (V _in ),
A longitudinal NMOS transistor (3) which is connected to the input (2) with a first load terminal (4) and forms an output for the regulated operating voltage (VCC) at a second load terminal (5), and
- A charge pump circuit (6) for providing a relation to the input voltage (V _in ) increased and the operating voltage (VCC) dependent drive voltage (V _ST ) for the control terminal (7) of the longitudinal control transistor (3),
characterized,
- That the charge pump circuit (6) has a first and a second tap (8, 9), wherein the first tap (8) is connected to the control terminal (7) and wherein between the first and the second tap (8, 9) at least an additional charge pump stage is arranged and
- That a control circuit (10, 11) is provided and adapted to the regulated operating voltage (VCC) to fall below a predetermined threshold to ...

Description

The The invention relates to a circuit arrangement for providing a regulated operating voltage for a disk with an entrance for an input voltage, a longitudinal NMOS transistor, which with a first load terminal is connected to the input and to a second load terminal an output for the regulated operating voltage forms and a charge pump circuit for providing a across from increased the input voltage and dependent on the operating voltage Drive voltage for the control terminal of the longitudinal control transistor. Furthermore The invention relates to a method for driving a NMOS longitudinal control transistor.

such Circuit arrangements become more contactless, in particular for the power supply disk, For example, contactless smart cards used. Is the operating voltage an integrated circuit of a data carrier smaller than the supply voltage, which generates, for example, in a receiving coil of the data carrier becomes a DC / DC converter needed. There may be switching regulators or linear regulators are used. If the expected variation the input voltage is high and the noise generated by the controller should be low, preferably a linear regulator is used. Especially in contactless applications, the input voltage very dynamic. The output voltage, however, must remain constant. These demands are made in a particularly suitable manner by a ge NMOS regulator in CMOS technology met.

NMOS transistors are especially good for that Control of a voltage suitable. At the control terminal, d. H. the Gate of the NMOS transistor, a control voltage must be applied, the bigger than the voltages at the two load terminals of the transistor. Around to enable this a charge pump circuit is used which is one opposite the Input voltage increased Voltage generated. Located at the output of the charge pump circuit a capacitor that is charged to the pumping voltage by moving charge on it, and in this way the drive voltage for the Provides control terminal of the transistor. Suitable charge pump circuits usually have a control input, which is with the regulated Operating voltage is connected. When the operating voltage drops increases the pumped voltage, so that the longitudinal control transistor is further controlled, causing an increase in the Operating voltage results.

Problematic is in known circuits of the prior art, when the nominal operating voltage already very low and only slightly higher than an undervoltage limit is below which an operation of the data carrier is not more is possible or allowed. At load jumps there is a risk that the operating voltage drops briefly and falls below the undervoltage limit. The one described above Control mechanism is too slow to compensate for such undershoots.

A first known possibility To fix this problem is sizing of the longitudinal regulator significantly increase. this leads to however, to an increased Power consumption and higher Costs. It is also possible the basic consumption of the circuit in the dimensioning higher than to set the maximum dynamic power consumption. At this solution While the dynamics of power consumption is not critical, it is solution in many applications, for example, in battery mode, not useful.

A another known possibility consists in recognizing a rapid drop in the operating voltage to stop immediately a clock signal of a digital consumer to reduce. this leads to however, to restrictions of operating behavior and is therefore usually not preferred Solution.

A at least theoretically possible Solution exists to dynamically change the design of the control loop. The Control speed is essentially determined by the bias current. The bigger the Bias current is the higher is also the speed of control. The bias current can be adjusted so that it is normally very low, which is to compensate slower load changes sufficient. If a higher one Control speed is required, the bias current is increased. Often It is known in advance when making operations on the disk should be, which have a high power consumption result. Before the implementation Because of such operations, the bias current is increased, then the surgery was done and subsequently lowered the bias current again. The interpretation of a However, such circuitry is extremely difficult, so that a reliable operation in all operating situations is not guaranteed can be.

From US 2003/0111986 A1, the US 6,275,395 B1 and the data sheet SDVS026C, REG101 from Texas Instruments, July 2001, circuit arrangements are known for providing a regulated operating voltage. NMOS transistors are used as longitudinal transistors, wherein a charge pump circuit for a relation to the input and output voltage he increased drive voltage ensures that is load-dependent.

Power supply circuit with longitudinal regulators are from EP 0 326 968 A1 and the US 5,682,093 A known. A control circuit is provided to increase the drive signal for the series transistor at higher loads in addition to regulation in a normal operating mode.

A power supply circuit with two parallel MOS output stages is in the DE 400 63 06 C2 described. The power supply circuit is driven by a charge pump circuit. The second stage is switched on when the output voltage drops below a certain value.

task The invention is a circuit arrangement for providing specify a regulated operating voltage for a data carrier, the has a low power consumption and still reliably correct load jumps. In addition, a suitable method should be specified.

These The object is achieved by a circuit arrangement of the aforementioned Sort of solved, characterized in that the charge pump circuit a first and a second tap, wherein the first Tap is connected to the control terminal and being between the first and the second tap at least one additional Charge pump stage is arranged, and that a control circuit provided and adapted to the regulated operating voltage to monitor for falling below a predetermined threshold and falls below the threshold value with the second tap to connect to the control terminal.

Regarding the The procedure becomes the task by a procedure with the characteristics of claim 3 solved.

at the circuit arrangement according to the invention Thus, a voltage is generated which is greater than the control voltage in a normal operating situation of the circuit arrangement. If necessary, if the operating voltage falls below a predetermined threshold, This becomes the second tap of the charge pump available higher voltage used to directly supply the voltage at the control terminal of the series-locked transistor increase, without the control circuit of the circuit arrangement being used. Such, the control circuit detuning intervention in the classic Model of a scheme referred to as disturbance would be allows one quick compensation of the dropped by a load jump operating voltage.

The Invention will be explained in more detail with reference to an embodiment.

The 1 shows a block diagram of a circuit arrangement according to the invention.

The 1 shows a circuit arrangement 1 for providing a regulated operating voltage for a contactless data carrier. A burden 13 is usually formed by an integrated circuit containing, for example, a controller and / or a memory. Depending on the type and mode of operation of the load 13 the power consumption is relatively even or fluctuates greatly. This is connected to an operating voltage V _CC , with which the load 13 is supplied, special requirements. The operating voltage V _CC must remain relatively constant despite large load changes. This is especially problematic because data carriers are often operated at a lower operating voltage limit in order to work as energy efficient as possible. The lower operating voltage limit, for example, by the specifications of the integrated circuit 13 determined because below the lower operating voltage limit of the integrated circuit 13 or the memory stops working properly. Although, as shown in the figure, a capacitor C3 is provided to support the operating voltage V _CC . The design of data carriers, however, often does not allow the support capacitor to be designed so large that it can support the operating voltage VCC sufficiently in the event of load jumps.

The Power supply of data carriers is also problematic in a second respect, because in many cases used contactless data carriers is the operating voltage by an electric field in conjunction with an on-disk provided provided in the figure but not shown coil antenna. The electric field induces an electrical voltage in the coil antenna, the strong of the strength dependent on the field is. Depending on how far away the data carrier is from the read / write device that generates the electric field is the induced voltage very tall or tiny.

mit W: Weite des Transistors, L: Länge des Transistors, β = μ_n·c'_ox mit μ_n : Mobilität, c'_ox : Kapazitätsbelag U_GS: Gate-Source-Spannung und V_TH: Abschnürspannung.In order to generate from the correspondingly strongly fluctuating, rectified input voltages V _in a constant operating voltage V _CC , a longitudinal regulator is provided, which according to the invention by a NMOS-Längsregeltransistor 3 is formed. The control transistor 3 has a self-regulating feature due to the design as NMOS regulator on. For a load variation, an NMOS regulator is self-controlling if the gate potential remains constant. As the load becomes smaller, the load current will be smaller and the gate-to-source voltage will also be lower. For this reason, the output voltage increases, ie the operating voltage required for the operation of the data carrier. In the case that the load becomes larger, the load current becomes larger, and the gate-source voltage U _GS must be correspondingly larger. The relationship is described by the formula:

with W: width of the transistor, L: length of the transistor, β = μ _n · c ' _ox with μ _n : mobility, c' _ox : capacitance U _GS : gate-source voltage and V _TH : pinch-off voltage.

It is a charge pump circuit 6 provided, which generates from the input voltage V _in or the operating voltage V _CC with respect to these increased control voltage V _ST , which is used to control the control terminal 7 the control transistor 3 is needed. As input voltage for the charge pump circuit 6 Preferably, the operating voltage V _{CC is} used, since their fluctuations are substantially lower than the fluctuations of the input voltage V _in .

The charge pump circuit 6 is additionally included in a control loop to further stabilize the operating voltage V _CC . For this purpose, a measured value is obtained via a voltage divider with two resistors R1 and R2, which is proportional to the current operating voltage V _CC . The measuring voltage becomes a regulator 12 where it is compared with a reference _voltage V _REF1 . Depending on the comparison, the charge pump circuit 6 controlled in a suitable manner. With decreasing operating voltage V _CC , for example, the pumping frequency f of the charge pump circuit 6 increase. The increased pumping frequency results in a higher voltage across a first capacitor C1 at a first tap 8th the charge pump circuit 6 because more charge is transported and after U = Q / C the voltage is proportional to the charge.

The charge pump circuit 6 has in this embodiment, several stages, where n stages for the generation of a voltage at the first tap 8th are provided and further m stages, which are connected on the input side to the output of the n stages, are provided for generating a voltage at a second tap 9 provided. The tap 9 is connected to a second capacitor C2.

The second tap 9 is over a switch 11 with the control terminal 7 the control transistor 3 connectable. The desk 11 is through an undervoltage sensor 10 controlled, the input side is connected to the operating voltage V _CC .

In a normal operating situation, the operating voltage V _CC via the self-regulation of the NMOS longitudinal control transistor 3 as well as the additional control via the controller 12 kept constant. The first n stages of the charge pump circuit 6 are used to generate the control voltage V _ST . The other m stages of the charge pump circuit 6 Although generate a voltage on the second tap 9 However, this voltage is not used to drive the control transistor 3 used. The desk 11 , which is designed in a concrete realization as a switching transistor is open because the undervoltage sensor 11 no voltage too low detected.

With a load jump, the current i _{L increases} in such a strong way that by the self-regulation of the longitudinal control transistor 3 the operating voltage V _CC can no longer be maintained above a predetermined threshold. Although a reduction in the operating voltage V _CC can in principle by an increased pumping frequency of the charge pump circuit 6 however, this control loop is too slow to respond to rapid changes in the load current i _L.

In this operating situation, the undervoltage sensor detects 10 the undershooting of the predetermined threshold value. The undervoltage sensor 10 is configured in the following embodiment such that at a gate of an NMOS transistor 16 a reference _voltage V _REF2 is applied. With a drop in the operating voltage V _CC at the source terminal of the transistor 16 increases the gate-source voltage U _GS , so that the Tran sistor 16 becomes conductive and the switch 11 such that it becomes conductive.

Then, the charge stored in the capacitor C2 is partially transferred to the capacitor C1, whereby the voltage across the capacitor C1 and thus at the control terminal 7 the longitudinal control transistor 3 elevated. Due to the increased voltage at the control connection 7 of the transistor 3 this is further controlled, so that the operating voltage V _CC increases.

The amount of voltage increase across the capacitor C1 depends inter alia on the ratio of the capacitances of the capacitors C1 and C2. The larger the capacitance of the capacitor C1 compared to the capacitance of the capacitor C2, the lower the resulting increase in voltage when closing the switch 11 ,

After the operating voltage V _{CC has} again risen above the predetermined threshold, detects the undervoltage sensor 10 and opens the switch 11 , ie the switching transistor used is high impedance. The charge flow from the capacitor C2 to the capacitor C1 is thereby interrupted.

In an example given purely by way of example, the setpoint value of the operating voltage V _CC is 2 V. Through the first n stages of the charge pump circuit 6 At the first tap, a voltage is generated which is typically 3V. Through the other m stages of the charge pump circuit 6 is at the tap 9 generates a voltage that is 4V. When closing the switch 11 the charge of the capacitor C2 is partially transferred to the capacitor C1, so that the voltage at the control terminal 7 of the transistor 3 rises by 200 mV. This is sufficient to raise the operating voltage V _CC above the predetermined threshold.

The Voltage values mentioned are to be understood as purely exemplary. The values occurring in a practical implementation depend on the respective boundary conditions and the dimensioning of the used Components off.

The circuit according to the invention and thus the method implemented by it are particularly advantageous since only a minimal additional space requirement is required. Because of the other m stages of the charge pump circuit 6 On the capacitor C2 results in a defined maximum charge, the detuning of the control loop made by closing the switch is precisely defined. Opening and closing the switch 11 can be done very quickly, so that a very fast response to changes in the operating voltage V _{CC is} possible. As a result of the rapid reaction, the charge-reversal process from the capacitor C2 to the capacitor C1 can also be terminated prematurely if the partial charge-reversal has already led to a sufficient increase in the operating voltage V _CC . The additional energy requirement of the circuit arrangement according to the invention 1 is very low.

The number of times in the charge pump circuit 6 used pump stages is of the desired voltages at the taps 8th and 9 dependent. For generating the opposite to the voltage at the tap 8th increased voltage at the tap 9 Also, a single additional pump stage may be sufficient.

1

disk

2

entrance

3

NMOS transistor longitudinal control

4

first load connection

5

second load connection

6

Charge pump circuit

7

control connection

8th

first tap

9

second tap

10

Under voltage sensor

11

switch

12

regulator

13

load

16

transistor

V _REF1 , V _REF2

reference voltages

 R1, R2

resistors

C1, C2, C3

capacitors

V _CC

operating voltage

V _ST

control voltage

i _L

load current

V _in

input voltage

Claims (4)

Circuit arrangement ( 1 ) for providing a regulated operating voltage for a data carrier with - an input ( 2 ) for an input voltage (V _in ), - an NMOS longitudinal control transistor ( 3 ) connected to a first load terminal ( 4 ) with the entrance ( 2 ) and connected to a second load terminal ( 5 ) forms an output for the regulated operating voltage (VCC), and - a charge pump circuit ( 6 ) for providing a control voltage (V _ST ) for the control terminal which is higher than the input voltage (V _in ) and dependent on the operating voltage (VCC) ( 7 ) of the longitudinal control transistor ( 3 ), characterized in that - the charge pump circuit ( 6 ) a first and a second tap ( 8th . 9 ), wherein the first tap ( 8th ) with the control connection ( 7 ) and wherein between the first and the second tap ( 8th . 9 ) at least one additional charge pump stage is arranged and - that a control circuit ( 10 . 11 ) is provided and is set up to monitor the regulated operating voltage (VCC) for falling below a predetermined threshold value and falls below the threshold value of the second tap ( 9 ) with the control connection ( 7 ) connect to. Circuit arrangement ( 1 ) according to claim 1, characterized in that the control circuit is controlled by an undervoltage sensor ( 10 ) and a switch ( 11 ) is formed. Method for driving a NMOS longitudinal control transistor ( 3 ) comprising the steps of supplying a control terminal connected to a first capacitor (C1) ( 7 ) of the transistor ( 3 ) with a in a normal operating situation of an operating voltage at an output of the transistor ( 3 ) Dependent control voltage (V _st), - charging a capacitor (C2) to a voltage that is greater than the control voltage in the normal operating situation, and - at least partial reloading of the second capacitor (C2) to the first capacitor (C1) when the Operating voltage falls below a predetermined threshold. Method according to claim 3, characterized that the increased Voltage on the second capacitor (C2) generated by a charge pump becomes.