DE102004016223A1 - Method of layout of dynamic RAM (DRAM) memory chips etc., with generating automatically transfer data train with information about set-up and/or functions of data lines or current paths by place and route system - Google Patents

Abstract

Method for layout design of DRAM memory chips etc. generates automatically transfer data train (10) with information about geometric set-up and/or function of data or current supply tracks by place and route system (1). Transfer data train is automatically transmitted to post-processing system (2) and/or recalled from data (3) bank by post-processing system. Post-processing in system is automatically carried out in dependence on data contained in transfer data train.

Description

The The invention relates to a method for the layout of semiconductor devices according to claim 1 and a system according to claim 9.

The The invention relates to the Place & Route process used in the design of semiconductor circuits for placement and wiring of the standard cells is made.

At the Designing ASICs is a high number (compared to memory design) of metal levels available for wiring, so that the standard cells can be placed very tightly; the wiring of the cells with each other is unproblematic.

at Memory devices (e.g., DRAMs) have fewer metal levels available leaving room for Wiring needed becomes. If you want to use standard cells, e.g. in the periphery of memory modules Arrange, typically only three metal levels in total and two of them for the wiring of the standard cells available. As these are the metal levels also partly in the standard cells and for the power supply Wiring is more difficult here than with the ASIC design. For this reason, only a much lower density the standard cells are reached.

on the other hand is currently on a high-volume product, such as the DRAM memory chips the need for space optimization very much in the foreground, so that even more compared to the ASIC design Effort in the area optimization the standard cells can or must be plugged.

At the Design of such circuits uses databases that are standard cells with different functions included (flip-flops, logic gates Etc.). These databases were created to make the design more complex Making circuits easier, which leads to certain design assumptions by discrete gradations of certain parameters in the database are stored permanently. This can lead to problems because these are fixed design specifications in conflict with other target functions, in particular the space requirement for wiring can reach.

The Today's Place & Route Programs can the extensive design rules, e.g. for the width and distances of Metal tracks for power supply, the design of transitions between the Metal tracks (vias), not completely edit. The Place & Route Programs deliver a preliminary design, but then with a post-processing tool has to be postprocessed by e.g. the power supply tracks be widened. Furthermore are used in post-processing e.g. also routines for uniform thickness distribution of layers and the application of OPC (optical proximity correction) carried out. The uniform thickness distribution the layers over the wafer is important so that the subsequent layer construction is not over sharp Edges between areas of different heights takes place.

Of the necessary data exchange between the Place & Route program and post-processing Program is done via a GDSII file, the standard for sharing layout information is. This GDSII file contains but exclusively information about the layout elements themselves, but not the arrangements of lines, so that e.g. Directions of vias and the isolation of wires (e.g., power tracks) in the post-processing step disposal stand. As a result, in post-processing, this step Information must be recalculated, which reduces the computational effort in the air drives. In particular, the increasingly complex rules for Definition of wide-dependent intervals and distance-dependent Wide post-processing post-processing make elaborate.

Of the present invention is based on the object, a better Integration between a Place & Route System and to create a post-processing system.

These The object is achieved by a Method solved with the features of claim 1.

First, will from a place & route System automatically transfers a transfer record with information about the geometric arrangement and / or function of lines, in particular Data lines or power tracks generated.

Subsequently, will the transfer record is automatically transferred to a post-processing system and / or through a post-processing System retrieved from a database.

One then Post-processing in the post-processing system is dependent of the data contained in the transfer record then automatically executed.

With the transfer data set it is possible to Information from the Place & Route Phase specifically to post-processing to transfer the once already gained information about make the draft available for post-processing.

there it is advantageous if the transfer data set contains information about the Width of lines depending of distances the lines and / or information about distances between lines in dependence whose width contains. With that you can In post-processing, these design parameters are specifically changed.

Advantageous It is also if the transfer record after the completion of the wiring through a place & route Procedure in Place & Route System is generated.

to Simplification of the design, it is advantageous if in post-processing an adaptation of a grid-based wiring takes place.

Further it is advantageous in grid-based wiring, if in the Post-processing for one Test line is determined whether an adjacent position of a line, is occupied, and subsequently dependent on the result automatically adjusts the geometry of the test lead he follows. By having several or all lines one after the other can be used as test leads, a complete picture the occupancy.

alternative can in post-processing an adaptation of a non-grid-based wiring respectively. It is advantageous if in post-processing for a first Line is determined, at which distance a second line arranged is and which geometric properties the second line has, subsequently dependent on from determining automatically an adjustment of the geometry. of the first line and / or the second line takes place. Especially advantageous it is when the adaptation of the geometry of the first and / or second Management in dependence of rules (electromigration rules), the line geometry (before in particular the width of the line) on the basis of electrical line parameters (e.g., expected current), he follows.

The Invention will be described below with reference to the figures of Drawings on several embodiments explained in more detail. It demonstrate:

1 a flowchart of the known method for the layout of semiconductor devices;

2 schematic representation of the operation of a first embodiment of the method and the system according to the invention;

3 schematic representation of the operation of a second embodiment of the method and the system according to the invention;

4A . 4B schematic representation of a grid-based wiring by means of an embodiment of the method according to the invention.

In 1 is the known per se procedure of a method for the layout of a semiconductor device, shown here a DRAM memory chip.

In a first step 101 a so-called netlist is generated, in which all logically necessary gates are interconnected. The netlist contains information about the function of individual elements of a layout, but still no information about the physical layout of the layout.

This design of the layout will be in the subsequent second step 102 with a Place & Route system 1 in which mostly standard cells are placed as building blocks for the logic gates.

The information about the placement of the standard cells are in a known manner in the third step 103 stored in a GDSII file. This file is then sent to a post-processing system 2 passed, in a fourth step 104 Among other things, the once defined layout changes again, in order to be able to generate smaller structures, eg through OPC.

In the fifth process step 105 the layout generated by post-processing is stored in a file (GDSII format) and in a sixth step 106 Then, a mask is created using the layout design.

A first embodiment of the method according to the invention modifies the second, third and fourth method steps as shown in FIG 1 , This first embodiment of the invention is schematically illustrated in FIG 2 shown.

This will be a GDSII file 3 from the Place & Route system 1 to the post-processing system 2 transmitted in a conventional manner. Parallel to this is the Place & Route system 1 a transfer record 10 generated by the Place & Route system 1 to the post-processing system 2 is transmitted.

In the transfer record 10 Information about the geometric arrangement of data lines and about the geometric dimensions of the data lines are stored. Alternatively, power supply tracks or other lines can be processed with an embodiment of the method according to the invention.

This data is thus made available to the post-processing system, which alone with the GDSII file 3 was not possible. The transfer record 10 can be transmitted as a separate data record (as in 2 shown) or as part of the GDSII dataset.

Using the information in the transfer record 10 can the post-processing system 2 get faster to an optimized layout, since the geometry data does not have to be regenerated first.

In 3 shows a second embodiment of the method according to the invention, in which the transfer data set 10 not to the post-processing system 2 but to a database 4 , From this database calls the post-processing system 2 the necessary information. The transfer of the GDSII file 3 takes place in the usual way.

The first and second embodiments can also be combined with each other.

at the implementation of distance-dependent Widths and width-dependent distances Of data lines one can between the cases of the grid-based and different from non-grid based wiring.

In In the event that at least partially all data lines on one defined grid, the implementation becomes simplified, since here all lines the same width and the same Have distance to each other. It just needs to be checked whether the respectively adjacent wiring grid positions are occupied or not. Dependent on this result then becomes an expansion in post-processing and / or a minor one Displacement of a line based on a correspondingly defined Distance / width table made.

In 4A and 4B are shown for reasons of simplicity Grids with exclusive horizontal wiring for lines. In 4A In one area all lines are occupied, so that the test line symbolized by arrows 21 has a neighbor on each side. This information may be in the transfer record 10 the test track 21 be assigned and stored. In 4B has the test lead 21 no immediate neighbors, so there is room for broadening the test track 21 consists.

In the event that at least some lines 20 not lying on a grid, the geometry of the lines can be changed further, which complicates the design process. In this case, it may be necessary to regulate the electromagnetic compatibility in the width and dimensioning of the lines 20 to take into account.

Successively different lines 20 as test leads 21 used to test the entire grid.

The Restricted invention in their execution not to the preferred embodiments given above. Rather, a number of variants are conceivable that of the inventive method and the system according to the invention also in principle different types Make use.

1

Places & Route System

2

Post-Processing system

3

GDSII data

4

Database for transfer record

10

Transfer Record

20

Cables, Power trains

21

test line

101-106

steps

Claims (8)

Method for the layout of semiconductor devices, in particular DRAM memory chips, in which a) from a Place & Route system ( 1 ) automatically transfer data ( 10 ) is generated with information about the geometric arrangement and / or function of lines, in particular data or power supply tracks, b) the transfer data set ( 10 ) automatically to a post-processing system ( 2 ) and / or by a post-processing system ( 2 ) from a database ( 4 ), c) post-processing in the post-processing system ( 2 ) depending on the data in the transfer record ( 10 ) is automatically executed. Method according to Claim 1, characterized in that the transfer data record ( 10 ) Contains information about the width of lines as a function of distances between the lines and / or information about distances between lines depending on their width. Method according to claim 1 or 2, characterized in that the transfer data record ( 10 ) after completion of the wiring by a Place & Route procedure in the Place & Route system ( 1 ) is produced. Method according to at least one of the preceding claims, characterized in that in post-processing an adaptation of a grid-based wiring ( 20 ) he follows. Method according to claim 4, characterized in that in post-processing for a test track ( 21 ) determines whether an adjacent position of a line ( 20 ), and then, depending on the result, an adaptation of the geometry of the test line ( 21 ) he follows. Method according to at least one of the preceding Claims, characterized in that in post-processing an adaptation of a non-grid based Wiring is done. Method according to Claim 6, characterized that in post-processing for a first line is determined, at which distance a second line is arranged and which geometric properties the second Having line, wherein then depending on the determination automatically adjusting the geometry of the first line and / or the second line takes place. Method according to claim 7, characterized in that that adaptation of the geometry of the first and / or second line dependent on of rules that govern the line geometry on the basis of electrical Check line parameters takes place.