DE102004022792A1 - Memory circuit for data storage esp. for mobile/cell phone, has control circuit for blocking and enabling read/write functions in first and second state - Google Patents

Abstract

A memory circuit (3) has a memory cells matrix (4), a control circuit (8) which is set into a first state with switch-on of the supply voltage to the memory circuit (3) and into a second state following initialization of the memory cells matrix (4). The control circuit (8), in the first state, blocks write and/or read of the memory cells matrix (4) and, in the second state, enables write and read of the memory cells matrix (4). An independent claim IS included for a method for driving a memory/storage circuit.

Description

Memory circuit Memory control unit for operating the memory circuit as well Method for driving the memory circuit and a method for operating the memory circuit

The The invention relates to a memory circuit having a memory cell array, which can be operated in an energy-saving mode. The invention further relates to a memory control unit for operating a such memory circuit. The invention further relates to a Method for driving such a memory circuit and a method for operating such a memory circuit.

Especially in mobile electronic devices is a low power consumption of the electronic used Components essential to the same battery life for a longer service life or, for the same service life, a lower required battery capacity with a smaller one Reach volume. This is usually the Device like that Constructs that individual function blocks depending on the operating condition go into a power-down mode or energy-saving mode or completely switched off become.

This applies to a storage system provided in the electronic device which is a memory controller and one or more memory circuits having. The memory circuit usually has a DRAM memory cell array on, e.g. can be designed as a low-power SDRAM. At a Such DRAM memory circuit usually has a standardized one State in which the memory circuit autonomously refresh the necessary performs the DRAM memory cells and no further commands from the memory controller needed to to keep the stored information stored. It's just necessary that the supply voltage to the memory circuit remains applied, so that the memory cells refreshed regularly can be.

There the memory circuit in this state is not from the memory controller must be controlled, there is the possibility of the memory controller in the energy-saving mode completely switch off the device, so as to save electricity. When the memory controller reconnects however, a problem arises. The memory controller must turn on again Can be detected, whether the memory circuit is still valid Contains information or not, because the supply voltage or the battery voltage at the memory circuit in the energy saving mode possibly also may have been switched off. In this case, the memory circuit must be reinitialized before further memory accesses.

The validity The data in the memory circuit can be basically on the Reading out for it check reserved addresses of the memory circuit previously, i. before the Taking the energy-saving mode, have been written in. Are these values when the memory control unit is switched on again? still present, the data in the memory circuit as valid considered. However, this has the disadvantage that in the memory circuit stored information certainly for a long time after switching off the supply voltage can be at least partially preserved. The correct reading of a date from a few such reserved Addresses are therefore not a really reliable indicator of the presence all other information in the memory circuit.

A Another known solution for this Problems is the storage of the state of the power supply the memory circuit in a non-volatile memory, such as a EEPROM, Flash or similar. This has the disadvantage that additional Components with a frequently elaborate Manufacturing technology must be realized, which is the overall system expensive.

It Object of the present invention, a memory circuit and Memory controller available to ask, with the simple way after leaving a Energy-saving mode through a memory controller can be determined, whether in the connected memory circuit data are still valid or not. It is a further object of the present invention to provide a Method for driving and a method for operating such Memory circuit available to deliver.

These The object is achieved by the memory circuit according to claim 1, the memory control unit Claim 5, the method for driving a memory circuit according to claim 11 and by the method for operating a memory circuit solved according to claim 17.

Further advantageous embodiments of the invention are specified in the dependent claims.

According to a first aspect of the present invention, a memory circuit having a Memory cell array provided. The memory circuit has a control circuit which is set to a first state when the supply voltage to the memory circuit is switched on and which is set to a second state after an initialization of the memory cell array. The control circuit is designed to block writing and / or reading out of the memory cell array in the first state and to allow writing and reading of the memory cell array in the second state.

On In this way, a memory circuit can be made available first after is switched to a first state indicating that that first the memory cell array must be initialized before being accessed can be. Only after initialization is the control circuit placed in a second state, which makes it possible to access the memory circuit access. This allows a memory controller, which consists of a Power saving mode wakes up, recognizing in the manner described below, whether in the memory circuit stored data valid are or not.

To For example, a status memory may be provided in the control circuit to be dependent on information stores from the first or second state.

The Memory circuit may include an energy-saving unit to the Memory cell field in an energy-saving mode to operate. Especially, when the memory cell array DRAM memory cells the energy-saving unit comprises a self-refreshing unit, to cyclically refresh the DRAM memory cells in the energy saving mode. This refresh is done without external control from a memory controller, so that the memory cell array with the DRAM memory cells automatically stores the stored data holds.

According to one Another aspect of the present invention is a memory controller to operate a connectable Memory circuit of the type described above provided. The memory controller has a detection unit to the first or the second Detect state of a connected memory circuit. It Furthermore, an initialization unit is provided in order to recognize of the first state to initialize the memory circuit. A Drive circuit is capable of detecting the second state the memory circuit according to a Normal operation mode to operate, and from the connected memory circuit Read data or write data into the memory circuit.

The Inventive memory controller is thus able to use a memory circuit of the type described above To work together in such a way that, on the one hand, it recognizes in which one State the connected memory circuit is located and dependent on the state either initializes the memory circuit to them subsequently operating in normal mode or operating in normal operation mode, since it was determined that the memory circuit since the last Initialize was not disconnected from the supply voltage.

Preferably For example, the detection unit is designed to use the drive circuit successively a first read of data from the connected Memory circuit, a write with the inverted at read data from the first read and a second read perform, wherein the first state of the memory circuit is detected when the data read during the first read and the second read Read data are not mutually inverted and wherein the second state of the memory circuit is detected, if the data read during the first read and the data read at the read second data are inverse to each other. This represents an easy way to determine in what state the memory circuit is located without both the memory controller and the memory circuit to implement a separate polling method.

Just if writing to the memory cell array is allowed according to the second state, recognizes the memory controller by reading the date and of the subsequent Reading out the inverted date that the intervening write has been successful. Are the data read out not inverse? to each other, the writing process has not been successful, and it is determined that the memory circuit is in the first state in which the writing and / or reading of the memory cell array is blocked.

In an advantageous embodiment, following detection of the state of the memory circuit, the content of the memory cells previously described with the inverted data is to be set to the initial state. This is done by writing back the data obtained on the first read. In the advantageous embodiment, this step is only imperative if the memory circuit was in the second state, but may also take place if the memory circuit was in the first state. As a result, the memory content has remained unchanged after the completion of the recognition process - this is advantageous in the application according to the invention, since any number of memory cells can be used without them being excluded from the normal application.

It it can be provided that the memory control unit the initialization unit for initializing the memory circuit by means of an initialization command performs.

According to one preferred embodiment the memory controller has an energy-saving unit to to be displaceable in an energy-saving mode, with the energy-saving unit having the detection unit is connected to after leaving the energy-saving mode to control the detection unit. The energy-saving mode of the storage controller is due to a reduced power consumption or by the complete shutdown the memory controller characterized.

According to one Another aspect of the present invention is a method for Driving a memory circuit provided. It is first a first or second state of a connected memory circuit detected and upon detection of the first state, the connected memory scarf device initialized. Upon detection of the second state, the connected Memory circuit according to a Normal operating mode for writing or reading data operated. The normal mode of operation includes conventional addressing of the memory cell array for writing or reading data. In particular, can be provided be that after initializing the memory circuit, the memory circuit according to the normal operation mode is operated.

Of the first or second state can be detected by one another following a first read of data, a write with the inverted data read in the first read and a second reading is performed, wherein the first state of the memory circuit is detected when the data read during the first read and the second read Read data are not inverse to each other. Of the second state of the memory circuit is detected when the at first read and the second read read data are inverse to each other. By a second inverted write back the data becomes the original one Memory contents restored.

According to one Another aspect of the present invention is a method for Operating a memory circuit provided. After turning on the supply voltage, a first state is taken, wherein in the first state, a writing and / or a reading of the Memory cell array is blocked. After receiving initialization signals for initializing the memory circuit, thereby initializing the memory circuit is set, the memory circuit is placed in a second state, wherein in the second state, writing and reading of the Memory cell array is allowed.

preferred embodiments The invention will be described below with reference to the accompanying drawings explained in more detail.

The single figure shows a storage system 1 in an electronic device (not shown), e.g. B. a mobile phone or other battery powered device. The storage system has a storage control unit 2 and a connected memory device having a memory circuit 3 contains. The memory circuit 3 has a memory cell array 4 containing memory cells (not shown) which are addressable via an address. The memory cells are preferably dynamic memory cells whose contents are refreshed by regular refresh cycles, but may also be static memory cells. Refreshing of the memory cells is done during normal operation of the memory circuit by the memory controller 2 specified. In normal operation is the memory circuit 3 switched so that over the bus connection 6 that the memory controller 2 with the memory circuit 3 connects, command signals, address signals and data signals can be transmitted to data in the memory cell array 4 to write or data from the memory cell array 4 read.

The memory circuit 3 still has an energy-saving unit 5 on top of that memory circuit 3 into an energy-saving mode, where the memory circuit 3 has a reduced power consumption. Thus, the memory cells of the memory cell array 4 does not lose the contents stored therein, the energy-saving unit points out 5 a self-refresh circuit 7 on, which is activated in the energy-saving mode, allowing it to refresh the memory cells of the memory cell array 4 controls.

When the memory circuit 3 is in an energy saving mode, the contents of the memory cell are continuously refreshed when a supply voltage VDD is applied. If the supply voltage V _{DD is} temporarily interrupted, the contents of the memory cells are used in a conventional memory system 4 when leaving the energy saving mode by the memory control unit 2 and the memory circuit 3 the memory controller 2 can not detect whether the previously stored data in the memory cell array 4 or whether they are deleted or invalid due to a temporary failure of the supply voltage V _DD .

For this reason, the memory circuit 3 a control circuit 8th which can be put in a first state and in a second state. In the first state, writing and / or reading out of the memory cell array is blocked, whereas in the second state writing and reading out of the memory cell array is permitted. The first state of the control circuit is assumed when the supply voltage is turned on. That is, after each failure of the supply voltage, the first state is automatically set in the memory circuit at the restart. The control circuit 8th assumes the second state if, after switching on the supply voltage, the memory cell array has been initialized, so that data can be written in and read out. Initialization is necessary to ensure proper functioning of the memory cell array 4 to ensure. The second state is thus taken as long as after initializing the supply voltage VDD to the memory circuit 3 is created.

The first or second state of the memory circuit 3 can in a state memory 9 the control circuit 8th which, after the power supply VDD is turned on again, is automatically written to the first state in the control circuit 8th is set. The provision of such a control circuit 8th allows the memory controller 2 to recognize if the in the memory circuit 3 stored data are valid or not valid.

The memory controller 2 has a detection unit 10 on, which can detect whether the connected memory circuit is in the first or second state. Is in the detection unit 10 a first state is detected, the initialization unit 11 instructed to initialize the memory circuit. The memory controller 2 also has a drive circuit 12 on which the command signals, address signals and data signals on the bus connection 6 provides. The initialization unit 11 is with the drive circuit 12 connected to detect the first state of the memory circuit 3 an initialization sequence via the drive circuit 12 on the bus connection 6 to send, so the memory circuit 3 is initialized. Represents the detection unit 10 the second state of the memory circuit 3 fixed, so is the drive circuit 12 switched to the requested by the entire system data or provided by the entire system for storing data in the memory circuit 3 to write or from the memory circuit 3 to read.

The detection of the first or second state by the detection unit 10 is done by the memory controller 2 after waking up from an energy-saving mode. To the storage controller 2 putting in energy-saving mode is an energy-saving unit 13 provided, the (all or) most of the circuits of the memory controller 2 turns off to reduce power consumption. When the energy saving mode is exited and returned to the normal operation mode, the detection unit becomes 10 from the further energy-saving unit 13 instructed the state of the connected memory circuit 3 determine.

The detection unit proceeds as follows: First, the drive circuit 12 instructed to read first data from a specific address, which in principle may be freely selectable. Subsequently, the first data is inverted and written to the same address. In a second read-out second data are now read. When comparing the first and second data with each other can now be determined whether the memory circuit 3 works normally in normal operating mode or not. If the read-out second data is inverted to the read-out first data, then the memory circuit operates 3 in normal operating mode. If the first data is not inverted to the second data, then the memory circuit has 3 that of the drive circuit 12 initiated write operation is not executed, which detects that the memory circuit 3 located in the first state. Will this condition by the detection unit 10 detected, becomes the initialization unit 11 instructed, initialization data via the drive circuit 12 to the memory circuit 3 to send. A repeated inverted write back of the data restores the original memory contents.

An advantage of the invention is the memory controller 2 and the memory circuit 3 after a loss of power for write and read operations until the initialization of the memory circuit 3 has been carried out. Furthermore, it is advantageous to detect the first or second state of the memory circuit 3 not by a separate polling sequence between the memory control circuit 2 and the memory circuit 3 whereby additional circuitry would be needed to encode or decode the query, but by determining whether normal communication as performed in the normal mode of operation with the memory circuit 3 possible or not.

1

storage system

2

Memory controller

3

memory circuit

4

Memory cell array

5

Energy-saving unit

6

bus

7

Selbstauffrischeinheit

8th

control circuit

9

state memory

10

detection unit

11

initialization

12

drive circuit

13

Further Energy-saving unit

VDD

supply voltage

Claims (17)

Memory circuit ( 3 ) with a memory cell array ( 4 ), with a control circuit ( 8th ), which when switching on the supply voltage (V _DD ) to the memory circuit ( 3 ) is set to a first state and after initialization of the memory cell array ( 4 ) is set in a second state, wherein the control circuit ( 8th ) in the first state a writing and / or reading of the memory cell array ( 4 ) and the control circuit ( 8th ) in the second state a writing and reading out of the memory cell array ( 4 ) allows. Memory circuit ( 3 ) according to claim 1, wherein the control circuit comprises a state memory which stores information depending on the first or second state. Memory circuit ( 3 ) according to claim 1 or 2, wherein the memory circuit comprises an energy-saving unit ( 5 ) to operate the memory cell array in an energy saving mode. Memory circuit ( 3 ) according to one of claims 1 to 3, wherein the memory cell array ( 4 ) DRAM memory cells, wherein the energy-saving unit ( 5 ) a self-refresh unit ( 7 ) in order to automatically refresh the DRAM memory cells cyclically in the energy-saving mode. Memory controller ( 2 ) for operating a connectable memory circuit ( 3 ) according to one of claims 1 to 4, with a detection unit ( 10 ) to the first or second state of a connected memory circuit ( 3 ), with an initialization unit ( 11 ), upon detection of the first state, the memory circuit ( 3 ) and with a drive circuit ( 12 ) to operate the memory circuit according to a normal operating mode for writing and / or reading data upon detection of the second state. Memory controller ( 2 ) according to claim 5, wherein the drive circuit is further configured to operate after initialization of the memory circuit ( 3 ) the memory circuit ( 3 ) according to a normal operating mode. Memory controller ( 2 ) according to claim 5 or 6, wherein the detection unit ( 10 ) is designed so as to use the drive circuit successively a first read operation of data from the connected memory circuit ( 3 ), a write operation with the inverted data read in the first read operation and a second read operation, wherein the first state of the memory circuit ( 3 ) is detected when the data read during the first read operation and the data read during the second read operation are not inverse to each other, and wherein the second state of the memory circuit ( 3 ) is detected when the data read during the first read operation and the data read during the second read operation are inversely related to each other. Memory controller ( 2 ) according to claim 7, wherein the detection unit ( 10 ) is designed so as to again invert the data read in the second read operation and the again inverted data in a write operation in the connected memory circuit ( 3 ) to write. Memory controller ( 2 ) according to one of claims 5 to 8, wherein the initialization unit ( 11 ) for initializing the memory circuit ( 3 ) an initialization command to the memory circuit ( 3 ) sends. Memory controller ( 2 ) according to one of claims 5 to 8, wherein the memory control unit ( 2 ) an energy-saving unit ( 13 ) in order to be displaceable in a power-saving mode with a reduced power consumption, wherein the energy-saving unit ( 13 ) with the detection unit ( 10 ) after leaving the energy-saving mode, the detection unit ( 10 ) head for. Method for driving a memory circuit ( 3 ), comprising the following steps: detecting a first or second state of a connected memory circuit ( 3 ), - initializing the connected memory circuit ( 3 ) upon detection of the first state, and - operating the connected memory circuit ( 3 ) upon detection of the second state according to a normal operation mode. Method according to claim 11, wherein after the initialization of the memory circuit ( 3 ) the memory circuit ( 3 ) is operated according to a normal operating mode. The method of claim 11 or 12, wherein the first or second state is detected by successively performing a first read of data, a write with the inverted data read in the first read, and a second read, wherein the first state of the memory circuit ( 3 ) is detected when the data read during the first read operation and the data read during the second read operation are not inverse to one another, and wherein the second state of the memory circuit ( 3 ) is detected when the data read during the first read operation and the data read during the second read operation are inversely related to each other. Method according to claim 13, wherein the data read out in the second read operation are again inverted in order to store the again inverted data in a write operation into the memory circuit ( 3 ) to write. Method according to one of claims 11 to 14, wherein for initializing the memory circuit ( 3 ) an initialization command to the memory circuit ( 3 ) is sent. A method according to any one of claims 11 to 15, wherein an energy saving mode is ingestible, wherein after leaving the energy-saving mode the Detecting the first or second state is performed. Method for operating a memory circuit ( 3 ), comprising the following steps: - assuming a first state after switching on the supply voltage (V _DD ), wherein in the first state a writing and / or reading of the memory cell array is blocked; Initializing the memory circuit ( 3 ) in the first state, - transition into a second state after initialization, wherein in the second state a writing and reading of the memory cell array ( 4 ).