DE102004040465A1 - Paketanordnung für elektronische Einrichtung und Verfahren zum Herstellen der Paketanordnung - Google Patents

Paketanordnung für elektronische Einrichtung und Verfahren zum Herstellen der Paketanordnung Download PDF

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Publication number
DE102004040465A1
DE102004040465A1 DE102004040465A DE102004040465A DE102004040465A1 DE 102004040465 A1 DE102004040465 A1 DE 102004040465A1 DE 102004040465 A DE102004040465 A DE 102004040465A DE 102004040465 A DE102004040465 A DE 102004040465A DE 102004040465 A1 DE102004040465 A1 DE 102004040465A1
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Prior art keywords
package assembly
manufacturing
electronic device
buffer layer
avoided
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DE102004040465A
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DE102004040465B4 (de
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Huang Yu-Tung
Wu Chih-Hsyong
Hsu Yung-Cheng
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Tai-Saw Technology Co Ltd
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Tai-Saw Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/058—Holders; Supports for surface acoustic wave devices
    • H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1078—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a foil covering the non-active sides of the SAW device
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    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
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    • H01L2924/351—Thermal stress

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Acoustics & Sound (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Erfindungsgemäß werden eine Pufferschicht auf einem Substrat gebildet und dann elektronische Einrichtungen auf die Pufferschicht gepackt, und Probleme einer geringen hermetischen Abdichtung und eines komplexen Prozesses nach dem Stand der Technik können vermieden werden. Die Erfindung liefert eine Packungsstruktur und ein Packungsverfahren mit einer besseren hermetischen Abdichtung und einem einfacheren Prozeß. Mittels der Pufferschicht können insbesondere die Planarisierung für Flip-Chip-Bonden verbessert und negative Effekte des Packungsprozesses vermieden werden.
DE102004040465A 2003-09-24 2004-08-20 Gehäuseanordnung für elektronische Bauelemente und Verfahren zum Verpacken elektronischer Bauelemente Active DE102004040465B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/671,334 US7239023B2 (en) 2003-09-24 2003-09-24 Package assembly for electronic device
US10/671,334 2003-09-24

Publications (2)

Publication Number Publication Date
DE102004040465A1 true DE102004040465A1 (de) 2005-05-04
DE102004040465B4 DE102004040465B4 (de) 2009-07-30

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Country Status (3)

Country Link
US (1) US7239023B2 (de)
CN (1) CN1300843C (de)
DE (1) DE102004040465B4 (de)

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DE102007058951A1 (de) * 2007-12-07 2009-06-10 Epcos Ag MEMS Package
DE102008025202A1 (de) * 2008-05-27 2009-12-10 Epcos Ag Hermetisch geschlossenes Gehäuse für elektronische Bauelemente und Herstellungsverfahren
DE102008030843A1 (de) * 2008-06-30 2009-12-31 Osram Opto Semiconductors Gmbh Optoelektronische Anordnung sowie Verfahren zur Herstellung einer optoelektronischen Anordnung
DE102010054782A1 (de) * 2010-12-16 2012-06-21 Epcos Ag Gehäustes elektrisches Bauelement

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DE102004005668B4 (de) * 2004-02-05 2021-09-16 Snaptrack, Inc. Elektrisches Bauelement und Herstellungsverfahren
KR20060115095A (ko) * 2005-05-04 2006-11-08 삼성전기주식회사 기밀특성이 우수한 표면탄성파 소자 패키지
KR100691160B1 (ko) * 2005-05-06 2007-03-09 삼성전기주식회사 적층형 표면탄성파 패키지 및 그 제조방법
US20070015300A1 (en) * 2005-07-15 2007-01-18 Yu-Chuan Liu Method for fabricating a light-emitting device
KR100722635B1 (ko) * 2005-09-27 2007-05-28 삼성전기주식회사 와이어 본딩 패드면과 볼패드면의 회로층이 다른 두께를갖는 반도체 패키지 기판 및 그 제조방법
US8283756B2 (en) * 2007-08-20 2012-10-09 Infineon Technologies Ag Electronic component with buffer layer
JP5537081B2 (ja) 2009-07-28 2014-07-02 浜松ホトニクス株式会社 加工対象物切断方法
US8021930B2 (en) 2009-08-12 2011-09-20 Stats Chippac, Ltd. Semiconductor device and method of forming dam material around periphery of die to reduce warpage
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CN1300843C (zh) 2007-02-14
DE102004040465B4 (de) 2009-07-30

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